TW200741820A - Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device

Info

Publication number
TW200741820A
TW200741820A TW095126975A TW95126975A TW200741820A TW 200741820 A TW200741820 A TW 200741820A TW 095126975 A TW095126975 A TW 095126975A TW 95126975 A TW95126975 A TW 95126975A TW 200741820 A TW200741820 A TW 200741820A
Authority
TW
Taiwan
Prior art keywords
semiconductor layer
semiconductor
manufacturing
forming
base
Prior art date
Application number
TW095126975A
Other languages
English (en)
Inventor
Kei Kanemoto
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW200741820A publication Critical patent/TW200741820A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
TW095126975A 2005-07-27 2006-07-24 Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device TW200741820A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005216873A JP4867225B2 (ja) 2005-07-27 2005-07-27 半導体基板の製造方法及び、半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW200741820A true TW200741820A (en) 2007-11-01

Family

ID=37674349

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095126975A TW200741820A (en) 2005-07-27 2006-07-24 Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device

Country Status (5)

Country Link
US (1) US7524705B2 (zh)
JP (1) JP4867225B2 (zh)
KR (1) KR100809408B1 (zh)
CN (1) CN100419954C (zh)
TW (1) TW200741820A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8017505B2 (en) * 2006-11-30 2011-09-13 Seiko Epson Corporation Method for manufacturing a semiconductor device
JP5256519B2 (ja) * 2007-05-03 2013-08-07 ソイテック 洗浄された歪みシリコン表面を作製するための改良されたプロセス
CN103117208B (zh) * 2012-07-03 2016-03-23 上海华力微电子有限公司 一种去除晶圆上SiGe薄膜的方法
CN107910264B (zh) * 2017-11-08 2020-06-30 上海华力微电子有限公司 一种全耗尽soi结构的制作方法
CN115849297A (zh) * 2022-12-27 2023-03-28 上海铭锟半导体有限公司 一种mems空腔的制备方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3216535B2 (ja) * 1996-08-30 2001-10-09 日本電気株式会社 Ｓｏｉ基板およびその製造方法
JP3114643B2 (ja) * 1997-02-20 2000-12-04 日本電気株式会社 半導体基板の構造および製造方法
KR100414217B1 (ko) * 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
JP3647777B2 (ja) * 2001-07-06 2005-05-18 株式会社東芝 電界効果トランジスタの製造方法及び集積回路素子
WO2003026019A1 (fr) * 2001-09-12 2003-03-27 Nec Corporation Dispositif a semi-conducteurs et procede de production correspondant
JP2003347399A (ja) * 2002-05-23 2003-12-05 Sharp Corp 半導体基板の製造方法
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US7026249B2 (en) * 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
US7049660B2 (en) * 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature
JP4140456B2 (ja) * 2003-06-17 2008-08-27 株式会社Ｓｕｍｃｏ 半導体基板の製造方法
US7015147B2 (en) * 2003-07-22 2006-03-21 Sharp Laboratories Of America, Inc. Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer
KR20060083218A (ko) * 2003-10-10 2006-07-20 토쿄고교 다이가꾸 반도체 기판, 반도체 장치 및 반도체 기판의 제작방법
US6955988B2 (en) 2003-12-04 2005-10-18 Analog Devices, Inc. Method of forming a cavity and SOI in a semiconductor substrate
KR100528486B1 (ko) * 2004-04-12 2005-11-15 삼성전자주식회사 불휘발성 메모리 소자 및 그 형성 방법
JP2006093268A (ja) * 2004-09-22 2006-04-06 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
US20060102204A1 (en) * 2004-11-12 2006-05-18 Tokyo Electron Limited Method for removing a residue from a substrate using supercritical carbon dioxide processing
EP1739749A2 (fr) * 2005-06-30 2007-01-03 STMicroelectronics (Crolles 2) SAS Cellule mémoire à un transistor MOS à corps isolé à effet mémoire prolongé
JP2007027231A (ja) * 2005-07-13 2007-02-01 Seiko Epson Corp 半導体装置の製造方法及び、半導体装置
JP4256381B2 (ja) * 2005-11-09 2009-04-22 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
KR20070014021A (ko) 2007-01-31
KR100809408B1 (ko) 2008-03-05
US20070026582A1 (en) 2007-02-01
US7524705B2 (en) 2009-04-28
JP2007035908A (ja) 2007-02-08
JP4867225B2 (ja) 2012-02-01
CN1905127A (zh) 2007-01-31
CN100419954C (zh) 2008-09-17

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