TW200739737A - Method of making a semiconductor structure with a plating enhancement layer - Google Patents

Method of making a semiconductor structure with a plating enhancement layer

Info

Publication number
TW200739737A
TW200739737A TW096100167A TW96100167A TW200739737A TW 200739737 A TW200739737 A TW 200739737A TW 096100167 A TW096100167 A TW 096100167A TW 96100167 A TW96100167 A TW 96100167A TW 200739737 A TW200739737 A TW 200739737A
Authority
TW
Taiwan
Prior art keywords
pel
ild
plating
making
semiconductor structure
Prior art date
Application number
TW096100167A
Other languages
English (en)
Chinese (zh)
Inventor
Shom Ponoth
Steven Shyng-Tsong Chen
John Anthony Fitzsimmons
Terry Allen Spooner
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200739737A publication Critical patent/TW200739737A/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/058Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by depositing on sacrificial masks, e.g. using lift-off
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/0425Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers comprising multiple stacked seed or nucleation layers

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
TW096100167A 2006-01-17 2007-01-03 Method of making a semiconductor structure with a plating enhancement layer TW200739737A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/306,930 US7341948B2 (en) 2006-01-17 2006-01-17 Method of making a semiconductor structure with a plating enhancement layer

Publications (1)

Publication Number Publication Date
TW200739737A true TW200739737A (en) 2007-10-16

Family

ID=38263770

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096100167A TW200739737A (en) 2006-01-17 2007-01-03 Method of making a semiconductor structure with a plating enhancement layer

Country Status (4)

Country Link
US (1) US7341948B2 (https=)
JP (1) JP4317564B2 (https=)
CN (1) CN100479130C (https=)
TW (1) TW200739737A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080113518A (ko) * 2007-06-25 2008-12-31 주식회사 동부하이텍 반도체 소자의 제조 방법
US8828878B2 (en) * 2011-06-01 2014-09-09 United Microelectronics Corp. Manufacturing method for dual damascene structure
US9312140B2 (en) 2014-05-19 2016-04-12 International Business Machines Corporation Semiconductor structures having low resistance paths throughout a wafer

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675468A (en) 1985-12-20 1987-06-23 The Standard Oil Company Stable contact between current collector grid and transparent conductive layer
US4977013A (en) * 1988-06-03 1990-12-11 Andus Corporation Tranparent conductive coatings
US5280381A (en) 1992-07-27 1994-01-18 Ford Motor Company Process for preparing a solid polymeric fast ion conducting layer for an electrochromic device
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
JP3085247B2 (ja) * 1997-07-07 2000-09-04 日本電気株式会社 金属薄膜の形成方法
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
US6162365A (en) 1998-03-04 2000-12-19 International Business Machines Corporation Pd etch mask for copper circuitization
US6197181B1 (en) 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
KR100336621B1 (ko) 2000-02-15 2002-05-16 박호군 고분자 기판 위의 인듐산화물 또는 인듐주석산화물 박막증착 방법
GB0029315D0 (en) 2000-12-01 2001-01-17 Koninkl Philips Electronics Nv Method of increasing the conductivity of a transparent conductive layer

Also Published As

Publication number Publication date
CN100479130C (zh) 2009-04-15
US20070166996A1 (en) 2007-07-19
CN101005043A (zh) 2007-07-25
US7341948B2 (en) 2008-03-11
JP4317564B2 (ja) 2009-08-19
JP2007194621A (ja) 2007-08-02

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