TW200727430A - Bumping process and etching apparatus - Google Patents

Bumping process and etching apparatus

Info

Publication number
TW200727430A
TW200727430A TW095100040A TW95100040A TW200727430A TW 200727430 A TW200727430 A TW 200727430A TW 095100040 A TW095100040 A TW 095100040A TW 95100040 A TW95100040 A TW 95100040A TW 200727430 A TW200727430 A TW 200727430A
Authority
TW
Taiwan
Prior art keywords
metal layer
layer
voltage
stacked
bumping process
Prior art date
Application number
TW095100040A
Other languages
Chinese (zh)
Inventor
Chueh-An Hsieh
Li-Cheng Tai
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW095100040A priority Critical patent/TW200727430A/en
Publication of TW200727430A publication Critical patent/TW200727430A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Weting (AREA)

Abstract

A bumping process including following steps is provided. First, a stacked metal layer composed of multiple metal layers is formed on the substrate, wherein the substrate has plural bonding pads thereon. Thereafter, a patterned photoresist layer is formed on the stacked metal layer above the bonding pads. Then, a voltage is implemented in the bottom metal layer of the stacked metal layer, and a wet etching process is performed to the stacked metal layer to remove the other metal layers exposed by the patterned photoresist layer. By adjusting the voltage, the over-etching phenomenon of the metal layers is prevented. Next, the voltage is removed and the wet etching process is resumed for the bottom metal layer to form a under ball metallurgy (UBM) layer on each bonding pad. Thereafter, a solder post is formed on the UBM layer. Furthermore, an etching apparatus suitable for the aforementioned bumping process is provided.
TW095100040A 2006-01-02 2006-01-02 Bumping process and etching apparatus TW200727430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW095100040A TW200727430A (en) 2006-01-02 2006-01-02 Bumping process and etching apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095100040A TW200727430A (en) 2006-01-02 2006-01-02 Bumping process and etching apparatus

Publications (1)

Publication Number Publication Date
TW200727430A true TW200727430A (en) 2007-07-16

Family

ID=57912754

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095100040A TW200727430A (en) 2006-01-02 2006-01-02 Bumping process and etching apparatus

Country Status (1)

Country Link
TW (1) TW200727430A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109637995A (en) * 2013-09-03 2019-04-16 日月光半导体制造股份有限公司 Board structure, encapsulating structure and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109637995A (en) * 2013-09-03 2019-04-16 日月光半导体制造股份有限公司 Board structure, encapsulating structure and its manufacturing method
CN109637995B (en) * 2013-09-03 2022-11-22 日月光半导体制造股份有限公司 Substrate structure, packaging structure and manufacturing method thereof

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