TW200727393A - Method for creating new via - Google Patents
Method for creating new viaInfo
- Publication number
- TW200727393A TW200727393A TW095100811A TW95100811A TW200727393A TW 200727393 A TW200727393 A TW 200727393A TW 095100811 A TW095100811 A TW 095100811A TW 95100811 A TW95100811 A TW 95100811A TW 200727393 A TW200727393 A TW 200727393A
- Authority
- TW
- Taiwan
- Prior art keywords
- vias
- integrated circuit
- creating new
- metal layers
- new via
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095100811A TWI292605B (en) | 2006-01-09 | 2006-01-09 | Method for creating new via |
US11/649,220 US7647566B2 (en) | 2006-01-09 | 2007-01-04 | Method for creating new via |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095100811A TWI292605B (en) | 2006-01-09 | 2006-01-09 | Method for creating new via |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200727393A true TW200727393A (en) | 2007-07-16 |
TWI292605B TWI292605B (en) | 2008-01-11 |
Family
ID=38234189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095100811A TWI292605B (en) | 2006-01-09 | 2006-01-09 | Method for creating new via |
Country Status (2)
Country | Link |
---|---|
US (1) | US7647566B2 (zh) |
TW (1) | TWI292605B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5125768B2 (ja) * | 2008-05-29 | 2013-01-23 | 富士通株式会社 | 電源網解析装置、電源網解析方法及び電源網解析プログラム |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5574853A (en) * | 1994-01-03 | 1996-11-12 | Texas Instruments Incorporated | Testing integrated circuit designs on a computer simulation using modified serialized scan patterns |
US5798937A (en) * | 1995-09-28 | 1998-08-25 | Motorola, Inc. | Method and apparatus for forming redundant vias between conductive layers of an integrated circuit |
JP4112244B2 (ja) * | 2002-03-04 | 2008-07-02 | 富士通株式会社 | 半導体集積回路素子の設計システム、プログラム、記録媒体、及び、半導体集積回路素子の設計方法 |
US20030188271A1 (en) * | 2002-04-02 | 2003-10-02 | Institute Of High Performance Computing | System and method for integrated circuit design |
US6904575B2 (en) * | 2002-06-11 | 2005-06-07 | International Business Machines Corporation | Method for improving chip yields in the presence of via flaring |
JP2004258869A (ja) | 2003-02-25 | 2004-09-16 | Denso Corp | 実装回路設計方法、実装回路設計システムおよび実装回路設計プログラム |
US20050188339A1 (en) * | 2004-02-25 | 2005-08-25 | Anderson David M. | System and method for navigating design information associated with an IC design |
-
2006
- 2006-01-09 TW TW095100811A patent/TWI292605B/zh not_active IP Right Cessation
-
2007
- 2007-01-04 US US11/649,220 patent/US7647566B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20070162883A1 (en) | 2007-07-12 |
US7647566B2 (en) | 2010-01-12 |
TWI292605B (en) | 2008-01-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |