TW200723461A - Method for manufacturing a chip package structure - Google Patents

Method for manufacturing a chip package structure

Info

Publication number
TW200723461A
TW200723461A TW094143281A TW94143281A TW200723461A TW 200723461 A TW200723461 A TW 200723461A TW 094143281 A TW094143281 A TW 094143281A TW 94143281 A TW94143281 A TW 94143281A TW 200723461 A TW200723461 A TW 200723461A
Authority
TW
Taiwan
Prior art keywords
manufacturing
substrate
chip package
package structure
wires
Prior art date
Application number
TW094143281A
Other languages
English (en)
Other versions
TWI283916B (en
Inventor
yong-fu Zhuang
Original Assignee
Taiwan Solutions Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Solutions Systems Corp filed Critical Taiwan Solutions Systems Corp
Priority to TW094143281A priority Critical patent/TWI283916B/zh
Priority to US11/807,680 priority patent/US20070228541A1/en
Publication of TW200723461A publication Critical patent/TW200723461A/zh
Application granted granted Critical
Publication of TWI283916B publication Critical patent/TWI283916B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemically Coating (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
TW094143281A 2005-08-12 2005-12-08 Manufacturing method of chip package structure TWI283916B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094143281A TWI283916B (en) 2005-12-08 2005-12-08 Manufacturing method of chip package structure
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JP5197953B2 (ja) * 2006-12-27 2013-05-15 新光電気工業株式会社 リードフレーム及びその製造方法、及び半導体装置
US7911059B2 (en) * 2007-06-08 2011-03-22 SeniLEDS Optoelectronics Co., Ltd High thermal conductivity substrate for a semiconductor device
JP5646948B2 (ja) * 2010-10-19 2014-12-24 ローム株式会社 半導体装置
KR101119306B1 (ko) * 2010-11-04 2012-03-16 삼성전기주식회사 회로기판의 제조방법
CN103907185B (zh) * 2011-08-11 2016-10-19 联达科技控股有限公司 具有多材料印刷形成的包装部件的引线载体
CN103379423B (zh) * 2012-04-20 2018-12-04 美律电子(深圳)有限公司 电子封装体的制造方法

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US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US7556984B2 (en) * 2005-06-17 2009-07-07 Boardtek Electronics Corp. Package structure of chip and the package method thereof

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