TW200721186A - Output circuit, semiconductor memory device having the same, and method of expanding a valid output data window - Google Patents
Output circuit, semiconductor memory device having the same, and method of expanding a valid output data windowInfo
- Publication number
- TW200721186A TW200721186A TW095143312A TW95143312A TW200721186A TW 200721186 A TW200721186 A TW 200721186A TW 095143312 A TW095143312 A TW 095143312A TW 95143312 A TW95143312 A TW 95143312A TW 200721186 A TW200721186 A TW 200721186A
- Authority
- TW
- Taiwan
- Prior art keywords
- bits
- output circuit
- memory device
- semiconductor memory
- read data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050113327A KR100655379B1 (ko) | 2005-11-25 | 2005-11-25 | 유효 출력 데이터 윈도우를 확장시킬 수 있는 출력회로,이를 구비한 반도체 메모리 장치, 및 유효 출력 데이터확장방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200721186A true TW200721186A (en) | 2007-06-01 |
Family
ID=37732569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095143312A TW200721186A (en) | 2005-11-25 | 2006-11-23 | Output circuit, semiconductor memory device having the same, and method of expanding a valid output data window |
Country Status (3)
Country | Link |
---|---|
US (1) | US7499341B2 (zh) |
KR (1) | KR100655379B1 (zh) |
TW (1) | TW200721186A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI402683B (zh) * | 2009-02-04 | 2013-07-21 | Via Tech Inc | 具有共享機制的資訊存取方法及其電腦系統 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100907927B1 (ko) * | 2007-06-13 | 2009-07-16 | 주식회사 하이닉스반도체 | 반도체메모리소자 및 그의 구동방법 |
US7529962B1 (en) | 2008-04-04 | 2009-05-05 | International Business Machines Corporation | System for expanding a window of valid data |
KR101187642B1 (ko) * | 2011-05-02 | 2012-10-08 | 에스케이하이닉스 주식회사 | 집적 회로의 모니터링 장치 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275444B1 (en) * | 1998-02-24 | 2001-08-14 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
JP4540137B2 (ja) | 1998-07-24 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 同期型半導体記憶装置 |
JP2001319500A (ja) * | 2000-05-10 | 2001-11-16 | Mitsubishi Electric Corp | 半導体集積回路装置 |
KR100543203B1 (ko) | 2003-03-20 | 2006-01-20 | 주식회사 하이닉스반도체 | 유효 데이타 윈도우의 조절이 가능한 반도체 메모리장치의 데이타 출력 버퍼 |
KR20040105060A (ko) | 2003-06-04 | 2004-12-14 | 삼성전자주식회사 | 유효 출력 데이터 윈도우(Valid outputdata window)를 확장시킬 수 있는 출력회로를구비하는 동기식 메모리장치 및 유효 출력 데이터 윈도우확장 방법 |
US6855607B2 (en) * | 2003-06-12 | 2005-02-15 | Advanced Micro Devices, Inc. | Multi-step chemical mechanical polishing of a gate area in a FinFET |
-
2005
- 2005-11-25 KR KR1020050113327A patent/KR100655379B1/ko active IP Right Grant
-
2006
- 2006-11-17 US US11/601,027 patent/US7499341B2/en active Active
- 2006-11-23 TW TW095143312A patent/TW200721186A/zh unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI402683B (zh) * | 2009-02-04 | 2013-07-21 | Via Tech Inc | 具有共享機制的資訊存取方法及其電腦系統 |
Also Published As
Publication number | Publication date |
---|---|
US7499341B2 (en) | 2009-03-03 |
US20070121397A1 (en) | 2007-05-31 |
KR100655379B1 (ko) | 2006-12-08 |
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