TW200709305A - Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices - Google Patents

Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices

Info

Publication number
TW200709305A
TW200709305A TW095124809A TW95124809A TW200709305A TW 200709305 A TW200709305 A TW 200709305A TW 095124809 A TW095124809 A TW 095124809A TW 95124809 A TW95124809 A TW 95124809A TW 200709305 A TW200709305 A TW 200709305A
Authority
TW
Taiwan
Prior art keywords
type
conductivity
regions
semiconductor layer
dopant
Prior art date
Application number
TW095124809A
Other languages
English (en)
Inventor
Ferruccio Frisina
Mario Giuseppe Saggio
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Publication of TW200709305A publication Critical patent/TW200709305A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
TW095124809A 2005-07-08 2006-07-07 Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices TW200709305A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05425495A EP1742249A1 (en) 2005-07-08 2005-07-08 Power field effect transistor and manufacturing method thereof

Publications (1)

Publication Number Publication Date
TW200709305A true TW200709305A (en) 2007-03-01

Family

ID=36091409

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095124809A TW200709305A (en) 2005-07-08 2006-07-07 Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices

Country Status (4)

Country Link
US (2) US7871880B2 (zh)
EP (1) EP1742249A1 (zh)
TW (1) TW200709305A (zh)
WO (1) WO2007006507A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1742249A1 (en) * 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Power field effect transistor and manufacturing method thereof
JP4412335B2 (ja) 2007-02-23 2010-02-10 株式会社デンソー 炭化珪素半導体装置の製造方法
US20100314695A1 (en) * 2009-06-10 2010-12-16 International Rectifier Corporation Self-aligned vertical group III-V transistor and method for fabricated same
JP5616665B2 (ja) * 2010-03-30 2014-10-29 ローム株式会社 半導体装置
JP5883563B2 (ja) * 2011-01-31 2016-03-15 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN103021856A (zh) * 2011-09-28 2013-04-03 比亚迪股份有限公司 具有超级结的半导体结构的形成方法及半导体结构
CN103578983A (zh) * 2012-08-01 2014-02-12 无锡华润上华半导体有限公司 场中止型绝缘栅型双极晶体管及其制造方法
DE112013006497T8 (de) * 2013-01-24 2015-11-12 Denso Corporation Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung
SE1550821A1 (sv) * 2015-06-16 2016-11-22 Ascatron Ab SiC SUPER-JUNCTIONS
CN111200025A (zh) * 2018-11-20 2020-05-26 深圳尚阳通科技有限公司 超结器件及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672407A (en) * 1984-05-30 1987-06-09 Kabushiki Kaisha Toshiba Conductivity modulated MOSFET
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
US6048759A (en) * 1998-02-11 2000-04-11 Magepower Semiconductor Corporation Gate/drain capacitance reduction for double gate-oxide DMOS without degrading avalanche breakdown
EP1009036B1 (en) * 1998-12-09 2007-09-19 STMicroelectronics S.r.l. High-voltage MOS-gated power device, and related manufacturing process
US6313482B1 (en) * 1999-05-17 2001-11-06 North Carolina State University Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein
JP3804375B2 (ja) * 1999-12-09 2006-08-02 株式会社日立製作所 半導体装置とそれを用いたパワースイッチング駆動システム
JP3913564B2 (ja) * 2002-01-31 2007-05-09 富士電機ホールディングス株式会社 超接合半導体素子の製造方法
US7067363B2 (en) * 2002-12-30 2006-06-27 Stmicroelectronics S.R.L. Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density
JP4939760B2 (ja) * 2005-03-01 2012-05-30 株式会社東芝 半導体装置
EP1742249A1 (en) * 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Power field effect transistor and manufacturing method thereof
EP1742250A1 (en) * 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Power field effect transistor and manufacturing method thereof

Also Published As

Publication number Publication date
US8174076B2 (en) 2012-05-08
WO2007006507A1 (en) 2007-01-18
US7871880B2 (en) 2011-01-18
US20110079794A1 (en) 2011-04-07
US20080185594A1 (en) 2008-08-07
EP1742249A1 (en) 2007-01-10

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