TW200705265A - A method and system for elastic signal pipelining - Google Patents

A method and system for elastic signal pipelining

Info

Publication number
TW200705265A
TW200705265A TW095111222A TW95111222A TW200705265A TW 200705265 A TW200705265 A TW 200705265A TW 095111222 A TW095111222 A TW 095111222A TW 95111222 A TW95111222 A TW 95111222A TW 200705265 A TW200705265 A TW 200705265A
Authority
TW
Taiwan
Prior art keywords
logic module
output
signal path
elastic signal
pipelining
Prior art date
Application number
TW095111222A
Other languages
English (en)
Other versions
TWI386849B (zh
Inventor
Guillermo J Rozas
Robert P Masleid
Original Assignee
Transmeta Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transmeta Corp filed Critical Transmeta Corp
Publication of TW200705265A publication Critical patent/TW200705265A/zh
Application granted granted Critical
Publication of TWI386849B publication Critical patent/TWI386849B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Advance Control (AREA)
TW095111222A 2005-03-31 2006-03-30 用於彈性信號管線化處理之方法與系統 TWI386849B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/096,354 US7724027B2 (en) 2005-03-31 2005-03-31 Method and system for elastic signal pipelining

Publications (2)

Publication Number Publication Date
TW200705265A true TW200705265A (en) 2007-02-01
TWI386849B TWI386849B (zh) 2013-02-21

Family

ID=37053716

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095111222A TWI386849B (zh) 2005-03-31 2006-03-30 用於彈性信號管線化處理之方法與系統

Country Status (3)

Country Link
US (1) US7724027B2 (zh)
TW (1) TWI386849B (zh)
WO (1) WO2006105303A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7236009B1 (en) 2004-12-01 2007-06-26 Andre Rohe Operational time extension
US7428721B2 (en) * 2004-12-01 2008-09-23 Tabula, Inc. Operational cycle assignment in a configurable IC
US7724027B2 (en) 2005-03-31 2010-05-25 Rozas Guillermo J Method and system for elastic signal pipelining
US7663408B2 (en) * 2005-06-30 2010-02-16 Robert Paul Masleid Scannable dynamic circuit latch
US20070013425A1 (en) * 2005-06-30 2007-01-18 Burr James B Lower minimum retention voltage storage elements
US7256634B2 (en) * 2005-07-06 2007-08-14 Transmeta Corporation Elastic pipeline latch with a safe mode
US7372297B1 (en) 2005-11-07 2008-05-13 Tabula Inc. Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US7495466B1 (en) 2006-06-30 2009-02-24 Transmeta Corporation Triple latch flip flop system and method
WO2008115243A2 (en) 2007-03-20 2008-09-25 Tabula, Inc. Configurable ic having a routing fabric with storage elements
US8863067B1 (en) 2008-02-06 2014-10-14 Tabula, Inc. Sequential delay analysis by placement engines
US8166435B2 (en) * 2008-06-26 2012-04-24 Tabula, Inc. Timing operations in an IC with configurable circuits
US8674721B2 (en) * 2008-09-17 2014-03-18 Tabula, Inc. Controllable storage elements for an IC
US8525550B2 (en) * 2010-10-20 2013-09-03 Robert P. Masleid Repeater circuit with multiplexer and state element functionality
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
US8984464B1 (en) 2011-11-21 2015-03-17 Tabula, Inc. Detailed placement with search and repair
CN118069218A (zh) * 2017-09-12 2024-05-24 恩倍科微公司 极低功率微控制器系统

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453708A (en) 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5610548A (en) 1995-09-08 1997-03-11 International Business Machines Corporation Split drive clock buffer
US5721886A (en) * 1995-11-30 1998-02-24 Ncr Corporation Synchronizer circuit which controls switching of clocks based upon synchronicity, asynchronicity, or change in frequency
US5880612A (en) 1996-10-17 1999-03-09 Samsung Electronics Co., Ltd. Signal de-skewing using programmable dual delay-locked loop
US6025738A (en) 1997-08-22 2000-02-15 International Business Machines Corporation Gain enhanced split drive buffer
US5930182A (en) * 1997-08-22 1999-07-27 Micron Technology, Inc. Adjustable delay circuit for setting the speed grade of a semiconductor device
US6133759A (en) 1998-06-16 2000-10-17 International Business Machines Corp. Decoupled reset dynamic logic circuit
US6154045A (en) 1998-12-22 2000-11-28 Intel Corporation Method and apparatus for reducing signal transmission delay using skewed gates
US6604807B1 (en) * 1999-02-18 2003-08-12 Hewlett-Packard Company Method and apparatus for detecting anomalous nozzles in an ink jet printer device
US6188259B1 (en) 1999-11-03 2001-02-13 Sun Microsystems, Inc. Self-reset flip-flop with self shut-off mechanism
US6799280B1 (en) * 2000-01-04 2004-09-28 Advanced Micro Devices, Inc. System and method for synchronizing data transfer from one domain to another by selecting output data from either a first or second storage device
JP2001188638A (ja) 2000-01-05 2001-07-10 Mitsubishi Electric Corp 双方向バス回路
JP2002014914A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 機能ブロック
JP4306098B2 (ja) 2000-06-30 2009-07-29 株式会社デンソー 通信装置
US6782459B1 (en) 2000-08-14 2004-08-24 Rambus, Inc. Method and apparatus for controlling a read valid window of a synchronous memory device
JP2002202347A (ja) 2000-12-28 2002-07-19 Nec Corp スキャンフリップフロップ回路
US6848060B2 (en) * 2001-02-27 2005-01-25 International Business Machines Corporation Synchronous to asynchronous to synchronous interface
US6466063B2 (en) 2001-03-20 2002-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Push-pull output buffer with gate voltage feedback loop
US6630851B2 (en) 2001-06-29 2003-10-07 Fujitsu Limited Low latency clock distribution
US6988215B2 (en) * 2001-09-14 2006-01-17 Medtronic, Inc. Method and apparatus for synchronization of clock domains
US6664807B1 (en) 2002-01-22 2003-12-16 Xilinx, Inc. Repeater for buffering a signal on a long data line of a programmable logic device
JP2003316566A (ja) * 2002-04-24 2003-11-07 Matsushita Electric Ind Co Ltd パイプラインプロセッサ
US6577176B1 (en) 2002-06-12 2003-06-10 Fujitsu Limited Complement reset latch
US6956405B2 (en) 2002-07-09 2005-10-18 Ip-First, Llc Teacher-pupil flip-flop
JP2004062281A (ja) * 2002-07-25 2004-02-26 Nec Micro Systems Ltd パイプライン演算処理装置及びパイプライン演算制御方法
US7158403B2 (en) 2004-03-04 2007-01-02 Mentor Graphics Corporation Ternary bit line signaling
JP4060282B2 (ja) 2004-03-22 2008-03-12 三菱電機株式会社 レベル変換回路、およびレベル変換機能付シリアル／パラレル変換回路
US7076682B2 (en) 2004-05-04 2006-07-11 International Business Machines Corp. Synchronous pipeline with normally transparent pipeline stages
US7119580B2 (en) 2004-06-08 2006-10-10 Transmeta Corporation Repeater circuit with high performance repeater mode and normal repeater mode
US7724027B2 (en) 2005-03-31 2010-05-25 Rozas Guillermo J Method and system for elastic signal pipelining
US7256634B2 (en) 2005-07-06 2007-08-14 Transmeta Corporation Elastic pipeline latch with a safe mode

Also Published As

Publication number Publication date
US20060220678A1 (en) 2006-10-05
WO2006105303A1 (en) 2006-10-05
TWI386849B (zh) 2013-02-21
US7724027B2 (en) 2010-05-25

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees