TW200642276A - Fan out buffer and method therefor - Google Patents

Fan out buffer and method therefor

Info

Publication number
TW200642276A
TW200642276A TW095109504A TW95109504A TW200642276A TW 200642276 A TW200642276 A TW 200642276A TW 095109504 A TW095109504 A TW 095109504A TW 95109504 A TW95109504 A TW 95109504A TW 200642276 A TW200642276 A TW 200642276A
Authority
TW
Taiwan
Prior art keywords
out buffer
fan out
method therefor
output
fan
Prior art date
Application number
TW095109504A
Other languages
English (en)
Other versions
TWI348823B (en
Inventor
Ira E Baskett
Original Assignee
Semiconductor Components Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Ind filed Critical Semiconductor Components Ind
Publication of TW200642276A publication Critical patent/TW200642276A/zh
Application granted granted Critical
Publication of TWI348823B publication Critical patent/TWI348823B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
TW095109504A 2005-03-21 2006-03-20 Fan out buffer and method therefor TWI348823B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/084,643 US7397288B2 (en) 2005-03-21 2005-03-21 Fan out buffer and method therefor

Publications (2)

Publication Number Publication Date
TW200642276A true TW200642276A (en) 2006-12-01
TWI348823B TWI348823B (en) 2011-09-11

Family

ID=37009663

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095109504A TWI348823B (en) 2005-03-21 2006-03-20 Fan out buffer and method therefor

Country Status (4)

Country Link
US (1) US7397288B2 (zh)
CN (1) CN100583636C (zh)
HK (1) HK1095671A1 (zh)
TW (1) TWI348823B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724089B1 (ko) * 2005-10-14 2007-06-04 삼성전자주식회사 반도체 시험 장치의 캘리브레이션 방법 및 반도체 시험장치
US7400193B2 (en) 2006-06-29 2008-07-15 Itt Manufacturing Enterprises, Inc. Ultra wide band, differential input/output, high frequency active splitter in an integrated circuit
CN102281078B (zh) * 2011-08-02 2013-08-21 上海贝岭股份有限公司 一种防输入短路的差分接收器电路
CN109684670B (zh) * 2018-11-28 2022-08-02 中国电子科技集团公司第五十八研究所 一种高频时钟扇出器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2666604B2 (ja) * 1991-05-31 1997-10-22 株式会社日立製作所 差動増幅器およびこれを用いたラッチ回路並びにラッチ回路を用いたメモリ装置及びその情報読み出し方法
JPH04373160A (ja) 1991-06-24 1992-12-25 Mitsubishi Electric Corp 半導体集積回路
US5825819A (en) * 1996-04-23 1998-10-20 Motorola, Inc. Asymmetrical digital subscriber line (ADSL) line driver circuit
US6104209A (en) * 1998-08-27 2000-08-15 Micron Technology, Inc. Low skew differential receiver with disable feature
US5805006A (en) * 1997-04-28 1998-09-08 Marvell Technology Group, Ltd. Controllable integrator
JPH11175183A (ja) * 1997-12-12 1999-07-02 Fujitsu Ltd 半導体集積回路におけるクロック分配回路
JPH11272786A (ja) * 1998-03-25 1999-10-08 Seiko Instruments Inc 差動増幅回路
US6188281B1 (en) * 1998-09-30 2001-02-13 Maxim Integrated Products, Inc. Linear transconductance circuits having class AB amplifiers parallel coupled with concave compensation circuits
US6338144B2 (en) * 1999-02-19 2002-01-08 Sun Microsystems, Inc. Computer system providing low skew clock signals to a synchronous memory unit
US6081162A (en) * 1999-06-17 2000-06-27 Intel Corporation Robust method and apparatus for providing a digital single-ended output from a differential input
JP2002270773A (ja) * 2001-03-12 2002-09-20 Nec Corp 半導体集積回路およびその製造方法
US6807118B2 (en) * 2003-01-23 2004-10-19 Hewlett-Packard Development Company, L.P. Adjustable offset differential amplifier
JP3920236B2 (ja) * 2003-03-27 2007-05-30 Ｎｅｃエレクトロニクス株式会社 差動増幅器

Also Published As

Publication number Publication date
US7397288B2 (en) 2008-07-08
CN100583636C (zh) 2010-01-20
HK1095671A1 (en) 2007-05-11
TWI348823B (en) 2011-09-11
US20060208771A1 (en) 2006-09-21
CN1838538A (zh) 2006-09-27

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