TW200632740A - Thread livelock unit - Google Patents

Thread livelock unit

Info

Publication number
TW200632740A
TW200632740A TW094131659A TW94131659A TW200632740A TW 200632740 A TW200632740 A TW 200632740A TW 094131659 A TW094131659 A TW 094131659A TW 94131659 A TW94131659 A TW 94131659A TW 200632740 A TW200632740 A TW 200632740A
Authority
TW
Taiwan
Prior art keywords
thread
livelock unit
thread livelock
logic
unit
Prior art date
Application number
TW094131659A
Other languages
English (en)
Other versions
TWI298458B (en
Inventor
David Burns
K Venkatraman
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200632740A publication Critical patent/TW200632740A/zh
Application granted granted Critical
Publication of TWI298458B publication Critical patent/TWI298458B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Power Sources (AREA)
TW094131659A 2004-09-23 2005-09-14 Multithreaded processor, computing system with thread livelock units and method for arbitrating livelock priority requests TWI298458B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/948,878 US7748001B2 (en) 2004-09-23 2004-09-23 Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time

Publications (2)

Publication Number Publication Date
TW200632740A true TW200632740A (en) 2006-09-16
TWI298458B TWI298458B (en) 2008-07-01

Family

ID=35997071

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094131659A TWI298458B (en) 2004-09-23 2005-09-14 Multithreaded processor, computing system with thread livelock units and method for arbitrating livelock priority requests

Country Status (7)

Country Link
US (2) US7748001B2 (zh)
JP (1) JP4603583B2 (zh)
KR (1) KR100880470B1 (zh)
CN (2) CN101031877B (zh)
DE (1) DE112005002305B4 (zh)
TW (1) TWI298458B (zh)
WO (1) WO2006034288A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421680B (zh) * 2007-05-10 2014-01-01 Memoright Memoritech Corp Parallel flash memory controller
TWI514262B (zh) * 2011-12-30 2015-12-21 Intel Corp 於處理器電路內識別及排定關鍵指令的優先次序之方法及系統

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9626194B2 (en) * 2004-09-23 2017-04-18 Intel Corporation Thread livelock unit
US7748001B2 (en) 2004-09-23 2010-06-29 Intel Corporation Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time
US7525986B2 (en) * 2004-10-28 2009-04-28 Intel Corporation Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools
US7810083B2 (en) * 2004-12-30 2010-10-05 Intel Corporation Mechanism to emulate user-level multithreading on an OS-sequestered sequencer
US7380038B2 (en) * 2005-02-04 2008-05-27 Microsoft Corporation Priority registers for biasing access to shared resources
WO2007031696A1 (en) * 2005-09-13 2007-03-22 Arm Limited Cache miss detection in a data processing apparatus
US7558946B2 (en) * 2005-12-12 2009-07-07 Intel Corporation Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach
WO2007099273A1 (en) * 2006-03-03 2007-09-07 Arm Limited Monitoring values of signals within an integrated circuit
US20090031082A1 (en) * 2006-03-06 2009-01-29 Simon Andrew Ford Accessing a Cache in a Data Processing Apparatus
JP4557949B2 (ja) * 2006-04-10 2010-10-06 富士通株式会社 資源ブローカリングプログラム、該プログラムを記録した記録媒体、資源ブローカリング装置、および資源ブローカリング方法
US7437539B2 (en) * 2006-04-14 2008-10-14 International Business Machines Corporation Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
US7434033B2 (en) * 2006-04-14 2008-10-07 International Business Machines Corporation Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
WO2007132424A2 (en) * 2006-05-17 2007-11-22 Nxp B.V. Multi-processing system and a method of executing a plurality of data processing tasks
US20080046684A1 (en) * 2006-08-17 2008-02-21 International Business Machines Corporation Multithreaded multicore uniprocessor and a heterogeneous multiprocessor incorporating the same
JP4841358B2 (ja) 2006-08-18 2011-12-21 富士通株式会社 リクエスト送信制御装置およびリクエスト送信制御方法
US7590784B2 (en) * 2006-08-31 2009-09-15 Intel Corporation Detecting and resolving locks in a memory unit
US8276151B2 (en) * 2006-09-06 2012-09-25 International Business Machines Corporation Determination of running status of logical processor
US8117618B2 (en) * 2007-10-12 2012-02-14 Freescale Semiconductor, Inc. Forward progress mechanism for a multithreaded processor
JP4691153B2 (ja) * 2008-12-10 2011-06-01 富士通株式会社 マルチコアプロセッサ,制御方法および情報処理装置
US8392667B2 (en) * 2008-12-12 2013-03-05 Nvidia Corporation Deadlock avoidance by marking CPU traffic as special
JP5035469B2 (ja) * 2009-03-31 2012-09-26 富士通株式会社 データ転送回路及びデータ転送方法
US8352561B1 (en) 2009-07-24 2013-01-08 Google Inc. Electronic communication reminder technology
US8516577B2 (en) 2010-09-22 2013-08-20 Intel Corporation Regulating atomic memory operations to prevent denial of service attack
US8898434B2 (en) 2011-11-11 2014-11-25 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Optimizing system throughput by automatically altering thread co-execution based on operating system directives
US20130332910A1 (en) * 2012-05-22 2013-12-12 Nec Laboratories America, Inc. Dynamic livelock analysis of multi-threaded programs
US9336357B2 (en) 2012-09-28 2016-05-10 Intel Corporation Secure access management of devices
JP6201591B2 (ja) * 2013-09-30 2017-09-27 富士通株式会社 情報処理装置および情報処理装置の制御方法
US9575916B2 (en) 2014-01-06 2017-02-21 International Business Machines Corporation Apparatus and method for identifying performance bottlenecks in pipeline parallel processing environment
US9424160B2 (en) 2014-03-18 2016-08-23 International Business Machines Corporation Detection of data flow bottlenecks and disruptions based on operator timing profiles in a parallel processing environment
US9501377B2 (en) 2014-03-18 2016-11-22 International Business Machines Corporation Generating and implementing data integration job execution design recommendations
US9642787B2 (en) 2014-04-25 2017-05-09 The Procter & Gamble Company Method of inhibiting copper deposition on hair
US9626749B2 (en) 2014-12-10 2017-04-18 Intel Corporation Sub-pixel modification of digital images by locally shifting to an arbitrarily dense supergrid
US10248463B2 (en) * 2015-02-13 2019-04-02 Honeywell International Inc. Apparatus and method for managing a plurality of threads in an operating system
US10496553B2 (en) * 2015-05-01 2019-12-03 Hewlett Packard Enterprise Development Lp Throttled data memory access
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US10191747B2 (en) * 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US9766946B2 (en) * 2015-11-11 2017-09-19 International Business Machines Corporation Selecting processor micro-threading mode
TWI597666B (zh) * 2015-12-28 2017-09-01 緯創資通股份有限公司 共享裝置的使用方法及資源共享系統
GB2551524B (en) * 2016-06-20 2018-08-22 Imagination Tech Ltd Livelock detection in a hardware design using formal verification
US10069949B2 (en) 2016-10-14 2018-09-04 Honeywell International Inc. System and method for enabling detection of messages having previously transited network devices in support of loop detection
US9798549B1 (en) 2016-10-31 2017-10-24 International Business Machines Corporation Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction
US10740102B2 (en) 2017-02-24 2020-08-11 Oracle International Corporation Hardware mechanism to mitigate stalling of a processor core
US10810086B2 (en) 2017-10-19 2020-10-20 Honeywell International Inc. System and method for emulation of enhanced application module redundancy (EAM-R)
US10783026B2 (en) 2018-02-15 2020-09-22 Honeywell International Inc. Apparatus and method for detecting network problems on redundant token bus control network using traffic sensor
WO2020008449A1 (en) 2018-07-02 2020-01-09 Drivenets Ltd. A system implementing multi-threaded applications
US10831563B2 (en) * 2019-03-19 2020-11-10 International Business Machines Corporation Deadlock resolution between distributed processes using process and aggregated information
CN110032453B (zh) 2019-04-19 2022-05-03 上海兆芯集成电路有限公司 用以任务调度与分配的处理系统及其加速方法
CN110058931B (zh) * 2019-04-19 2022-03-22 上海兆芯集成电路有限公司 用以任务调度的处理系统及其加速方法
CN110046053B (zh) 2019-04-19 2021-11-12 上海兆芯集成电路有限公司 用以分配任务的处理系统及其访存方法
CN110083387B (zh) 2019-04-19 2021-11-12 上海兆芯集成电路有限公司 使用轮询机制的处理系统及其访存方法
US11422849B2 (en) * 2019-08-22 2022-08-23 Intel Corporation Technology for dynamically grouping threads for energy efficiency
CN112187581B (zh) 2020-09-29 2022-08-02 北京百度网讯科技有限公司 服务信息处理方法、装置、设备及计算机存储介质
CN115408153B (zh) * 2022-08-26 2023-06-30 海光信息技术股份有限公司 多线程处理器的指令分发方法、装置和存储介质

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US621254A (en) 1899-03-14 Track-sight
JP3760035B2 (ja) * 1996-08-27 2006-03-29 松下電器産業株式会社 複数の命令流を独立に処理し、命令流単位に処理性能を柔軟に制御するマルチスレッドプロセッサ
JPH10111828A (ja) * 1996-09-27 1998-04-28 Internatl Business Mach Corp <Ibm> メモリシステム、データ転送方法
US6658447B2 (en) * 1997-07-08 2003-12-02 Intel Corporation Priority based simultaneous multi-threading
US6343352B1 (en) * 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6212544B1 (en) * 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6216178B1 (en) * 1998-11-16 2001-04-10 Infineon Technologies Ag Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6542921B1 (en) * 1999-07-08 2003-04-01 Intel Corporation Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
US6543002B1 (en) * 1999-11-04 2003-04-01 International Business Machines Corporation Recovery from hang condition in a microprocessor
US6898617B2 (en) * 1999-11-18 2005-05-24 International Business Machines Corporation Method, system and program products for managing thread pools of a computing environment to avoid deadlock situations by dynamically altering eligible thread pools
US6618825B1 (en) * 2000-04-20 2003-09-09 Hewlett Packard Development Company, L.P. Hierarchy of fault isolation timers
US6920516B2 (en) * 2000-08-31 2005-07-19 Hewlett-Packard Development Company, L.P. Anti-starvation interrupt protocol
US6880073B2 (en) * 2000-12-28 2005-04-12 International Business Machines Corporation Speculative execution of instructions and processes before completion of preceding barrier operations
US7401211B2 (en) * 2000-12-29 2008-07-15 Intel Corporation Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor
US6651158B2 (en) * 2001-06-22 2003-11-18 Intel Corporation Determination of approaching instruction starvation of threads based on a plurality of conditions
US7454600B2 (en) * 2001-06-22 2008-11-18 Intel Corporation Method and apparatus for assigning thread priority in a processor or the like
US7248585B2 (en) * 2001-10-22 2007-07-24 Sun Microsystems, Inc. Method and apparatus for a packet classifier
US6968431B2 (en) * 2001-11-15 2005-11-22 International Business Machines Corporation Method and apparatus for livelock prevention in a multiprocessor system
US7065596B2 (en) * 2002-09-19 2006-06-20 Intel Corporation Method and apparatus to resolve instruction starvation
US7000047B2 (en) * 2003-04-23 2006-02-14 International Business Machines Corporation Mechanism for effectively handling livelocks in a simultaneous multithreading processor
US20040216103A1 (en) * 2003-04-24 2004-10-28 International Business Machines Corporation Mechanism for detecting and handling a starvation of a thread in a multithreading processor environment
US7401207B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Apparatus and method for adjusting instruction thread priority in a multi-thread processor
US7748001B2 (en) 2004-09-23 2010-06-29 Intel Corporation Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time
US7437539B2 (en) * 2006-04-14 2008-10-14 International Business Machines Corporation Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
US7434033B2 (en) * 2006-04-14 2008-10-07 International Business Machines Corporation Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421680B (zh) * 2007-05-10 2014-01-01 Memoright Memoritech Corp Parallel flash memory controller
TWI514262B (zh) * 2011-12-30 2015-12-21 Intel Corp 於處理器電路內識別及排定關鍵指令的優先次序之方法及系統
US9323678B2 (en) 2011-12-30 2016-04-26 Intel Corporation Identifying and prioritizing critical instructions within processor circuitry

Also Published As

Publication number Publication date
KR100880470B1 (ko) 2009-01-28
US8276149B2 (en) 2012-09-25
WO2006034288A3 (en) 2006-11-23
TWI298458B (en) 2008-07-01
CN101334721A (zh) 2008-12-31
WO2006034288A2 (en) 2006-03-30
KR20070055554A (ko) 2007-05-30
JP2008513894A (ja) 2008-05-01
CN101031877B (zh) 2010-05-05
US20100229172A1 (en) 2010-09-09
US20060064695A1 (en) 2006-03-23
CN101031877A (zh) 2007-09-05
DE112005002305T5 (de) 2007-09-06
US7748001B2 (en) 2010-06-29
DE112005002305B4 (de) 2011-03-17
JP4603583B2 (ja) 2010-12-22
CN101334721B (zh) 2013-06-19

Similar Documents

Publication Publication Date Title
TW200632740A (en) Thread livelock unit
GB201122094D0 (en) Providing state storage in a processor for system management mode
WO2005046304A3 (en) Method and system for allocation of special purpose computing resources in a multiprocessor system
TW200745953A (en) System and method for grouping execution threads
WO2005081105A3 (en) Methods and apparatus for task management in a multi-processor system
WO2016183028A3 (en) Methods and architecture for enhanced computer performance
TW200622908A (en) System and method for sharing resources between real-time and virtualizing operating systems
WO2008155827A1 (ja) キャッシュ制御装置及び制御方法
TW200617680A (en) Establishing command order in an out of order DMA command queue
CN103605568A (zh) 一种多线程管理方法及装置
GB2485683A (en) Thread shift: Allocating threads to cores
TW200707170A (en) Power management of multiple processors
WO2005081104A8 (en) Methods and apparatus for processor task migration in a multi-processor system
WO2015050594A3 (en) Methods and apparatus for parallel processing
ATE540353T1 (de) Einteilen von threads in einem prozessor
IN2012DN00929A (zh)
HK1088417A1 (en) Processing architecture having passive threads and active semaphores
MX2016012531A (es) Area de control para gestionar multiples subprocesos en una computadora.
WO2006083543A3 (en) Multithreading processor including thread scheduler based on instruction stall likelihood prediction
EP1788486A3 (en) Cooperative scheduling using coroutines and threads
ATE459047T1 (de) Verfahren und vorrichtung zur aktivierung einer laufzeitprozessormigration mit betriebssystemunterstützung
ATE530986T1 (de) Unterbrechungsarbitrierung für multiprozessoren
EA201990877A1 (ru) Структура сертифицируемой системы управления с постоянными параметрами для приложений жесткого реального времени, критических с точки зрения безопасности, в системах бортового радиоэлектронного оборудования, с использованием многоядерных процессоров
US20180068134A1 (en) Method to isolate real-time or safety-critical software and operating system from non-critical software and operating system
WO2008083030A3 (en) Efficient resource arbitration

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees