TW200618176A - Homogeneous copper interconnects for beol - Google Patents
Homogeneous copper interconnects for beolInfo
- Publication number
- TW200618176A TW200618176A TW094131072A TW94131072A TW200618176A TW 200618176 A TW200618176 A TW 200618176A TW 094131072 A TW094131072 A TW 094131072A TW 94131072 A TW94131072 A TW 94131072A TW 200618176 A TW200618176 A TW 200618176A
- Authority
- TW
- Taiwan
- Prior art keywords
- copper
- impure
- layer
- seed layer
- beol
- Prior art date
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title abstract 8
- 229910052802 copper Inorganic materials 0.000 title abstract 8
- 239000010949 copper Substances 0.000 title abstract 8
- 230000004888 barrier function Effects 0.000 abstract 2
- 230000007547 defect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
- Chemical Vapour Deposition (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/711,700 US20060071338A1 (en) | 2004-09-30 | 2004-09-30 | Homogeneous Copper Interconnects for BEOL |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200618176A true TW200618176A (en) | 2006-06-01 |
Family
ID=36124734
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094131072A TW200618176A (en) | 2004-09-30 | 2005-09-09 | Homogeneous copper interconnects for beol |
Country Status (7)
Country | Link |
---|---|
US (2) | US20060071338A1 (zh) |
EP (1) | EP1800335A4 (zh) |
JP (1) | JP2008515229A (zh) |
KR (1) | KR20070067067A (zh) |
CN (1) | CN101023514A (zh) |
TW (1) | TW200618176A (zh) |
WO (1) | WO2006039138A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5239156B2 (ja) * | 2006-12-20 | 2013-07-17 | 富士通株式会社 | 配線形成方法及び半導体装置 |
US8492897B2 (en) * | 2011-09-14 | 2013-07-23 | International Business Machines Corporation | Microstructure modification in copper interconnect structures |
US10586732B2 (en) | 2016-06-30 | 2020-03-10 | International Business Machines Corporation | Via cleaning to reduce resistance |
US10760156B2 (en) | 2017-10-13 | 2020-09-01 | Honeywell International Inc. | Copper manganese sputtering target |
US11035036B2 (en) | 2018-02-01 | 2021-06-15 | Honeywell International Inc. | Method of forming copper alloy sputtering targets with refined shape and microstructure |
US11599804B2 (en) * | 2020-04-17 | 2023-03-07 | Disney Enterprises, Inc. | Automated annotation of heterogeneous content |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US633151A (en) * | 1898-07-07 | 1899-09-19 | Heyl & Patterson | Casting apparatus. |
US5484518A (en) * | 1994-03-04 | 1996-01-16 | Shipley Company Inc. | Electroplating process |
US6268291B1 (en) * | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
US6709562B1 (en) * | 1995-12-29 | 2004-03-23 | International Business Machines Corporation | Method of making electroplated interconnection structures on integrated circuit chips |
US6387805B2 (en) * | 1997-05-08 | 2002-05-14 | Applied Materials, Inc. | Copper alloy seed layer for copper metallization |
US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
JPH11186263A (ja) * | 1997-12-17 | 1999-07-09 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
DE69929967T2 (de) * | 1998-04-21 | 2007-05-24 | Applied Materials, Inc., Santa Clara | Elektroplattierungssystem und verfahren zur elektroplattierung auf substraten |
US6113771A (en) * | 1998-04-21 | 2000-09-05 | Applied Materials, Inc. | Electro deposition chemistry |
US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
US6071814A (en) * | 1998-09-28 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Selective electroplating of copper for damascene process |
KR100385042B1 (ko) * | 1998-12-03 | 2003-06-18 | 인터내셔널 비지네스 머신즈 코포레이션 | 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법 |
US6174799B1 (en) * | 1999-01-05 | 2001-01-16 | Advanced Micro Devices, Inc. | Graded compound seed layers for semiconductors |
US6339258B1 (en) * | 1999-07-02 | 2002-01-15 | International Business Machines Corporation | Low resistivity tantalum |
US6337151B1 (en) * | 1999-08-18 | 2002-01-08 | International Business Machines Corporation | Graded composition diffusion barriers for chip wiring applications |
US6380628B2 (en) * | 1999-08-18 | 2002-04-30 | International Business Machines Corporation | Microstructure liner having improved adhesion |
US6413858B1 (en) * | 1999-08-27 | 2002-07-02 | Micron Technology, Inc. | Barrier and electroplating seed layer |
US6331237B1 (en) * | 1999-09-01 | 2001-12-18 | International Business Machines Corporation | Method of improving contact reliability for electroplating |
US6136707A (en) * | 1999-10-02 | 2000-10-24 | Cohen; Uri | Seed layers for interconnects and methods for fabricating such seed layers |
KR20020070443A (ko) * | 1999-11-24 | 2002-09-09 | 허니웰 인터내셔널 인코포레이티드 | 전도성 상호연결장치 |
US6461225B1 (en) * | 2000-04-11 | 2002-10-08 | Agere Systems Guardian Corp. | Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP) |
US6350688B1 (en) * | 2000-08-01 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Via RC improvement for copper damascene and beyond technology |
JP2002075995A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6387806B1 (en) * | 2000-09-06 | 2002-05-14 | Advanced Micro Devices, Inc. | Filling an interconnect opening with different types of alloys to enhance interconnect reliability |
TW523870B (en) * | 2000-11-02 | 2003-03-11 | Ebara Corp | Method for forming interconnects and semiconductor device |
US6680514B1 (en) * | 2000-12-20 | 2004-01-20 | International Business Machines Corporation | Contact capping local interconnect |
KR100424714B1 (ko) * | 2001-06-28 | 2004-03-27 | 주식회사 하이닉스반도체 | 반도체소자의 구리 배선 형성 방법 |
US6472023B1 (en) * | 2001-07-10 | 2002-10-29 | Chang Chun Petrochemical Co., Ltd. | Seed layer of copper interconnection via displacement |
JP4011336B2 (ja) * | 2001-12-07 | 2007-11-21 | 日鉱金属株式会社 | 電気銅めっき方法、電気銅めっき用純銅アノード及びこれらを用いてめっきされたパーティクル付着の少ない半導体ウエハ |
KR100805843B1 (ko) * | 2001-12-28 | 2008-02-21 | 에이에스엠지니텍코리아 주식회사 | 구리 배선 형성방법, 그에 따라 제조된 반도체 소자 및구리 배선 형성 시스템 |
US6709582B2 (en) * | 2002-04-22 | 2004-03-23 | Michael Danner | Combined filter and skimmer assembly for ponds |
US6726535B2 (en) * | 2002-04-25 | 2004-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing localized Cu corrosion during CMP |
US6743719B1 (en) * | 2003-01-22 | 2004-06-01 | Texas Instruments Incorporated | Method for forming a conductive copper structure |
-
2004
- 2004-09-30 US US10/711,700 patent/US20060071338A1/en not_active Abandoned
-
2005
- 2005-09-09 TW TW094131072A patent/TW200618176A/zh unknown
- 2005-09-20 EP EP05797431A patent/EP1800335A4/en not_active Withdrawn
- 2005-09-20 WO PCT/US2005/033539 patent/WO2006039138A1/en not_active Application Discontinuation
- 2005-09-20 KR KR1020077001248A patent/KR20070067067A/ko not_active Application Discontinuation
- 2005-09-20 JP JP2007534644A patent/JP2008515229A/ja active Pending
- 2005-09-20 CN CNA2005800315706A patent/CN101023514A/zh active Pending
-
2008
- 2008-01-09 US US11/971,488 patent/US20080156636A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
KR20070067067A (ko) | 2007-06-27 |
CN101023514A (zh) | 2007-08-22 |
JP2008515229A (ja) | 2008-05-08 |
WO2006039138A1 (en) | 2006-04-13 |
US20080156636A1 (en) | 2008-07-03 |
EP1800335A1 (en) | 2007-06-27 |
EP1800335A4 (en) | 2008-01-02 |
US20060071338A1 (en) | 2006-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200723448A (en) | Interconnect structure and fabrication method thereof and semiconductor device | |
TW200618176A (en) | Homogeneous copper interconnects for beol | |
WO2009088522A3 (en) | Cobalt nitride layers for copper interconnects and methods for forming them | |
TW200739811A (en) | Interconnect structure of an integrated circuit, damascene structure, semiconductor structure and fabrication methods thereof | |
SG116638A1 (en) | A process of forming a composite diffusion barrierin copper/organic low-k damascene technology. | |
TW200629472A (en) | Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer | |
TW200717712A (en) | Technique for forming a copper-based metallization layer including a conductive capping layer | |
WO2011041522A3 (en) | Methods for multi-step copper plating on a continuous ruthenium film in recessed features | |
GB2459232A (en) | Increasing reliability of copper-based metallization structures in a microstructure device by using aluminium nitride | |
TW200707754A (en) | Wire structure, method of forming wire, thin film transistor substrate, and method of manufacturing thin film transistor substrate | |
US7879720B2 (en) | Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation | |
KR20210030910A (ko) | 쓰루 실리콘 비아 금속화 | |
US20150228555A1 (en) | Structure and method of cancelling tsv-induced substrate stress | |
SG135091A1 (en) | Entire encapsulation of cu interconnects using self-aligned cusin film | |
WO2008069832A3 (en) | Creating reliable via contacts for interconnect applications | |
TW200731463A (en) | A technique for increasing adhesion of metallization layers by providing dummy vias | |
AU2003269066A1 (en) | Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip | |
TW200740989A (en) | Semiconductor wafer cleaning solution, method for cleaning a semiconductor wafer and method for forming an interconnect structure of an integrated circuit | |
TW200518263A (en) | Method for fabricating copper interconnects | |
WO2013126458A8 (en) | Improved structures, devices and methods related to copper interconnects for compound semiconductors | |
TWI339873B (en) | Improved chemical planarization performance for copper/low-k interconnect structures | |
TW200711038A (en) | Method of forming a semiconductor device having a diffusion barrier stack and structure thereof | |
US20140024212A1 (en) | Multi-layer barrier layer for interconnect structure | |
SG128555A1 (en) | Integrated circuit system using dual damascene process | |
WO2010005592A3 (en) | Microelectronic interconnect element with decreased conductor spacing |