TW200535863A - Bit switch voltage drop compensation during programming in nonvolatile memory - Google Patents

Abstract

A method is provided of regulating a supply voltage for providing a bit line voltage in a semiconductor memory device where the bit line voltage is provided to memory cells in a bit line from the supply voltage through a bit switch. A bit line current provided to the memory cells is detected. The supply voltage is adjusted responsive to the deducted bit line current to at least partially compensate for a voltage drop across the bit switch where the voltage drop is dependent at least in part on the bit line current.

Description

200535863 13239twf.doc / 006 发明, Description of the invention: · ',, [Technical field to which the invention belongs] The present invention relates to an integrated circuit memory, which includes an array of memory cell arrays. memory cells), and circuits that provide voltage drop compensation during programming. [Prior art] FIG. 1 shows a conventional integrated circuit, which includes a flash electronic erasable and writable read-only memory (flash EEPR0M, hereinafter referred to as flash EEPR0M memory) array 100, and an array 1 〇The memory cell performs writing, erasing, reading, and overerase correction circuits. The flash EEPROM memory array 100 is composed of individual unit cells, such as unit cell 102. Each cell has a drain coupled to a bitline, such as bitline 104, and each bitline is coupled to a bitline switch circuit 106 and a row Decoder (column decoder) 108. The source cells (somxe) of the memory cell are coupled to each other and to a common source signal VSL, and the gates of each cell are connected to the column via a wordline Decoder 110. The column decoder 110 receives a voltage signal from the power supply i 12 and is controlled by a row address issued by a processor or a state machine 114, and distributes the voltage signal to a word line. . Similarly, the bit line switching circuit 106 also receives the voltage signal from the power supply 112, and is controlled by the signal from the processor 114 to distribute the specific voltage signal to the bit line. The voltage from the power supply 112 is also controlled by the signal from the processor 114. The row decoder 108 is controlled by a row address signal (column 200535863 13239twf.doc / 006 address signal) from the processing_114, and transmits the signal from a specific bit line to a sense amplifier or a comparator (comparat〇r) ) 116. The power supply 112 supplies voltage to the row decoder 108 and the bit line 104. The sense amplifier 116 also receives signals from reference cells of a reference array 118. With the signal input from the row decoder 108 and the reference array 118, the sense amplifier 116 can provide a signal to indicate the state difference between a bit line and a reference cell line. This signal It is transmitted to the processor 114 through a data latch or a buffer 120. If it is desired to write to a unit cell of the flash memory array 100, the power supply 112 will send a high-voltage gate-to-source pulse to the unit cell, and the source of the unit cell must be grounded. For example, during the writing process, a gate voltage pulse of about 10 volts is sent to a cell multiple times, each lasting about three to six microseconds, while the drain voltage of the cell is maintained at 4.5 volts. The source is grounded. This 4.5 volt bias from drain to source generates hot electrons near the drain. The high voltage pulse from the gate to the source gives the hot electrons the opportunity to overcome the energy barrier formed by the channel and a thin dielectric layer to reach the floating gate of the cell pole. This writing program, called "hot electron injection", raises the threshold voltage of the unit cell, which is the gate-source voltage required for the unit cell to conduct. In order to erase a certain unit cell of the flash memory array 100, a procedure called "Fowler-Nordheim tunneling" must be used, that is, a gate source with high negative chirp is continuously applied Extreme voltage pulses last milliseconds. For example, during the erase process, a gate voltage pulse of 200535863 13239twf.doc / 006 times -10 volts can be applied to a unit cell, while the source voltage of the unit cell is maintained at 5.5 volts, and its drain is floating. . This high-negative 値 gate-source voltage pulse allows electrons to leave the floating gate of the memory cell by the tunneling effect, thereby reducing its threshold voltage 値. After erasing, beware of a phenomenon called "over-erasing." The over-erased unit cell will generate leakage current below the gate-source voltage of 0 volts because the threshold voltage is too low. Leakage from the cell can cause bit line currents that cannot be ignored, resulting in read and write errors. Therefore, 'erase correction is needed to reduce this bit line current. During over-erasing correction 'In the flash memory array 100, all cells coupled to the same bit line have the same gate-source voltage, and the source is always grounded, and the drain voltage is set to About 5 volts. Hot electrons are injected into the floating gate to increase the critical voltage of these cells 胞. During the writing process, the current on a bit line is the sum of the output current of the cell in the writing state and the current of other unselected cells on the same bit line. Generally, the gate-source voltage of the unselected cell is the ground level. In the over-erase correction, the current on a bit line is the sum of the currents of all the cells coupled to the bit line. If the over-erase correction is performed by the bit line, all cells will have the same gate-source voltage. If the over-erase correction is performed by the unit cell, the gate-source voltage of the selected unit cell will be different from other unit cells. A cell's floating gate stores a data bit 'and goes through the aforementioned writing and erasing steps. After writing, the critical voltage of the unit cell is usually maintained above about 5.0 volts, and the critical voltage of the unit cell after erasing is usually below about 3.0 volts. If you want to read a unit cell, you must apply a gate voltage between 3_0 volts and 6.5 volts. 200535863 13239twf.doc / 006 The control gate voltage is usually 5 volts. The 5 volt read pulse will be input to the gate of an array cell, and a reference cell 118 with a critical voltage close to 3.5 volts. In the array 100, the critical voltage of the written unit cell is greater than 5.0 volts, and its output current will be less than the current supplied by the reference unit cell of the critical 3.5 volts, indicating that the memory unit cell has written data. The critical voltage of the erased cell is lower than 3.0 volts, and its output current will be greater than the reference cell with a critical threshold of 3.5 volts, indicating that the memory cell has been erased. When confirming writing or erasing, the read voltage is also input to a cell of the memory array and a cell of the reference array 118. For write confirmation, a reference cell with a critical 値 5.0 volt is used for comparison, and for erase confirmation, a reference cell with a critical 値 3.0 volt is used for comparison. FIG. 2 is a partial circuit diagram of the flash memory. In particular, two bit lines 104 are shown, each of which includes two unit cells 102, and bits are generated at the drain of each unit cell 102 during write and overwrite corrections. Circuit related to the element line voltage VBL (labeled VBLo to VBLn). The common source line is grounded in the figure. Although only two bit lines 104 and two word lines are shown in the figure, the actual memory array can contain any number of bit lines and word lines' and therefore any number of unit cells. Individual word line signals WLo to WLn are coupled to the control gate of each cell 102. The row decoder (Figure 1) selects multiple bit lines to activate the bit switch 124 attached to each bit line. Turning on a bit switch 124 will activate the corresponding bit line 104 'and the corresponding cell 102 can be activated by a word line signal. The billion-body array usually also includes a plurality of input / output terminals (1/0). For example, a byte mode requires eight 'word modes and sixteen words. Each input and output terminal contains multiple bit lines 104, and each input and output terminal 200535863 13239twf.doc / 006 will select a bit line for ejection or writing, that is, in bit One bit line is selected for each of the eight input and output terminals of the group mode (eight bit lines and eight bits in total), and one bit line is selected for each of the sixteen input and output terminals of the character mode (a total of sixteen Bit lines and sixteen bits), read or write. Each input and output end corresponds to an internal data line signal DL (labeled DL [0] to DL [n]) and a plurality of bit lines. Although FIG. 2 only shows one bit line 104 for each input and output terminal, in fact, the signal DL [n] is a global signal shared by multiple local bit lines coupled to the same input and output terminal. ) 'Signal DL [0] is also a global signal shared by multiple regional bit lines coupled to the same input and output. If a cell 102 of a bit line 104 at an input-output terminal is to write "0", the corresponding P-type metal-oxide-semiconductor (M0S) transistor QPL attached to the input-output 5 It will open. If the cell is to be written as "丨", the corresponding P-type metal-oxide-semiconductor QPL attached to the input and output terminals will be turned off. The power supply 112 (also shown in FIG. 1) may include a charge pumping circuit or an external power supply, so as to provide bit line current during write or erase correction. One of them is to use a differential amplifier 122 so that the supplied voltage VDQ1 is controlled to approach the target drain voltage 値 VDQ2. The bit switch 124, which is not shown in the figure as pass gate transistors QbsO, Qbsl, Qbs2, is turned on by the high voltage VPP output from the row decoder 108, so that the voltage VDQ2 passes to the regional bit line 104. In the illustrated example, each bit switch 124 includes three metal-oxide half-transistors. The actual number of transistors may vary depending on the design of the wafer. The target value of the voltage VDQ2 is set to ((Ra + Rb) / Ra) * VR. VR is a reference voltage of 200535863 13239twf.doc / 006, which can be provided by a reference voltage sub-circuit (not shown). The capacitor 126 is coupled between VDQ2 and a ground line (gioimd). The capacitor 126 can reduce the fluctuation range of VDQ2 when VDQ1 is pumped. If VDQ2 exceeds the target 値 ’, especially when the charge pump circuit has just generated VDQ2, the leakage path cirxuit 128 will channel VDQ2 to avoid excessive voltage. The capacitor 130 is coupled between the gate of the P-type metal-oxide semiconductor transistor QP0 and VDQ2. Capacitor 130 will instantly react VDQ2 to QP0. The bit switch I24 in the figure is driven by a high voltage VPP, and during write and overwrite correction, VDQ2 is allowed to enter the area bit line. The transistor size of the bit switch 124 is generally limited to save area. During the writing and over-erasing corrections, when the current passes through the P-type metal-oxide-semiconductor QPL and bit switch 124 of each bit line, a voltage drop will occur. Is proportional to the magnitude of the current, that is, the greater the bit line current, the greater the voltage drop. This voltage drop will reduce the regional bit line voltage VBL (labeled VBLo to VBLn in the figure) below the target voltage VDQ2. Because the current of the unit cell 102 is increased, the writing ability will be greatly reduced in the initial stage of writing. Over-erase corrections are also adversely affected. When a unit cell is written gradually, the unit cell will accumulate charges, which will cause the unit cell current to gradually decrease. Once the area bit line current is reduced, the area voltage VBL will rise to approach VDQ2. The pressure drop of the VBL will also impact the erase correction. The efficiency of over-erase correction will be greatly reduced, which may cause failure, that is, the 'memory cell cannot successfully over-erase within the preset time limit. The circuit writing technique 'as described above and illustrated in FIG. 2 does not provide a fixed VBL when writing to each cell 102. If VDQ2 is increased in the design to compensate for the voltage drop across the bit switch 124, and there is still a problem with reliable scolding when the bit line current is reduced by writing or over-erasing the correction 200535863 13239twf.doc / 006. Reliability problems include the generation of interface state. This reduces the durability of the cell. If VBL rises too close to VDQ2, it may cause a soft program on the unselected unit cell on the selected bit line, resulting in hot holes that impact the silicon-silicon dioxide interface ( Si-Si02 interface), and generate an interface state. The state of the unit cell at this interface will impact the critical voltage of the unit cell and change the erasing and writing characteristics of the unit cell. Therefore, we need a circuit and method to provide bit line voltages that are not easily affected by the cell current to a single or multiple memory cell. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for controlling a supply voltage, which provides a bit line voltage in a semiconductor memory device, wherein the bit line voltage is Supply to the memory cell belonging to the bit line. This method detects the bit line current supplied to the memory cell. The supply voltage is adjusted with the detected bit line current to compensate at least part of the voltage drop through the bit switch, and this voltage drop is at least partially affected by the bit line current. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings. [Embodiment] FIG. 3 shows a circuit for supplying a bit line voltage VBL, which is not easily affected by a bit line current change, to a memory cell 102 belonging to the bit line 104. The circuit in Figure 3 is almost the same as that in Figure 2. The same components use the same reference numerals. The difference is that Figure 3 does not show capacitors 126 and 130. 11 200535863 13239twf.doc / 006 does not show the leakage path circuit (leakage path circuit ) 128 is shown, and the array 1000 includes a bit line current detection and reference voltage adjustment circuit (hereinafter referred to as “detection and adjustment circuit”) 200, which supplies a reference voltage VRp to a differential amplifier 122 . The detection and adjustment circuit 200 detects the total bit line current j from the transistor QP0 to be supplied to the cell 102, and adjusts the potential of the reference voltage VRP according to the size of the total bit line current I to compensate for the crossing The voltage drop of the bit switch 124 and the I / O selection transistor QPL. The reference voltage VRP is input to the differential amplifier 122 to control the potential of VDQ2, and then the potential of the regional bit line voltage VBL. When a large amount of total bit line current passes through the P-type metal-oxide-semiconductor (M0S) transistor QP0, VRP will rise to increase VDQ2 to offset the increased voltage drop across the bit switch 124 And increase the regional voltage VBL. This method is illustrated in more detail in the embodiment of FIG. Referring to FIG. 4, the detection and adjustment circuit 200 includes a current mirror circuit, such as a small P-type metal-oxide semiconductor transistor QP1, which is irradiated with a fixed reduction ratio (M). Total bit line current I. The reduced current i is equal to I (total bit line current) / M. In one embodiment, M is between about 10 and 50. A resistor Rt (preferably adjustable, described in detail later) is coupled between a fixed reference voltage VR and a current mirror to increase the voltage i * Rt above VR, thereby supplying the adjusted reference voltage VRP, and VRP Controlled by fixed voltage VR and total bit line current 1. Basically, the voltage VRP system includes a fixed component (VR) and a variable component (i * Rt) controlled by the total bit line current 1. As mentioned earlier, the reference voltage VRP is controlled by the differential amplifier 122 to control the potential of 12 200535863 13239twf.doc / 006 VDQ2. The P-type metal-oxide semiconductor transistors QP2 to QPn of the detection and adjustment circuit 200 can be used to increase the voltage VDP to approach VDQ2, so that the current mirror QP1 operates under the same bias condition as QP0, so that the current mirror's role is approached perfect. Because VRP is partly affected by the total bit line current I, a large amount of total bit line current I will accumulate a proportionally large voltage above VR, the amount of which is i * Rt (or (I / M) * Rt). This voltage increase will be reflected in VDQ2 and compensate for the voltage drop across the voltage switch in the activated bit line, especially during the initial write phase. At this time, VBL may drop below the target voltage due to a large voltage drop. When the cell current is reduced due to writing or over-erase correction, the total bit line current I also decreases, resulting in a reduction in the mirror current i, which in turn causes a reduction in the voltage i * Rt accumulated over VR, Therefore, the voltages VRP and VDQ2 must be reduced accordingly to prevent the memory cell 104 from being overloaded. How to determine the size of the P-type metal-oxide semiconductor and the resistance of Rt in the circuit 200 will be described later. It is assumed that a plurality of bit lines 104 coupled to a plurality of input / output terminals (I / O) are all represented by a single bit line model. The equivalent resistances of the plurality of parallel bit switches 124 and the P-type metal-oxide semiconductor transistor QPL activated in any write event are Req. The total current I flows through Req. Assuming VD = VRP, then (Ra / (Ra + Rb)) * VDQ2 = VRP. VRP is also equal to (I / M) * Rt + VR. VDQ2 is also equal to VBL + I * Req. Therefore, (Ra / (Ra + Rb)) * (VBL + I * Req) = VR + (I / M) * Rt. The bit line voltage VBL is usually set equal to ((Ra + Rb) / Ra) * VR, where VR is a fixed voltage. From this equation, (Ra / (Ra + Rb)) * I * Req = (I / M) * Rt. So Rt = ((M * Ra) / (Ra + Rb)) * Req. It is further assumed that when only one cell is written, Req can be set to "Req per cell"-that is, the QPL of a selected bit line 104 and the equivalent resistance of its bit switch 124. The transistor QP2 13 200535863 13239twf.doc / 006 should preferably be large enough so that its resistance is negligible compared to Rt. The voltage at node VDP is preferably close to VDQ2 to provide a perfect current mirror approaching theory, but this is not necessary. In the P-type metal-oxide-semiconductor QP2 to QPn between the nodes VRP and VDP, more transistors can be added to increase the voltage VDP, make it approach VDQ2, and make QP1 have a bias condition similar to QP0. . The conductive path between the nodes VDP and VRP must be opened to limit the number of P-type metal-oxide semiconductors used in the detection and adjustment circuit 200. The N well bias of the P-type metal-oxide-semiconductor QPn coupled to the node VRP must be higher than the voltage of VRP, because the P-type metal-oxide-semiconductor N-well of QPn must have a higher voltage than its source and drain. Voltage to avoid opening the pn junction of the source or drain. This voltage is hereinafter referred to as the voltage VCX. During the writing process, as individual cells complete writing, the total potential current I will gradually decrease from the initial writing state. In addition, when some unit cells finish writing and some unit cells are not written, the total bit line current I also decreases. The cells that have been written are open circuit, and their corresponding switches QPL become open after writing and are isolated from node VDQ2. When some cells finish writing, the voltage drop across the bit switch 124 and the P-type metal-oxide-semiconductor QPL will not change due to the written cell, but the voltage (i * Rt) accumulated above VR ) Will decrease due to the decrease of the total current I, so VDQ2 appears to decrease as expected. Once VDQ2 decreases, the area voltage VBL of the cell still being written may not reach the target value. In order to avoid this effect, the resistor Rt can preferably be adjusted so that it can reflect the number of unit cells that have been written. When the individual cell finishes writing, the current I gradually decreases, and the resistance R of the resistor Rt will increase as it adjusts the relationship between the variable voltage component of VRP and the total bit line current to compensate for the reduced total bit line. The current, although the variable voltage component, will be immediately affected by the change in the line current after the total bit 14 200535863 13239twf.doc / 006. However, Zeng Guo's resistor 确保 can ensure that the changing voltage component of VRP has a substantial effect. In one embodiment of FIG. 5, each input and output terminal returns a signal PDN to indicate whether the address cell in the selected bit line is in a written state. The signal PDN is then used to adjust the resistance of Rt, as shown in Figure 5. The signal PDN may be generated using a reference array 118 and a sense amplifier 116 according to the aforementioned technology, or other methods known to those skilled in the art of confirming the write state of a memory cell. These control signals are shown in FIG. 5 as PDN [0] to PDN [n] in the adjustment circuit 500 in the detection and adjustment circuit 200. The adjustment circuit 500 includes a plurality of resistors R connected in parallel. These resistors can be selectively added or removed from the parallel combination by a transistor switch triggered by the control signal PDN to change the resistance 値 of Rt. As mentioned above, each signal of PDN [0] to PDN [n] corresponds to the writing state of an addressed cell of a selected bit line to another input / output terminal. If a memory cell of an input / output terminal is already in the writing state, the signal PDN [n] in the corresponding adjustment circuit 500 will be set to a low level, the corresponding switch will be opened, and the corresponding resistor R will be removed from the adjustment circuit. The parallel combination of 500 is removed to increase the resistance R of the adjustment circuit 500 to maintain the voltage i * Rt, although the total bit line current I will gradually decrease as the cell finishes writing. Basically, when the current i decreases as each cell finishes writing, the resistance Rt increases to maintain the relative strength of the voltage i * Rt, which then affects VRP (ie, VR + i * Rt). However, it should be noted that, in the embodiment of FIG. 5, the resistance 値 of Rt is gradually changed, instead of changing immediately with the current i. Once Rt changes because one cell has finished writing, Rt remains unchanged until the next cell completes writing. VRP will continue to track the change of current i at a rate set by Rt resistance 値 200535863 13239twf.doc / 006 until R and t change. Once the writing of the next cell is completed, the corresponding resistor R will be removed from the parallel combination of the circuit 500 to increase the resistance t of Rt and the degree to which the variation component of VRP changes instantaneously with the current i. Letting the resistance of Rt increase as each cell finishes writing can ensure that the voltage VRP continues to meaningfully track changes in the total bit line current I. For example, it is assumed that the writing is performed in bytes. If five cells of the eight cells are not written, five of the eight signal PDNs will trigger the switches in the circuit 500 so that Rt is equal to the equivalent resistance of the five resistors R connected in parallel. During the writing process of these five unit cells, VRP and VDQ2 will track the changes in current I in real time to the extent set by the temporarily fixed Rt 値. Once one of the five cells is written, the corresponding signal PDN will open one of the corresponding switches in circuit 500 to increase the equivalent resistance of Rt, and when VRP and VDQ2 are written in the remaining four cells, That is, the degree to which the current I changes is tracked. In one embodiment, according to the formula derived previously for Rt, the resistance 每个 of each resistor R is M * (Ra / (Ra + Rb)) * (per cell Req). As mentioned earlier, for a written cell or 10, the bit switch path can be closed by the signal PD [n], which is coupled to the 0 control gate of the P-type metal-oxide semiconductor transistor QPL. Each signal PD is in the opposite state of the corresponding signal PDN, its logic high potential is set to VDQ2, and its logic low potential is set to VSS. Although not shown, the memory circuit of FIG. 5 still includes a leakage path grounded from the node VDQ2 as shown in FIG. 2 to reduce the excessively high phenomenon of VDQ2 mentioned in the related description of FIG. 2. However, this current is mirrored in the circuit 200 by a P-type metal-oxide semiconductor transistor QP1 which detects the bit line current. In order to remove the influence of leakage current, the leakage current circuit can be turned on for a certain period of time, such as one microsecond, to stabilize the VDQ2 potential, and then turn off the leakage current. 16 200535863 13239twf.doc / 006 circuit. The time limit can be controlled by a timing electric chanting (not shown). You can use a timer that generates a clock control signal for the write pulse, over erase pulse, and erase pulse. In this time limit, the input of the differential amplifier 122 may be set to VR instead of VRP, which is equivalent to cutting off the coupling between the detection and adjustment circuit 200 and the differential amplifier 122, and setting VDQ2 to fixed 値. After the time limit, the VRP will be coupled to the differential amplifier. In addition, a small leakage path circuit 'can be opened to replace the original leakage path circuit to avoid VDQ2 being too high. As known to those familiar with the prior art circuit of FIG. 2, the leakage path circuit may consist of one or more N-type metal-oxide semiconductor transistors coupled in series to node VDQ2. If the voltage of VDQ2 is too high, the current will enter the ground through the N-type metal-oxide semiconductor transistor. Once the potential of VDQ2 is stabilized and a smaller N-type metal-oxide semiconductor transistor is coupled to the node VDQ2, the leakage current can be reduced. FIG. 6 illustrates that the resistors R in the adjustment circuit 500A can be implemented by transistors, and the size of these transistors conforms to this ratio: (Ra / (Ra + Rb)) * M * (— bit switch of a bit line 124 transistor and the equivalent resistance of the input and output switch QPL). Compared with the use of resistors, this design has the advantage of better temperature compensation, that is, these transistors have the same temperature coefficient as the transistors in the bit switch. Table 1 below The contents of -1 and 1-2 are the results of software simulation of the prior art circuit of FIG. 2, where VCC (voltage of power supply), temperature and reference voltage VR are shown in the table. The row position "G" is the gate voltage of the P-type metal-oxide semiconductor transistor QP0. The following table records two conditions-(1) only one erased unit cell needs to be written, or only one bit line needs to be erased and corrected, and (2) eight erased unit cells need to be written , Or eight bit lines need erasure correction. 17 200535863 13239twf.doc / 006 The following table shows that when a current of approximately 0.3 to 0.00 milliamps (mA) passes through a bit line, the bit line voltage VBL will decrease compared to the fixed voltage VDQ2 of the controlled tube About 0.4 to 0.6 volts. "0 mA" indicates that the selected cell to be written is already in a post-write state, and the remaining cells' coupled to the same bit line have no leakage current during the writing process. Alternatively, “0 mA” indicates that during the over-erase correction process, all the unit cells on the selected bit line have no leakage current. Table 1-1. VCC / temperature = 3.6 volts / 0 degrees Celsius; VR = 1.2 volts. Among them, the unit of voltage "V" is volt, and the unit of current "mA" is milliampere.

VDQ1 VDQ2 Number of input and output terminals to be written Total bit line current G VBL 6V 4.67V 1 0mA 5.2V 4.67V 4.66V 0.3 15mA 5.07V 4.26V 4.67V 8 0mA 5.2V 4.67V 4.66V 2.53mA 4.81V 4.25V 8V 4.69V 1 0mA 7.24V 4.69V 4.67V 0.317mA 7.10V 4.27V 4.69V 8 0mA 7.24V 4.69V 4.65V 2.52mA 6.86V 4.26V Table 1-2. VCC / temperature = 2.5 Volts / 90 degrees Celsius; VR = 1.2 Volts. The voltage unit "V" is volts and the current unit "mA" is milliamperes. 200535863 13239twf.doc / 006

VDQ1 VDQ2 Number of input and output terminals to be written Total bit line current G VBL 6V 4.68V 4.66V 1 j ----〇mA 5.4V 4.68V 〇.344mA 5.22V 4.1 IV 4.68V 4.65V 8 〇mA 5.4V 4.68V 2.74mA 4.89V 4.11V 8V 4.70V 4.67V 1 〇mA 7.44V 4.70V 〇3444ηη 7.25V 4.12V 4.70V 4.65V 8 〇mA 7.44V 4.70V 2.74mA 6.94V 4.10V The following table 2-1 And 2-2 shows the software simulation result of the circuit of FIG. 6, where the resistance of the bit switch is simulated by a resistor. The following table shows two conditions: (1) only one erased unit cell needs to be written, or one bit line needs to be erased and corrected, and (2) eight erased unit cells need to be written, Or eight bit lines need erasure correction. Table 2 and 2_2 show that when the total bit line current increases, the VBL changes _ VRP plane decreases, and also shows the change of VDQ2 when the total bit line current increases or decreases. The simulation results show that in each simulation, due to The VBL caused by the change of the bit line current does not exceed 0.17 volts. The simulation process assumes that the temperature coefficient of the resistor Rt is 1000 parts per million (ppm) / degrees Celsius. The voltage VBL in the table shows 200535863 13239twf when the bit line current is not 0 (that is, the bit line is being written or erased), and there is no current on the bit line, and the QPL is in the "on" state. doc / 006 bit line voltage. When there is no current on the bit line and the QPL is in the “on” state, the voltage of VBL will be equal to VDQ2. Table 2-1. VCC / temperature = 3.6 volts / degrees Celsius; VR = 1.2 volts. Among them, the unit of voltage "V" is volt, and the unit of current "mA" is milliampere.

VDQ1 VDQ2 Number of input and output terminals to be written VRP Total bit line current VBL G VDP 6V 4.76V 1 1.22V 0mA 4.76V 5.2V 4.12V 5.24V 1.34V 0.33mA 4.79V 5.05V 4.63V 4.68V 8 1.20V 0mA 4.68V 5.2V 4.09V 5.12V 1.32V 2.59mA 4.68V 4.78V 5.0V 8V 4.77V 1 1.22V 0mA 4.77V 7.23V 4.11V 5.23V 1.34V 0.33mA 4.78V 7.09V 4.61V 4.70V 8 1.20V 0mA 4.70 V 7.24V 4.08V 5.09V 1.31V 2.61mA 4.66V 6.84V 4.98V

VDQ1 VDQ2 Number of input and output terminals to be written VRP IU — ▲▲ Total bit line current VBL G VDP 6V 4.76V 1 1.22V 0mA 4.76V 5.4V 3.29V 5.36V 1.37V 0.36mA 4.71V 5.19V 4.02V 4.69V 8 1.20V 0mA 4.69V 5.4V 3.27V 5.14V 1.36V 2.87mA 4.65V 4.83V 4.53V 8V 4.77V 1 1.22V 0mA 4.77V 7.43V 3.27V 5.22V 1.33V 0.36mA 4.60V 7.24V 3.91V 4.71V 8 1.20V 0mA 4.71V 7.44V 3.24V 5.21V 1.34V 2.88mA 4.60V 6.91V 4.47V Table 2-2. VCC / temperature = 2.5 Volts / 90 degrees Celsius; VR = 1.2 Volts. Its ί-electricity, the unit ", ν · ^ Αί cant, the current unit" mA "is milliampere.

20 200535863 13239twf.doc / 006 The following tables 3-1 and 3-2 show f: The software simulation result of the circuit of Figure 6 'is to simulate the resistance of the bit switch with a transistor. The following table shows two conditions: (1) only one erased unit cell needs to be written, or one bit line needs to be erased and corrected, and (2) eight erased unit cells need to be written ' Or eight bit lines need erasure correction. The results in Tables 3-1 and 3-2 are similar to those in Tables 2-1 and 2-2, where the VBL is relatively stable (that is, the maximum VBL change caused by the change of the total bit line current is only about 0.2 volts). Table 3-1. VCC / temperature = 3.6 volts / 0 degrees Celsius; VR = 1.2 volts. among them

The voltage unit "V." is volts, and the current 11 digits "m A" is milliamps c ► VDQ1 VDQ2 needs to be written in the total VRP bit VBL G (the input voltage of the gate VDP and the output voltage of the pole) 6.2V 4.77V 1 1.22V 0mA 4.77V 5.36V 4.01V 5.37V 1.38V 0.29mA 4.97V 5.16V 4.61V 4.68V 8 1.20V 0mA 4.68V 5.36V 3.98V 5.25V 1.35V 2.28mA 4.86V 4.74 V 5.0V 8V 4.80 V 1 1.22V 0mA 4.80V 7.17V 3.99V 5.38V 1.38V 0.29mA 4.97V 6.97V 4.61V 4.69V 8 1.20V 0mA 4.69V 7.17V 3.97V 5.24V 1.35V 2.28mA 4.85V 6.57V 4.99V Table 3- 2. VCC / temperature = 2.5 Volts / 90 degrees Celsius; VR = 1.2 Volts. The voltage unit "V" is volts and the current unit "mA" is milliamperes. 21 200535863 13239twf.doc / 006

VDQ1 VDQ2 Number of input and output terminals to be written VRP, total bit line current VBL G (gate voltage) VDP 6.2V 4.78V 1 1.22V 0mA 4.78V 5.56V 3.11V 5.48V 1.41V 0.3 1 mA 4.92V 5.30V 3.95V 4.69V 8 1.20V 0mA 4.69V 5.56V 3.10V 5.38V 1.39V 2.47mA 4.83V 4.75V 4.47V 8V 4.80V 1 1.22V 0mA 4.80V 7.38V 3.10V 5.56V 1.42V 0.31mA 4.98V 7.11V 4.00 V 4.68V 8 1.20V 0mA 4.68V 7.36V 3.10V 5.31V 1.37V 2.48mA 4.77V 6.59V 4.44V FIG. 7 shows another embodiment of the circuit 200, the voltage of which is controlled by the total bit line current VDQ2. In this embodiment, the positive input terminal of the differential amplifier 122 is connected to the voltage VBLRP. In the adjustment circuit 500B, VBLR is set to VR * (Ra + Rb) / Ra. VBLRP is equal to VBLR + i * Rt. The circuit in Figure 7 uses VDQ2 as the input to the differential amplifier, that is, VDQ2 is coupled to the negative input of the differential amplifier through a feedback line. This circuit has the same VBL control effect as the circuit of Figure 6 described earlier. VBLRP is a reference voltage that generates voltage VDQ2. The resistance of the analog bit switch is M times greater than the resistance of the bit line switch itself, rather than M * Ra / (Ra + Rb) times. The N-well of the P-type metal-oxide semiconductor transistor Qpn coupled to VBLR should have a voltage VCXX higher than VBLR. For the reason, please refer to the description of voltage VCX in FIG. 6 above. 22 200535863 13239twf.doc / 006 As mentioned above, it should be seen that the present invention, the sun and the moon, provide a circuit and method to make the regional bit line voltage less susceptible to changes in the total bit line current. The method is to compensate the bit The voltage loss on the element line, such as the loss of the bit line switch across the enabled bit line, improves the write and over-erase correction efficiency, and the cell life. In one embodiment, the variation of the regional bit line voltage VBL due to the variation of the total bit line current from the power supply is less than about 0.2 volts. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined by the scope of patent application attached to the Spring View. [Simplified description of the figure] Figure 1 shows a conventional typical embodiment, which includes a flash EEPROM memory array, and The array performs integrated circuits of write, erase, read, and over-erase correction circuits. Fig. 2 is a circuit diagram of a conventional circuit that supplies bit line voltage to a memory cell in a flash EEPROM memory array during writing and erasing correction. φ FIG. 3 is a circuit design diagram showing a voltage for supplying a fixed bit line. 4 to 7 illustrate embodiments of the circuit design of FIG. 3. [Schematic description] 100, 1000: memory array 102: memory cell 104: bit line 106: bit line switching circuit 108: row decoder 23 200535863 13239twf.doc / 006 110: column decoder Λ 112 : Power supply or charge pump circuit 114: processor or state machine 116: sense amplifier 118: reference array 120: data latch or buffer area 122: differential amplifier 124: bit switch 126, 130: capacitor 128: leakage path circuit 200: Bit line current detection and reference voltage adjustment circuits 500, 500A, 500B: adjustment circuits R, Ra, Rb, Rt: resistors

Req: Equivalent resistance D: Metal-oxide semiconductor transistor drain G: Metal-oxide semiconductor transistor gate S: Metal-oxide semiconductor transistor source

QbsO, Qbsl, Qbs2: N-type metal-oxide semiconductors QP0, QP1, QP2, QP3, QPLo, QPLn, QPn: P-type metal-oxide semiconductors I, i: Current DL (0), DL (n), PD [0], PD [n], PDN [0], PDN [n], VBLo, VBLn, VBLR, VBLRP, VCC, VCX, VCXX, VD, VDP, VDQ1, VDQ2, VPP, VR, VRP, VSL, WLo WLn · Voltage signal 24

Claims (1)

200535863 13239twf.doc / 006 Patent application scope: 1. A method for controlling the supply voltage, which is to provide a bit line voltage in a semiconductor memory device, the bit line voltage comes from the supply voltage, and After passing through a one-bit switch, the memory cell is supplied to a plurality of one-bit lines. The method includes the following steps: detecting a one-bit line current supplied to the memory cells; and The detected bit line current adjusts the supply voltage to at least partially compensate the voltage drop across the bit switch, and the voltage drop is at least partially affected by the bit line current. 2. The method for controlling the supply voltage as described in item 1 of the scope of patent application, wherein the adjustment step includes: if an increase in the bit line current is detected, increasing the supply voltage, and if the bit is detected When the element current decreases, the supply voltage is reduced. 3. The method for controlling the supply voltage as described in item 1 of the scope of the patent application, further comprising adjusting the supply voltage to maintain a bit line voltage at the memory cells when the bit line voltage is being written The method of controlling the supply voltage as described in item 1 of the scope of the patent application, wherein the semiconductor memory device includes a plurality of bit lines coupled to the supply voltage, Each of the bit lines includes a respective memory cell, which is coupled to the supply voltage through a respective bit switch, and a group of the memory cell units are addressed together for writing and erasing. In addition to one of the modifications, the detecting step includes detecting a total bit line current supplied to the bit lines, and the adjusting step includes adjusting the supply voltage according to the detected total bit line current. 5. The method for controlling the supply voltage as described in item 4 of the scope of patent application, whose adjustment steps in 25 200535863 13239twf.doc / 006 include increasing the supply voltage if an increase in the bit line current is detected. If the total bit line current is detected to decrease, then the supply voltage is reduced. 6. The method for controlling the supply voltage according to item 4 of the scope of the patent application, wherein the supply voltage includes a fixed reference voltage component and a variable voltage component affected by the detected total bit line current, The method further includes gradually adjusting the relationship between the variation component and the total bit line current as the individual memory cells enter a written state 'in the group of memory cells. 7. The method for controlling the supply voltage according to item 6 of the scope of the patent application, wherein the step-by-step adjustment step adjusts the variation component and the Relationship between total bit line currents. 8. The method of controlling the supply voltage according to item 6 of the scope of patent application, the step of generating the variable voltage component includes mirroring the total bit line current with a reduction rate, and generating the change with the mirrored portion ingredient. 9. The method of controlling the supply voltage as described in item 8 of the scope of the patent application, wherein the step of stepwise adjustment includes changing the resistance 用于 for generating the variable voltage component. 10. The method for controlling the supply voltage as described in item 9 of the scope of the patent application, wherein the changing step is affected by a plurality of control signals, and the control signals indicate each of the individual memories in the set of memory cells. The unit cell is in the written state or not. 11. The method for controlling the supply voltage according to item 4 of the scope of patent application, wherein the semiconductor memory device is a flash memory device, and the flash memory device includes a flash memory cell. A plurality of input / output block arrays, each of which includes a plurality of rows and a plurality of 26 200535863 13239twf.doc / 006 columns, and the input / output block array includes the bits line. 12. A semiconductor device, comprising: a single V-line; a plurality of memory cells, and a one-bit connection is coupled to the memory cells and a supply voltage node; a detection device for detecting Measuring a bit line current supplied to the memory cells; and an adjusting device for adjusting a supply voltage at the supply voltage node according to the detected bit line current to at least partially compensate for crossing the The voltage drop of the bit switch, which is at least partially affected by the bit line current. 13. The semiconductor device according to item 12 of the scope of patent application, wherein the adjustment device includes increasing the supply voltage when detecting an increase in the bit line current, and detecting a decrease in the bit line current when the bit line current is detected to increase. A device that reduces the supply voltage. 14. The semiconductor device according to item 12 of the scope of patent application, further comprising adjusting the supply voltage to maintain a bit line voltage at the memory cells, the bit line voltage being written and erased. A device that remains largely unchanged during the correction process. 15. The semiconductor device according to item 12 of the scope of patent application, wherein the semiconductor device includes a plurality of bit lines coupled to the supply voltage; each of the bit lines includes a respective memory cell, and passes through a respective memory cell. The bit switch is coupled to the supply voltage, and a group of the memory cell lines are addressed together for writing or over-erase correction. The detection device includes a device for detecting the supply. A total bit line current to the bit lines, and 27 200535863 13239twf.doc / 006 The adjustment device includes a device for adjusting the supply voltage according to the detected total bit line current. 16. The semiconductor device according to item 15 of the scope of patent application, wherein the detection device includes a current mirror circuit designed to mirror the total bit line current at a reduced rate. 17. The semiconductor device according to item 15 of the scope of patent application, wherein the adjusting device includes a means for increasing the supply voltage when an increase in the total bit line current is detected, and when the total bit is detected A device that reduces the supply voltage when the line current is reduced. 18. The semiconductor device according to item 17 of the scope of patent application, wherein the adjustment device comprises a z-differential amplifier, the output of the differential amplifier is coupled to the supply voltage node; and a reference voltage generating circuit, the reference An output terminal of the voltage generating circuit is coupled to a reference voltage input terminal of the differential amplifier. 19. The semiconductor device as described in claim 18, wherein the reference voltage generating circuit includes a resistor circuit coupled to a current mirror circuit, and the current mirror circuit is designed to mirror the overall position at a reduced rate. Element line current. 20. The semiconductor device according to item 15 of the scope of patent application, wherein the supply voltage includes a fixed reference voltage component and a variable voltage component affected by the detected total bit line current, and the semiconductor device is more It includes an adjustment device that gradually adjusts the relationship between the change component and the total bit line current as individual memory cells enter a written state in the set of unit cells. 21. The semiconductor device according to item 20 of the scope of patent application, wherein the tuning device includes a reference voltage generating circuit, and the reference voltage generating circuit includes an adjustable resistance circuit coupled to a reference circuit. A current mirror circuit, which is designed to mirror the total bit line current at a reduced rate. 22. The semiconductor device according to item 21 of the scope of patent application, further comprising a resistor for adjusting the adjustable resistance circuit according to a plurality of control signals, the control signals indicating each of the group of memory cells Whether the individual memory cell is in a written state. 23. The semiconductor device according to item 22 of the scope of patent application, wherein the relationship is adjusted after each individual cell of the group of memory cells enters the φ of the written state. 24. The semiconductor device described in item 20 of the scope of patent application, further includes a device that generates the variable voltage component. 25. The semiconductor device according to item 15 of the scope of patent application, wherein the semiconductor memory device is a flash memory device, including an array of input-output blocks composed of a plurality of flash memory cells, each of which The input-output blocks include a plurality of rows and a plurality of columns, and the input-output block array includes the bit lines. 26. A semiconductor device comprising an array of flash memory cells, the array includes a plurality of rows and a plurality of columns, the rows include a plurality of bit lines, each of which includes An individual memory cell is coupled to a supply voltage through an individual bit switch. One group of the memory cells can be addressed together to write data. The semiconductor device further includes: a detection device To detect a total bit line current provided to the bit lines coupled to the set of memory cells; a controlled voltage supply source provides the supply voltage, the supply voltage 29 200535863 13239twf. doc / 006 includes a fixed reference voltage component and a variable voltage component affected by the detected total bit line current, wherein the supply voltage is adjusted to track the supply to the memory cell coupled to the group The total bit line current of the bit lines; and an adjusting device for adjusting the variation component and the total bit line current as each of the memory cells enters a written state between Relations. 27. The semiconductor device according to item 26 of the scope of patent application, wherein the adjusting device includes a reference voltage generating circuit, the reference voltage generating circuit includes an adjustable resistor circuit coupled to a current mirror circuit, and the current mirror circuit is Designed to mirror the total bit line current at a reduced rate. 28. The semiconductor device described in item 27 of the scope of patent application, further comprising adjusting the resistance of the adjustable resistance circuit according to a control signal, the control signal indicating whether each individual memory cell is in a written state State of a device. 29. The semiconductor device according to item 28 of the scope of patent application, wherein the relationship is adjusted after each individual cell enters a written state. 30. A semiconductor memory device, comprising: a one-bit line; a memory cell, and a one-bit switch coupled between the memory cell and a supply voltage node; a current mirror circuit for A reduction ratio mirroring the bit line current passing through the memory cell; a voltage source whose output terminal is coupled to the supply voltage node and varies with a reference voltage; and a reference voltage generating circuit An output terminal of the reference voltage generating circuit is coupled to a reference voltage input terminal of the voltage source, and the reference voltage generating circuit package includes a resistor circuit coupled to the current mirror circuit, wherein the reference voltage generating circuit supplies A reference voltage is given to the voltage source, and the reference voltage will change with the bit line current after the mirroring. With the reference voltage, the supply voltage at the supply voltage node will be adjusted according to the bit line current. A voltage drop across the bit switch is at least partially compensated, and the voltage drop is at least partially affected by the bit line current. 31