1239015 13239twf.doc/006 玖、發明說明： 【發明所屬之技術領域】 本發明是關於一積體電路(integrated circuit)記憶體，此記 憶體包含一記憶體晶胞陣列（array of memory cells)，以及在寫 入（programming)過程中提供壓降補償（voltage drop compensation)的電路。 【先前技術】 圖1係繪示傳統一個積體電路，其包括快閃電子可抹除 可寫入唯讀記憶體（flash EEPR0M，以下簡稱快閃EEPR0M 記憶體）陣列1〇〇,以及對陣列1〇〇其中的記憶體晶胞做寫入、 抹除(erasing)、讀取、和過抹除修正(overerase correction)的電 路。快閃EEPR0M記憶體陣列100是由個別晶胞組成，例如 晶胞102。每個晶胞都有一個汲極（drain)耦接至位元線 (bitline)，例如位元線104，且每條位元線都耦接位元線交換 電路（bitline switch circuit) 106 以及行解碼器（column decoder) 108。記憶體晶胞的源極（souixe)互相耦接，並耦接共同源極信 號（common source signal) VSL，而各晶胞的閛極(gate)係經由 一條字元線(wordline)連到列解碼器110。 列解碼器110由電源供應器112接收電壓信號，且受處理 器（processor)或狀態機（state machine)l 14發出的列位址（row address)控制，並將電壓信號分送到字元線。同樣的，位元線 交換電路106亦接收來自電源供應器112的電壓信號，並且受 處理器114發出的信號控制而將特定的電壓信號分送到位元 線。而電源供應器112送出的電壓，也受處理器114送出的信 號控制。 行解碼器108受來自處理费114的行位址信號（column 1239015 13239twf.doc/006 address signal)控制，而將信_自特定位元線傳送至感應放大 器（sense amplifier)或比較器(comparator) 116。電源供應器 112 提供電壓給行解碼器108與位元線104。感應放大器116也接 收來自參考陣歹[J (reference array) 118的參考晶胞（reference cells)的信號。有了來自行解碼器108與參考陣列118的信號 輸入，感應放大器116就能提供信號，以指示一條位元線與一 條參考晶胞線（reference cell line)之間的狀態差異，此信號係 通過資料閂（data latch)或緩衝區（buffer) 120，傳送至處理器 114 ° 如果想寫入快閃記憶體陣列100的一個晶胞，電源112會 發出高電壓的閘源極（gate-to-source)脈衝給該晶胞，同時晶胞 的源極必須接地。例如在寫入過程中，會向一個晶胞送出多 次大約1〇伏特的閘極電壓脈衝，每次持續大約三到六微秒 (microsecond)，同時該晶胞的汲極電壓保持在4.5伏特，源極 接地。此汲極到源極的4.5伏特偏壓(bias)會在汲極附近產生 熱電子（hot electrons)。從閘極到源極的高電壓脈衝’讓熱電 子有機會克服通道(channel)與一薄介電層(dielectric layer)所形 成的能量障壁(energy barrier)，以到達該晶胞的浮置閘極。這 個寫入程序，名爲「熱電子注射」（hot electron injection)，其 係提高該晶胞的臨界電壓(threshold voltage)，也就是使該晶胞 進行傳導所需的閘源極電壓。 爲抹除快閃記憶體陣列1〇〇的某個晶胞，必須用一種名 爲「福勒—諾漢穿險」（Fowler-Nordheim tunneling)的程序， 也就是連續施加高負値的閘源極電壓脈衝，每次持續幾個毫 秒（mmisecond)。例如在抹除過程中，可以對一個晶胞施加幾 1239015 13239twf.doc/006 次-10伏特的閘極電壓脈衝，同、時、該晶胞的源極電壓保持在5.5 伏特，且其汲極浮置。這種高負値閘源極電壓脈衝可使電子 憑藉穿隧效應離開記憶體晶胞的浮置閘極，藉以降低其臨界 電壓値。 ， 在抹除之後，要提防一種稱爲「過抹除」的現象。過抹 除的晶胞因爲臨界電壓過低，在〇伏特的閘源極電壓之下也 會產生漏電流（leakage current)。晶胞漏電會造成不容忽視的 位元線電流，而導致讀取與寫入錯誤。因此’需要過抹除修 正以減少這種位元線電流。在過抹除修正時’在快閃記憶體 陣列100之中，耦接同一條位元線的所有晶胞，都有相同的 閘源極電壓，且其源極一律接地，汲極電壓設定爲大約5伏 特。熱電子會被注入浮置聞極’以提筒該些晶胞的臨界電壓 値。 在寫入過程中，一條位元線上的電流’是由處於寫入狀 態的晶胞的輸出電流’以及同一位元線上其他未受選定的晶 胞的電流加總而成。一般來說’未受選定的晶胞之閘源極電 壓係爲接地準位。在過抹除修正時’一條位元線上的電流’ 是耦接位元線的全部晶胞的電流總和。如果過抹除修正是由 位元線執行，全部晶胞會有相同的閘源極電壓。如果過抹除 修正是由晶胞執行，受選定的晶胞的閘源極電壓會和其他的 晶胞不同。 一個晶胞的浮置閘極儲存一個資料位元’會經過前述的 寫入與抹除步驟。在寫入後，晶胞的臨界電壓通常保持在約5.0 伏特以上，而抹除後的晶胞，其臨界電壓通常約低於3·0伏特。 如果想讀取一個晶胞’必須施以3·0伏特和6·5伏特之間’通 1239015 13239twf.doc/006 常是5伏特的控制閘極電壓。、該5伏特的讀取脈衝會被輸入 到一個陣列晶胞的閘極，以及參考陣列U8當中一個臨界電壓 接近3.5伏特的晶胞。在陣列1〇〇當中，已寫入的晶胞，其臨 界電壓大於5.0伏特，其輸出電流會小於該臨界3.5伏特之參 考晶胞所供給之電流，表示該記憶體晶胞已寫入資料。已抹 除資料的晶胞，其臨界電壓低於3.0伏特，其輸出電流會大於 該臨界値爲3.5伏特的參考晶胞，表示記憶體晶胞已經被抹 除。在確認寫入或抹除時，讀取電壓同樣會被輸入到記憶體 陣列的一個晶胞以及參考陣列118的一個晶胞。在作寫入確認 時，係使用臨界値5.0伏特的參考晶胞做比較，在作抹除確認 時，係使用臨界値3.0伏特的參考晶胞做比較。 圖2是快閃記憶體的部分電路圖，特別繪示兩條位元線 104，各包含兩個晶胞102，以及在寫入與過抹除修正時，在 各晶胞102的汲極產生位元線電壓VBL (標示爲VBLo至 VBLn)的相關電路。共同源極線在圖中接地。雖然圖中只繪 示兩條位元線1〇4和兩條字元線，實際的記憶體陣列可包含 任意數量的位元線與字元線，因此可包含任意數量的晶胞。 個別的字元線信號WLo至WLn耦接至各晶胞102的控制閘 極。行解碼器（圖1 )會選定多條位元線，以啓動附屬於各位 元線的位元開關（bit switch) 124。打開一個位元開關124，將 啓動對應的位元線104 ’而對應的晶胞1〇2即可由字元線信號 啓動。 記憶體陣列通常也包含複數個輸入輸出端(I/O)，例如位 元組模式（byte mode)需要八個’字元模式（w〇rd m〇de)需要十 六個。每個輸入輸出端包含多條位元線1〇4，且每個輸入輸出 1239015 13239twf.doc/006 端都會選出一條位元線來作嗓取或寫入的動作，也就是說， 在位麵模式八個輸入輸出端各選出—條位元線（總共有八 條位元線和八個位元）’而在字元模式十六個輸入輸出端各選 出一條位兀線（總共有十六條位元線和十六個位元），做讀取 或寫入動作。每個輸入輸出端對應到一個內部資料線信號DL (標示爲DL[0]至DL[n])以及多條位元線。雖然圖2只爲每 個輸入輸出％5繪不一條ill兀線104，其實信號DL[n]是由稱接 同一輸入輸出端的多條區域位兀線（local bit line)共享的全域 信號(global signal) ’信號DL[0]也是由耦接同一輸入輸出端的 多條區域位元線共享的全域信號。如果一個輸入輸出端的一 條位元線104的一個晶胞102要寫入「〇」，附屬於該輸入輸 出晒的相對應P型金氧半（metal_oxide-semiconductor，即 M0S)電晶體QPL就會開啓。如果該晶胞要寫入爲r !」，附 屬於該輸入輸出端的相對應P型金氧半電晶體QPL就會關閉。 電源供應器112 (亦繪示於圖1)可包含一電荷泵電路 (charge pumping circuit)或外部電源，藉以在寫入或過抹除修 正時提供位元線電流。其中一種做法是用差動放大器 (differential amplifier) 122，以使供應的電壓VDQ1受到控制 而趨近於目標汲極電壓値VDQ2，。位元開關124，在圖中繪 示爲過場電晶體（pass gate transistors) QbsO、Qbsl、Qbs2，會 受行解碼器108輸出的高電壓VPP開啓，以使電壓VDQ2通 往區域位元線104。在圖示的範例中，每個位元開關I24包含 三個金氧半過場電晶體，而實際的過場電晶體數量可能隨晶 片設計而變動。 電壓VDQ2的目標値設定爲（(Ra+Rb)/Ra)*VR。VR係爲 1239015 13239twf.doc/006 一參考電壓，可由一參考電壓子電路提供（未繪示）。電容器 126耦接至VDQ2與地線(ground)之間。電容器126可在VDQ1 被抽運時，降低VDQ2的變動幅度。如果VDQ2超越目標値’ 特別是在電荷泵電路剛產生VDQ2時，漏電路徑電路(leakage path circuit)128會疏導VDQ2以避免電壓過局。電谷益130稱 接在P型金氧半電晶體QP0的閘極與VDQ2之間。電容器130 會將VDQ2即時反應到QP0。圖中的位元開關124受到高電 壓VPP而驅動，在寫入與過抹除修正時，則允許VDQ2進入 區域位元線。位元開關124的電晶體大小通常爲節省面積而 受限制。 在寫入與過抹除修正時，當電流經過每條位元線的p型 金氧半電晶體QPL和位元開關124，會產生電壓降，壓降程 度與通過每個晶胞102的電流大小成正比，也就是說，位元 線電流越大，壓降也越大。這個壓降會使區域位元線電壓VBL (在圖中標示爲VBLo到VBLn)降低到目標電壓VDQ2以下。 由於晶胞102的電流增強，在寫入的初始階段會大幅降低寫 入的能力。過抹除修正也同樣受到不利影響。當一個晶胞逐 漸被寫入，晶胞會累積電荷，使晶胞電流逐漸減少。一旦區 域位元線電流減少，區域電壓VBL會升高到趨近VDQ2。 VBL的壓降也會衝擊過抹除修正。過抹除修正的效率會 因此大幅降低，而可能造成失敗，也就是說，記憶體晶胞在 預設的時限中無法成功地修正過抹除。 如前面所述及圖2所繪示的電路寫入技術，在寫入每個 晶胞102時，並不提供固定的VBL。如果設計時提高VDQ2 以補償跨越位元開關124的壓降，而當寫入或過抹除修正過 1239015 13239twf.doc/006 程降低位元線電流時，可靠輿依然會有問題。可靠度問題包 括介面狀態（interface state.)產生，因而減低晶胞的耐用期限。 假如VBL升高到太接近Vdq2，可能造成在受選定的位元線 上的未受選定的晶胞發生軟程式化（soft program)，產生熱電 洞（hot holes)衝擊矽〜二氧化矽介面（Si_si〇2 interface)，並產 生介面狀態。晶胞於此介面狀態會衝擊晶胞臨界電壓，並改 變晶胞的抹除與寫入特性(characteristics)。 因此’我們需要一種電路與方法，以提供不易受到晶胞 電流影響的位元線電壓給單一或多個記憶體晶胞。 【發明內容】 * 本發明的目的是提供一種控管供應電壓(supply voltage)的 方法，其係在半導體記憶體裝置內提供位元線電壓，其中位 元線電壓係在通過位元開關之後，被供應給隸屬於位元線的 記憶體晶胞。該方法會偵測提供給記憶體晶胞的位元線電流。 供應電壓會隨偵測到的位元線電流調整，以至少補償一部份 通過位元開關的壓降，而此壓降至少有部分受到位元線電流 影響。 爲讓本發明之上述和其他目的、特徵和優點能更明顯易籲 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明 如下。 【實施方式】 圖3係繪示供應極不易受到位元線(bit line)電流改變影響 的位元線電壓VBL給隸屬位元線104的記憶體晶胞(memory cell) 102的電路。圖3的電路與圖2幾乎相同，相同的元件使 用相同的標示代號，差別是圖3沒有將電容器126與130繪 11 1239015 13239twf.doc/006 不出，亦沒有將漏電路徑電路(leakage path circuit) 128繪示 出，而且陣列1000有包括位元線電流偵測與參考電壓調整電 路（以下簡稱「偵測與調整電路」）200 ’其係供應參考電壓VRp 給差動放大器（differential amplifier) 122。偵測與調整電路2〇〇 偵測來自電晶體QP0，以供應給晶胞102的總位元線電流I， 並根據總位元線電流I的大小，調整參考電壓VRP的電位， 以補償跨越位元開關（bit switch) 124和輸入輸出選擇電晶體 (I/O selection transistor) QPL 的壓降。參考電壓 VRP 輸入給 差動放大器122，以控制VDQ2的電位，進而控制區域位元線 電壓VBL的電位。當大量的總位元線電流通過P型金氧半 (metal-oxide-semiconductor，即 MOS)電晶體 QP0，VRP 會 上升以提高VDQ2，藉以抵銷因應增加的跨越位元開關124的 壓降，並提高區域電壓VBL。圖4的實施例中有這個方法的 更詳細繪示。 請參照圖4，偵測與調整電路200包括一電流鏡電路 (current mirror circuit)，例如一小顆P型金氧半電晶體QP1， 其係以一固定降縮率(reduction ratio) Μ鏡射總位元線電流Ϊ。 降縮後的電流i等於I (總位元線電流）/ Μ。在一實施例中， Μ大約在10到50之間。一電阻器Rt (最好可調整’詳情後 述）耦接於一固定參考電壓VR與電流鏡之間’以將電壓i*Rt 增加到VR之上，藉以供應調整後的參考電壓VRP ’而VRP 受控於固定電壓VR與總位元線電流I。基本上，電壓VRP係 包括一固定成分(VR)以及一受控於總位元線電流1的變動成分 (i*Rt)。 如前所述’參考電壓VRP係透過差動放大器122來控制 12 1239015 13239twf.doc/006 VDQ2的電位。偵測與調整電路200的P型金氧半電晶體QP2 到QPn可用於電壓VDP提高到趨近VDQ2，以使電流鏡QP1 運作於與QP0相同的偏壓狀況下，讓電流鏡的作用趨近完美。 因爲VRP有部分受到總位元線電流I影響，大量的總位元線 電流I會在VR之上累加成比例的大電壓，其數量爲i*Rt (或 (I/M)*Rt)。該電壓加値會反應於VDQ2，並補償在啓動的位元 線中跨越電壓開關的壓降，尤其是在初始寫入階段，此時VBL 可能因爲大量壓降而降至低於目標値。當晶胞電流因爲寫入 或過抹除修正而減少時，總位元線電流I也隨之減少，而造成 鏡射電流i的減少，進而造成累加於VR之上的電壓i*Rt減少， 因此電壓VRP與VDQ2也得隨之減少，以防止記憶體晶胞104 超出負荷。後面會說明如何決定電路200之中，P型金氧半電 晶體的大小與Rt的電阻値。 先假設耦接複數個輸入輸出端（I/O)的複數條位元線104 皆以單獨一條位元線的模型來表示。該些在任一寫入事件中 啓動的複數個並聯的位元開關124以及P型金氧半電晶體QPL 的等效電阻爲Req。總電流I流經Req。假設VD=VRP，則 (Ra/(Ra+Rb)) * VDQ2 = VRP。VRP 亦等於(I/M)*Rt + VR〇 VDQ2 亦等於 VBL + I*Req。因此，（Ra/(Ra+Rb)) * (VBL + I*Req) = VR + (I/M)*Rt。位元線電壓 VBL通常設定爲等於 ((Ra+Rb)/Ra)*VR，其中VR爲一固定電壓。由這個等式可知 (Ra/(Ra+Rb))*I*Req = (I/M)*Rt 。因此 Rt ((M*Ra)/(Ra+Rb))*Req。更進一步假設只有一個晶胞被寫入 時，Req可設定爲「每晶胞Req」-也就是一條受選定的位元 線104的QPL以及其位元開關124的等效電阻。電晶體QP2 1239015 13239twf.doc/〇〇6 到QPn最好夠大，以使其電阻、與、Rt相比之下可忽略不計。 節點VDP的電壓最好接近VDQ2，以提供趨近於理論的 完美電流鏡，但這並非必要。在節點VRP與VDP之間的P型 金氧半電晶體QP2到QPn之中，可加入更多電晶體，以提高 電壓VDP，使其趨近VDQ2，並使QP1有近似QP0的偏壓狀 況。節點VDP與VRP之間的導電路徑必須開啓，以限制偵測 與調整電路200使用的P型金氧半電晶體數量。耦接節點VRP 的P型金氧半電晶體QPn的N井(N well)偏壓必須高於VRP 的電壓，因爲QPn的P型金氧半電晶體N井必須有高於其源 極與汲極的電壓，以避免打開源極或汲極的pn接面（p-η junction)。以下稱這個電壓爲電壓VCX。 在寫入過程中，隨著個別晶胞完成寫入，總位元電流I會 從初始寫入狀態慢慢減少。此外，當一些晶胞完成寫入，而 一些晶胞尙未寫入時，總位元線電流I也會減少。已經寫入的 晶胞視同斷路(open circuit)，寫入後它們的對應開關QPL則 成爲斷路狀態，並與節點VDQ2隔離。當一些晶胞完成寫入 時，跨越位元開關124與P型金氧半電晶體QPL的壓降不會 因被寫入的晶胞而改變，但是累加於VR之上的電壓（i*Rt)會 因爲總電流I的降低而降低，因此VDQ2出現預期地降低。一 旦VDQ2降低，仍在寫入的晶胞的區域電壓VBL可能不會到 達目標値。爲了避免這個效應，電阻器Rt最好可以調整，使 其能反應已經完成寫入的晶胞數量。當個別晶胞完成寫入， 電流I逐漸減少，電阻器Rt的電阻値會隨著增加，以調整VRP 的變動電壓成分與總位元線電流之間的關係，以補償減少的 總位元線電流，儘管變動電壓成分在這之後仍然會受總位元 1239015 13239twf.doc/006 線電流改變的即時影響。但增职Rt的電阻値可確保VRP的變 動電壓成分有實質影響。在圖5的一個實施例中’每個輸入 輸出端都回饋一個信號PDN以表示受選定的位元線中，被定 址(address)的晶胞是否在已寫入狀態。然後將信號PDN用於 調整Rt的電阻値，如圖5所示。信號PDN可依照前述的技術， 或依照熟習確認記億體晶胞的寫入狀態的技術者所知的其他 方式，用參考陣歹[](reference array) 118與感應放大器（sense amplifier) 116 來產生。 這些控制信號在圖5繪示爲偵測與調整電路200中調整鲁 電路500中的PDN[0]至PDN[n]。調整電路500包含複數個 並聯的電阻器R，這些電阻器可由受控制信號PDN觸動的電 晶體開關，選擇性地在並聯組合中加入或移除，以改變Rt的 電阻値。如前所述，PDN[0]到PDN[n]的每個信號，都對應 到一個別的輸入輸出端的一條受選定的位元線的一個被定址 的晶胞的寫入狀態。如果一個輸入輸出端的一個記憶體晶胞 已處於寫入狀態，對應的調整電路500當中的信號PDN[n]會 設定爲低電位，使對應的開關斷路，並將對應的電阻器R從 調整電路500的並聯組合中移除來增加調整電路500的Rt的 0 電阻値，以維持電壓i*Rt，儘管總位元線電流I會隨晶胞完成 寫入而逐漸減少。基本上，當電流i隨各晶胞完成寫入而減少， 電阻Rt會增加以維持電壓i*Rt的相對強度，後者則隨後影響 VRP (即VR + i*Rt)。不過要注意的是，在圖5的實施例中，1239015 13239twf.doc / 006 发明, Description of the invention: [Technical field to which the invention belongs] The present invention relates to an integrated circuit memory. The memory includes an array of memory cells. And a circuit that provides voltage drop compensation during programming. [Prior art] FIG. 1 shows a conventional integrated circuit, which includes a flash electronic erasable and writable read-only memory (flash EEPR0M, hereinafter referred to as flash EEPR0M memory) array 100, and an array One hundred of the memory cells do write, erase, read, and overerase correction circuits. The flash EEPROM memory array 100 is composed of individual unit cells, such as unit cell 102. Each cell has a drain coupled to a bitline, such as bitline 104, and each bitline is coupled to a bitline switch circuit 106 and a row Decoder (column decoder) 108. The source cells of the memory cell are coupled to each other and are coupled to a common source signal VSL. The gates of each cell are connected to the column via a wordline. Decoder 110. The column decoder 110 receives a voltage signal from the power supply 112 and is controlled by a row address issued by a processor or a state machine 114, and distributes the voltage signal to a word line. . Similarly, the bit line switching circuit 106 also receives the voltage signal from the power supply 112, and is controlled by the signal from the processor 114 to distribute the specific voltage signal to the bit line. The voltage from the power supply 112 is also controlled by the signal from the processor 114. The row decoder 108 is controlled by a row address signal (column 1239015 13239twf.doc / 006 address signal) from the processing fee 114, and transmits a signal from a specific bit line to a sense amplifier or a comparator. 116. The power supply 112 supplies voltage to the row decoder 108 and the bit line 104. The sense amplifier 116 also receives signals from reference cells (J (reference array) 118). With the signal input from the row decoder 108 and the reference array 118, the sense amplifier 116 can provide a signal to indicate the state difference between a bit line and a reference cell line. This signal is passed The data latch or buffer 120 is transmitted to the processor 114 ° If you want to write to a cell of the flash memory array 100, the power source 112 will issue a high-voltage gate-to- source) pulse to the unit cell, and the source of the unit cell must be grounded. For example, during the writing process, a gate voltage pulse of about 10 volts is sent to a cell multiple times, each lasting about three to six microseconds, while the drain voltage of the cell is maintained at 4.5 volts. The source is grounded. This 4.5 volt bias from drain to source generates hot electrons near the drain. The high voltage pulse from the gate to the source gives the hot electron the opportunity to overcome the energy barrier formed by the channel and a thin dielectric layer to reach the floating gate of the cell pole. This writing program, called "hot electron injection", raises the threshold voltage of the unit cell, which is the gate-source voltage required for the unit cell to conduct. In order to erase a certain unit cell of the flash memory array 100, a procedure called "Fowler-Nordheim tunneling" must be used, which is to apply a gate source with high negative pressure continuously. Polar voltage pulses, each lasting several milliseconds (mmisecond). For example, during the erasing process, a gate voltage pulse of 1239015 13239twf.doc / 006 times -10 volts can be applied to a unit cell. At the same time, the source voltage of the unit cell is maintained at 5.5 volts, and its drain Float. This high-negative 値 gate-source voltage pulse allows electrons to leave the floating gate of the memory cell by the tunneling effect, thereby reducing its threshold voltage 値. After erasing, beware of a phenomenon called "over-erasing." The over-erased unit cell will generate leakage current below the gate-source voltage of 0 volts because the threshold voltage is too low. Leakage from the cell can cause bit line currents that cannot be ignored, resulting in read and write errors. Therefore, 'erase correction is needed to reduce this bit line current. During over-erasing correction 'In the flash memory array 100, all cells coupled to the same bit line have the same gate-source voltage, and the source is always grounded, and the drain voltage is set to About 5 volts. Hot electrons will be injected into the floating sense electrode 'to raise the critical voltage of the cells 晶. During the writing process, the current on a bit line is the sum of the output current of the cell in the writing state and the current of other unselected cells on the same bit line. Generally, the gate-source voltage of the unselected cell is the ground level. During the over-erasing correction, 'the current on one bit line' is the sum of the currents of all the cells coupled to the bit line. If the over-erase correction is performed by the bit line, all cells will have the same gate-source voltage. If the over-erase correction is performed by the unit cell, the gate-source voltage of the selected unit cell will be different from other unit cells. A cell's floating gate stores a data bit 'and goes through the aforementioned writing and erasing steps. After writing, the critical voltage of the unit cell is usually kept above about 5.0 volts, and the critical voltage of the unit cell after erasing is usually below about 3.0 volts. If you want to read a unit cell, you must apply a voltage between 3.0 volts and 6.5 volts. 1239015 13239twf.doc / 006 The gate voltage is usually 5 volts. The 5 volt read pulse will be input to the gate of an array cell, and a cell with a critical voltage close to 3.5 volts in the reference array U8. In the array 100, the critical voltage of the written unit cell is greater than 5.0 volts, and its output current will be less than the current supplied by the reference 3.5 volt reference cell, indicating that the memory unit cell has written data. The critical voltage of the erased cell is lower than 3.0 volts, and its output current will be greater than the reference cell with a critical threshold of 3.5 volts, indicating that the memory cell has been erased. When confirming writing or erasing, the read voltage is also input to a cell of the memory array and a cell of the reference array 118. For write confirmation, a reference cell with a critical 値 5.0 volt is used for comparison, and for erase confirmation, a reference cell with a critical 値 3.0 volt is used for comparison. FIG. 2 is a partial circuit diagram of the flash memory. In particular, two bit lines 104 are shown, each of which includes two unit cells 102, and bits are generated at the drain of each unit cell 102 during write and overwrite corrections. Circuit related to the element line voltage VBL (labeled VBLo to VBLn). The common source line is grounded in the figure. Although only two bit lines 104 and two word lines are shown in the figure, the actual memory array can contain any number of bit lines and word lines, and therefore can contain any number of unit cells. Individual word line signals WLo to WLn are coupled to the control gate of each cell 102. The row decoder (Figure 1) selects multiple bit lines to activate the bit switch 124 attached to each bit line. Turning on a bit switch 124 will activate the corresponding bit line 104 'and the corresponding unit cell 102 can be activated by a word line signal. The memory array usually also includes a plurality of input / output terminals (I / O). For example, a byte mode requires eight 'word modes (word mode) and requires sixteen. Each input and output terminal contains multiple bit lines 104, and each input and output terminal 1239015 13239twf.doc / 006 will select a bit line for voice or write operations, that is, on the bit plane Each of the eight input and output terminals of the mode is selected-one bit line (a total of eight bit lines and eight bits) ', and one character line is selected at each of the sixteen input and output terminals of the character mode (a total of sixteen Bit lines and sixteen bits), read or write. Each input and output end corresponds to an internal data line signal DL (labeled DL [0] to DL [n]) and a plurality of bit lines. Although FIG. 2 only draws one ill line 104 for each input and output% 5, in fact, the signal DL [n] is a global signal (global) shared by multiple local bit lines connected to the same input and output ends. signal) 'Signal DL [0] is also a global signal shared by multiple regional bit lines coupled to the same input and output. If a cell 102 of a bit line 104 on an input / output terminal is to write “〇”, the corresponding P-type metal-oxide-semiconductor (M0S) transistor QPL attached to the input-output terminal will be turned on. . If the unit cell is to be written as r! ", The corresponding P-type metal-oxide-semiconductor QPL attached to the input and output terminals will be turned off. The power supply 112 (also shown in FIG. 1) may include a charge pumping circuit or an external power supply, so as to provide bit line current during write or erase correction. One of them is to use a differential amplifier 122 so that the supplied voltage VDQ1 is controlled to approach the target drain voltage 値 VDQ2. The bit switch 124 is shown in the figure as pass gate transistors QbsO, Qbsl, Qbs2, and is turned on by the high voltage VPP output from the row decoder 108, so that the voltage VDQ2 passes to the regional bit line 104. In the illustrated example, each bit switch I24 contains three metal-oxide half-transistors. The actual number of transistors may vary depending on the design of the wafer. The target value of the voltage VDQ2 is set to ((Ra + Rb) / Ra) * VR. VR is 1239015 13239twf.doc / 006 a reference voltage, which can be provided by a reference voltage sub-circuit (not shown). The capacitor 126 is coupled between VDQ2 and the ground. The capacitor 126 can reduce the fluctuation range of VDQ2 when VDQ1 is pumped. If VDQ2 exceeds the target 値 ′, especially when VDQ2 is just generated by the charge pump circuit, the leakage path circuit 128 will guide VDQ2 to avoid voltage overshoot. Electric Valley 130 said that it was connected between the gate of P-type metal-oxide semiconductor transistor QP0 and VDQ2. Capacitor 130 will instantly react VDQ2 to QP0. The bit switch 124 in the figure is driven by the high voltage VPP, and VDQ2 is allowed to enter the area bit line during the writing and erasing corrections. The transistor size of the bit switch 124 is generally limited to save area. During the writing and over-erasing corrections, when the current passes through the p-type metal-oxide-semiconductor QPL and bit switch 124 of each bit line, a voltage drop is generated. The magnitude is directly proportional, that is, the larger the bit line current, the greater the voltage drop. This voltage drop will reduce the regional bit line voltage VBL (labeled VBLo to VBLn in the figure) below the target voltage VDQ2. Because the current of the unit cell 102 is increased, the writing ability will be greatly reduced in the initial stage of writing. Over-erase corrections are also adversely affected. When a unit cell is written gradually, the unit cell will accumulate charges, which will cause the unit cell current to gradually decrease. Once the area bit line current is reduced, the area voltage VBL will rise to approach VDQ2. The pressure drop of the VBL will also impact the erase correction. The efficiency of over-erase correction will be greatly reduced, which may cause failure, that is, the memory cell cannot successfully over-erase within the preset time limit. As described above and shown in FIG. 2, the circuit writing technique does not provide a fixed VBL when writing to each cell 102. If VDQ2 is increased during the design to compensate for the voltage drop across the bit switch 124, and there is still a problem with the reliability of the bit line when the bit line current is reduced when writing or over-erasing the correction 1239015 13239twf.doc / 006. Reliability problems include the generation of interface state. This reduces the durability of the cell. If VBL rises too close to Vdq2, it may cause a soft program on the unselected unit cell on the selected bit line, resulting in hot holes that impact the silicon ~ silicon dioxide interface (Si_si 〇2 interface), and generate an interface state. The state of the unit cell at this interface will impact the critical voltage of the unit cell and change the erasing and writing characteristics of the unit cell. So we need a circuit and method to provide bit line voltages that are not easily affected by the cell current to a single or multiple memory cell. [Summary of the invention] * The purpose of the present invention is to provide a method for controlling a supply voltage, which is to provide a bit line voltage in a semiconductor memory device, wherein the bit line voltage is after passing a bit switch. Memory cells are supplied to bit lines. This method detects the bit line current supplied to the memory cell. The supply voltage is adjusted with the detected bit line current to compensate at least part of the voltage drop through the bit switch, and this voltage drop is at least partially affected by the bit line current. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is hereinafter described in detail with the accompanying drawings as follows. [Embodiment] FIG. 3 shows a circuit for supplying a bit line voltage VBL, which is not easily affected by a bit line current change, to a memory cell 102 belonging to the bit line 104. The circuit in Figure 3 is almost the same as that in Figure 2. The same components use the same labeling code. The difference is that Figure 3 does not show capacitors 126 and 130. 11 1239015 13239twf.doc / 006 does not show the leakage path circuit (leakage path circuit ) 128 is shown, and the array 1000 includes a bit line current detection and reference voltage adjustment circuit (hereinafter referred to as “detection and adjustment circuit”) 200 ′ which supplies a reference voltage VRp to a differential amplifier 122 . The detection and adjustment circuit 200 detects the total bit line current I supplied from the transistor QP0 to the cell 102, and adjusts the potential of the reference voltage VRP according to the size of the total bit line current I to compensate for the crossing The voltage drop of the bit switch 124 and the I / O selection transistor QPL. The reference voltage VRP is input to the differential amplifier 122 to control the potential of VDQ2, and then the potential of the regional bit line voltage VBL. When a large amount of total bit line current passes through the P-type metal-oxide-semiconductor (MOS) transistor QP0, VRP will rise to increase VDQ2 to offset the corresponding increase in voltage drop across the bit switch 124. And increase the regional voltage VBL. This method is illustrated in more detail in the embodiment of FIG. Referring to FIG. 4, the detection and adjustment circuit 200 includes a current mirror circuit, such as a small P-type metal-oxide semiconductor transistor QP1, which is irradiated with a fixed reduction ratio (M). Total bit line current Ϊ. The reduced current i is equal to I (total bit line current) / M. In one embodiment, M is between about 10 and 50. A resistor Rt (preferably adjustable 'to be described later) is coupled between a fixed reference voltage VR and a current mirror' to increase the voltage i * Rt above VR to supply the adjusted reference voltage VRP 'and VRP It is controlled by the fixed voltage VR and the total bit line current I. Basically, the voltage VRP system includes a fixed component (VR) and a variable component (i * Rt) controlled by the total bit line current 1. As mentioned earlier, the reference voltage VRP is controlled by the differential amplifier 122 to 12 1239015 13239twf.doc / 006 VDQ2. The P-type metal-oxide semiconductor transistors QP2 to QPn of the detection and adjustment circuit 200 can be used to increase the voltage VDP to approach VDQ2, so that the current mirror QP1 operates under the same bias condition as QP0, so that the current mirror's role is approached perfect. Because VRP is partly affected by the total bit line current I, a large amount of total bit line current I will accumulate a proportionally large voltage above VR, the amount of which is i * Rt (or (I / M) * Rt). This voltage increase will be reflected in VDQ2 and compensate for the voltage drop across the voltage switch in the activated bit line, especially during the initial write phase. At this time, VBL may drop below the target voltage due to a large voltage drop. When the cell current is reduced due to writing or over-erase correction, the total bit line current I also decreases, resulting in a reduction in the mirror current i, which in turn causes a reduction in the voltage i * Rt accumulated over VR, Therefore, the voltages VRP and VDQ2 must be reduced accordingly to prevent the memory cell 104 from being overloaded. How to determine the size of the P-type metal-oxide semiconductor and the resistance of Rt in the circuit 200 will be described later. It is assumed that a plurality of bit lines 104 coupled to a plurality of input / output terminals (I / O) are all represented by a single bit line model. The equivalent resistances of the plurality of parallel bit switches 124 and the P-type metal-oxide semiconductor transistor QPL activated in any write event are Req. The total current I flows through Req. Assuming VD = VRP, then (Ra / (Ra + Rb)) * VDQ2 = VRP. VRP is also equal to (I / M) * Rt + VR. VDQ2 is also equal to VBL + I * Req. Therefore, (Ra / (Ra + Rb)) * (VBL + I * Req) = VR + (I / M) * Rt. The bit line voltage VBL is usually set equal to ((Ra + Rb) / Ra) * VR, where VR is a fixed voltage. From this equation, (Ra / (Ra + Rb)) * I * Req = (I / M) * Rt. So Rt ((M * Ra) / (Ra + Rb)) * Req. It is further assumed that when only one cell is written, Req can be set to "Req per cell"-that is, the QPL of a selected bit line 104 and the equivalent resistance of its bit switch 124. The transistor QP2 1239015 13239twf.doc / 〇〇6 is preferably large enough so that its resistance is negligible compared with Rt. The voltage at node VDP is preferably close to VDQ2 to provide a perfect current mirror approaching theory, but this is not necessary. Between the P-type metal-oxide-semiconductor QP2 to QPn between the nodes VRP and VDP, more transistors can be added to increase the voltage VDP, bring it closer to VDQ2, and make QP1 a biased state similar to QP0. The conductive path between the nodes VDP and VRP must be opened to limit the number of P-type metal-oxide semiconductors used in the detection and adjustment circuit 200. The N well bias of the P-type metal-oxide-semiconductor QPn coupled to the node VRP must be higher than the voltage of VRP, because the P-type metal-oxide-semiconductor N-well of QPn must have a higher voltage than its source and drain. To avoid opening the pn junction of the source or drain. This voltage is hereinafter referred to as the voltage VCX. During the writing process, as individual cells complete writing, the total bit current I will gradually decrease from the initial writing state. In addition, when some unit cells finish writing and some unit cells are not written, the total bit line current I also decreases. The cells that have been written are regarded as open circuits. After writing, their corresponding switches QPL become open and isolated from node VDQ2. When some cells finish writing, the voltage drop across the bit switch 124 and the P-type metal-oxide-semiconductor QPL will not change due to the written cell, but the voltage (i * Rt) accumulated above VR ) Will decrease due to the decrease of the total current I, so VDQ2 appears to decrease as expected. Once VDQ2 decreases, the area voltage VBL of the cell still being written may not reach the target value. In order to avoid this effect, the resistor Rt can preferably be adjusted so that it can reflect the number of unit cells that have been written. When the individual cell finishes writing, the current I gradually decreases, and the resistance R of the resistor Rt will increase as it adjusts the relationship between the variable voltage component of VRP and the total bit line current to compensate for the reduced total bit line. The current, although the variable voltage component, is still immediately affected by the change in the total bit current of 1239015 13239twf.doc / 006. However, increasing the resistance of Rt can ensure that the changing voltage component of VRP has a substantial effect. In one embodiment of FIG. 5, each of the input and output terminals returns a signal PDN to indicate whether or not the addressed cell is in the written state in the selected bit line. The signal PDN is then used to adjust the resistance of Rt, as shown in Figure 5. The signal PDN may be in accordance with the aforementioned technology, or other methods known to those skilled in the art of confirming the writing state of the billion-unit cell, using the reference array [] (reference array) 118 and the sense amplifier (116). produce. These control signals are shown in FIG. 5 as PDN [0] to PDN [n] in the adjustment circuit 500 in the detection and adjustment circuit 200. The adjustment circuit 500 includes a plurality of resistors R connected in parallel. These resistors can be selectively added or removed from the parallel combination by a transistor switch triggered by the control signal PDN to change the resistance 値 of Rt. As mentioned above, each signal of PDN [0] to PDN [n] corresponds to the writing state of an addressed cell of a selected bit line to another input / output terminal. If a memory cell of an input / output terminal is already in the writing state, the signal PDN [n] in the corresponding adjustment circuit 500 will be set to a low level, the corresponding switch will be opened, and the corresponding resistor R will be removed from the adjustment circuit The parallel combination of 500 is removed to increase the resistance R0 of the adjustment circuit 500 to maintain the voltage i * Rt, although the total bit line current I will gradually decrease as the cell finishes writing. Basically, when the current i decreases as each cell finishes writing, the resistance Rt increases to maintain the relative strength of the voltage i * Rt, which then affects VRP (ie, VR + i * Rt). It should be noted, however, that in the embodiment of FIG. 5,
Rt的電阻値是逐步變動，而不是隨電流i立即變動。一旦Rt 因爲一個晶胞完成寫入狀態而改變，Rt就保持不變，直到下 一個晶胞完成寫入爲止。VRP會以Rt的電阻値設定的速率繼 15 1239015 13239twf.doc/006 繪追縱電〖iL· i的變化，直到民i；變動爲止。一*旦下個晶胞完成 寫入，對應的電阻器R會.首電路5〇〇的並聯組合中移除，以 增加Rt的電阻値，以及VRP的變動成分隨電流i即時變動的 程度。讓Rt的電阻値隨各晶胞完成寫入而遞增，可確保電壓 VRP繼續有意義地追蹤總位元線電流I的改變。 舉例而言，假設寫入係以以位元組（byte)爲單位。如果八 個晶胞當中有五個尙未寫入，八個信號PDN當中就有五個會 觸動電路500當中的開關，以使Rt等於五個電阻器R並聯而 成的等效電阻。在這五個晶胞的寫入過程，VRP與VDQ2會 以暫時固定的Rt値設定的程度，即時追蹤電流I的變化。一 旦五個晶胞其中之一完成寫入，對應的信號PDN會使電路500 當中一個對應的開關斷路，以提高Rt的等效電阻値，以及VRP 與VDQ2在其餘四個晶胞寫入時，即追蹤電流I變化的程度。 在〜實施例中，根據前面爲Rt導出的公式，每個電阻器R的 電阻値爲Μ * (Ra/(Ra+Rb)) * (每晶胞Req)。 如前所述，對一已寫入的晶胞或1〇，位元開關路徑可由 信號PD[n]關閉，此信號係耦接至Ρ型金氧半電晶體QPL的 控制閘極。每個信號PD都處於對應信號PDN的相反狀態， 其邏輯高電位設定爲VDQ2，其邏輯低電位設定爲VSS。 圖5的記憶體電路，雖然沒有繪示，仍包含如圖2所示 從節點VDQ2接地的一漏電路徑，，以減低VDQ2在之前圖2 的相關說明中提到的過高現象。不過，這股電流會由偵測位 元線電流的P型金氧半電晶體QP1鏡射在電路200之中。爲 除去漏電流的影響，可將漏電流電路開啓持續一段時限，例Rt's resistance 变动 changes gradually, not immediately with current i. Once Rt changes because one cell has finished writing, Rt remains unchanged until the next cell completes writing. VRP will follow the change of 15 1239015 13239twf.doc / 006 at a rate set by the resistance of Rt, until the change in iL · i is reached until the value of i is changed. Once the writing is completed by the next unit cell, the corresponding resistor R will be removed from the parallel combination of the first circuit 500 to increase the resistance R of Rt, and the degree to which the variation component of VRP changes instantaneously with the current i. Letting the resistance of Rt increase as each cell finishes writing can ensure that the voltage VRP continues to meaningfully track changes in the total bit line current I. For example, it is assumed that the writing is performed in bytes. If five cells of the eight cells are not written, five of the eight signal PDNs will trigger the switches in the circuit 500 so that Rt is equal to the equivalent resistance of the five resistors R connected in parallel. During the writing process of these five unit cells, VRP and VDQ2 will track the change of current I in real time to the extent set by the temporarily fixed Rt 値. Once one of the five cells is written, the corresponding signal PDN will open one of the corresponding switches in circuit 500 to increase the equivalent resistance of Rt, and when VRP and VDQ2 are written in the remaining four cells, That is, the degree to which the current I changes is tracked. In the embodiments, the resistance 公式 of each resistor R is M * (Ra / (Ra + Rb)) * (per cell Req) according to the formula derived for Rt. As mentioned above, for a written cell or 10, the bit switch path can be closed by the signal PD [n], which is coupled to the control gate of the P-type metal-oxide semiconductor transistor QPL. Each signal PD is in the opposite state of the corresponding signal PDN, its logic high potential is set to VDQ2, and its logic low potential is set to VSS. Although not shown, the memory circuit of FIG. 5 still includes a leakage path grounded from the node VDQ2 as shown in FIG. 2 to reduce the excessive phenomenon of VDQ2 mentioned in the related description of FIG. 2. However, this current is mirrored in the circuit 200 by a P-type metal-oxide semiconductor transistor QP1 which detects the bit line current. In order to remove the influence of leakage current, the leakage current circuit can be turned on for a certain period of time.
I 如s微秒(microsecond)，以穩定VDQ2電位，然後關閉漏電流 1239015 13239twf.doc/006 電路。此時限可由一計時電吟c未繪示）控制。可使用爲寫 入脈衝、過抹除脈衝和抹除脈衝產生時脈控制信號的計時器。 在該時限中，差動放大器122的輸入可設爲VR，而非VRP， 其係等於切斷偵測與調整電路200與差動放大器122的耦接， 並將VDQ2設爲固定値。在時限之後，VRP會耦接到差動放 大器，另外可以打開一個小型漏電路徑電路，取代原先的漏 電路徑電路，以避免VDQ2過高。如熟悉圖2的先前技術電 路者所知，漏電路徑電路可由一個或多個N型金氧半電晶體 串聯耦接至節點VDQ2組成。如果VDQ2的電壓過高，電流 # 會通過N型金氧半電晶體進入地線。一旦VDQ2的電位穩定 下來，耦接更小的N型金氧半電晶體到節點VDQ2，就能減少 漏電流。 圖6說明調整電路500A當中的電阻器R可用電晶體實 作，而這些電晶體的大小符合此比列：（Ra/(Ra+Rb))*M * ( — 條位元線的位元開關124的電晶體以及輸入輸出端開關QPL 的等效電阻）。比起使用電阻器，這種設計的優點是溫度補償 (temperature compensation)更佳，也就是說，這些電晶體和位 元開關裡的電晶體有相同的溫度係數（temperature · coefficient) 〇 以下的表格1-1與1-2的內容是以軟體模擬圖2的先前技 術電路的結果，其中VCC (電源供應的電壓）、溫度與參考電 壓VR如表格中所示。行位「G」是P型金氧半電晶體QP0的 閘極電壓。下列表格記錄兩種狀況-（1)只有一個抹除後的晶 胞需要寫入，或只有一條位元線需要過抹除修正，以及（2)有 八個抹除後的晶胞需要寫入，或八條位元線需要過抹除修正。 17 1239015 13239twf.doc/006 下列表格顯示當大約0.3到〇.彡毫安培(mA)的電流通過一條位 元線時，比起受控管的固定電壓VDQ2，位元線電壓VBL會 降低大約0.4到0.6伏特。「0毫安培」表示受選定的待寫入晶 胞已經是寫入後狀態，而耦接同一條位元線的其餘晶胞，在 寫入過程中都沒有漏電流。或者，^ 〇毫安培」表示在過抹除 修正過程中，受選定的位元線上的全部晶胞都沒有漏電流。 表格1-1。VCC/溫度=3.6伏特/攝氏0度；VR=1.2伏特。其中 電壓單位「V」爲伏特，電流單位^mA」爲毫安培。I as microsecond to stabilize the VDQ2 potential, and then turn off the leakage current 1239015 13239twf.doc / 006 circuit. The time limit can be controlled by a timing electric channel (not shown). You can use a timer that generates a clock control signal for the write pulse, over erase pulse, and erase pulse. In this time limit, the input of the differential amplifier 122 may be set to VR instead of VRP, which is equivalent to cutting off the coupling between the detection and adjustment circuit 200 and the differential amplifier 122, and setting VDQ2 to fixed 値. After the time limit, the VRP will be coupled to the differential amplifier. In addition, a small leakage path circuit can be opened to replace the original leakage path circuit to avoid VDQ2 being too high. As known to those familiar with the prior art circuit of FIG. 2, the leakage path circuit may consist of one or more N-type metal-oxide semiconductor transistors coupled in series to node VDQ2. If the voltage of VDQ2 is too high, the current # will enter the ground through the N-type metal-oxide semiconductor transistor. Once the potential of VDQ2 is stabilized and a smaller N-type metal-oxide semiconductor transistor is coupled to the node VDQ2, the leakage current can be reduced. FIG. 6 illustrates that the resistors R in the adjustment circuit 500A can be implemented by transistors, and the size of these transistors conforms to this ratio: (Ra / (Ra + Rb)) * M * (— bit switch of a bit line 124 transistor and the equivalent resistance of the input and output switch QPL). Compared with the use of resistors, this design has the advantage of better temperature compensation, that is, these transistors have the same temperature coefficient as the transistors in the bit switch. The following table The contents of 1-1 and 1-2 are the results of software simulation of the prior art circuit of FIG. 2, where VCC (voltage of power supply), temperature and reference voltage VR are shown in the table. The row position "G" is the gate voltage of the P-type metal-oxide semiconductor transistor QP0. The following table records two conditions-(1) only one erased unit cell needs to be written, or only one bit line needs to be erased and corrected, and (2) eight erased unit cells need to be written , Or eight bit lines need erasure correction. 17 1239015 13239twf.doc / 006 The following table shows that when a current of about 0.3 to 0.00 milliamperes (mA) passes through a bit line, the bit line voltage VBL decreases by about 0.4 compared to the fixed voltage VDQ2 of the controlled tube To 0.6 volts. "0 mA" indicates that the selected cell to be written is already in the post-write state, and the remaining cells coupled to the same bit line have no leakage current during the writing process. Alternatively, "^ 〇mA" indicates that during the over-erase correction process, all the unit cells on the selected bit line have no leakage current. Table 1-1. VCC / temperature = 3.6 volts / 0 degrees Celsius; VR = 1.2 volts. Wherein the voltage unit "V" is volts and the current unit ^ mA "is milliamperes.
VDQ1 VDQ2 需要寫入的 輸入輸出端 數量 總位元線 電流 G VBL 6V 4.67V 1 0mA 5.2V 4.67V 4.66V 0.3 15mA 5.07V 4.26V 4.67V 8 0mA 5.2V 4.67V 4.66V 2.53mA 4.81V 4.25V 8V 4.69V 1 0mA 7.24V 4.69V 4.67V 0.317mA 7.10V 4.27V 4.69V 8 0mA 7.24V 4.69V 4.65V 2.52mA 6.86V 4.26V 表格1-2。VCC/溫度=2.5伏特/攝氏90度；VR=1.2伏特。其 中電壓單位「V」爲伏特，電流單位「mA」爲毫安培。 1239015 13239twf.doc/006VDQ1 VDQ2 Number of input and output terminals to be written Total bit line current G VBL 6V 4.67V 1 0mA 5.2V 4.67V 4.66V 0.3 15mA 5.07V 4.26V 4.67V 8 0mA 5.2V 4.67V 4.66V 2.53mA 4.81V 4.25V 8V 4.69V 1 0mA 7.24V 4.69V 4.67V 0.317mA 7.10V 4.27V 4.69V 8 0mA 7.24V 4.69V 4.65V 2.52mA 6.86V 4.26V Table 1-2. VCC / temperature = 2.5 Volts / 90 degrees Celsius; VR = 1.2 Volts. The voltage unit "V" is volts and the current unit "mA" is milliamperes. 1239015 13239twf.doc / 006
VDQ1 VDQ2 需要寫入的 總位元線 G VBL 輸入輸出端 電流 數量 --------- 6V 4.68V 1 0mA 5.4V 4.68V 4.66V 0.344mA 5.22V 4.11V 4.68V 8 0mA 5.4V 4.68V 4.65V 2.74mA 4.89V 4.1 IV 8V 4.70V 1 0mA 7.44V 4.70V 4.67V 0.344mA 7.25V 4.12V 4.70V 8 0mA 7.44V 4.70V 4.65V 2.74mA 6.94V 4.10V 下列的表格2-1與2-2顯示圖6的電路的軟體模擬結果， 其中係以電阻器模擬位元開關的電阻。下列表格顯示兩種狀 況-（1)只有一個抹除後的晶胞需要寫入，或一條位元線需要 過抹除修正，以及（2)有八個抹除後的晶胞需要寫入，或八條 位元線需要過抹除修正。表格2-1與2_2顯示當總位元線電流 增加時，VBL的改變會因VRP變動而減低，也顯示總位元線 電流增加或減少時VDQ2的改變。模擬結果顯示，在每一次 模擬中，因位元線電流改變而造成的VBL改變都不超過0.17 伏特。模擬過程爲假設電阻Rt的溫度係數爲1000百萬分之一 (ppm)/攝氏1度。表格中的電壓VBL顯示位元線電流不爲0 時的位元線電壓（也就是說，位元線正在做寫入或過抹除修 正），以及位元線上沒有電流，同時QPL在「開啓」狀態時的 1239015 13239twf.doc/006VDQ1 VDQ2 The total bit line G VBL input and output current to be written --------- 6V 4.68V 1 0mA 5.4V 4.68V 4.66V 0.344mA 5.22V 4.11V 4.68V 8 0mA 5.4V 4.68 V 4.65V 2.74mA 4.89V 4.1 IV 8V 4.70V 1 0mA 7.44V 4.70V 4.67V 0.344mA 7.25V 4.12V 4.70V 8 0mA 7.44V 4.70V 4.65V 2.74mA 6.94V 4.10V The following tables 2-1 and 2 -2 shows the result of software simulation of the circuit of FIG. 6, where the resistance of the bit switch is simulated by a resistor. The following table shows two conditions-(1) only one erased unit cell needs to be written, or one bit line needs to be erased and corrected, and (2) eight erased unit cells need to be written, Or eight bit lines need erasure correction. Tables 2-1 and 2_2 show that when the total bit line current increases, the change in VBL will decrease due to the change in VRP. It also shows the change in VDQ2 when the total bit line current increases or decreases. The simulation results show that in each simulation, the VBL change caused by the bit line current change does not exceed 0.17 volts. The simulation process assumes that the temperature coefficient of the resistor Rt is 1000 parts per million (ppm) per degree Celsius. The voltage VBL in the table shows the bit line voltage when the bit line current is not 0 (that is, the bit line is being written or erased), and there is no current on the bit line. 1239015 13239twf.doc / 006
位元線電壓。當位元線上沒有電流而旦QPL在「開啓」狀態 時，VBL的電壓値會等於VDQ2。 表格2-1。VCC/溫度=3.6伏特/攝氏〇度；VR=1.2伏特。其中 電壓單位「V」爲伏特，電流單位「mA」爲毫安培。Bit line voltage. When there is no current on the bit line and the QPL is in the “on” state, the voltage of VBL will be equal to VDQ2. Table 2-1. VCC / temperature = 3.6 volts / degrees Celsius; VR = 1.2 volts. Among them, the unit of voltage "V" is volt, and the unit of current "mA" is milliampere.
VDQ1 VDQ2 需要寫入 的輸入輸 出端數量 VRP 總位元 線電流 VBL G VDP 6V 4.76V 1 1.22V 0mA 4.76V 5.2V 4.12V 5.24V 1.34V 0.33mA 4.79V 5.05V 4.63V 4.68V 8 1.20V 0mA 4.68V 5.2V 4.09V 5.12V 1.32V 2.59mA 4.68V 4.78V 5.0V 8V 4.77V 1 1.22V 0mA 4.77V 7.23V 4.11V 5.23V 1.34V 0.33mA 4.78V 7.09V 4.61V 4.70V 8 1.20V 0mA 4.70V 7.24V 4.08V 5.09V 1.31V 2.61mA 4.66V 6.84V 4.98V 表格2-2。VCC/溫度=2. 中電壓單位「V」爲伏特 5伏特/攝氏90度；VR=1.2伏特。 t，電流單位「mA」爲毫安培。 VDQ1 VDQ2 需要寫入 的輸入輸 出端數量 VRP 總位元 線電流 VBL G VDP 6V 4.76V 1 1.22V 0mA 4.76V 5.4V 3.29V 5.36V 1.37V 0.36mA 4.71V 5.19V 4.02V 4.69V 8 1.20V 0mA 4.69V 5.4V 3.27V 5.14V 1.36V 2.87mA 4.65V 4.83V 4.53V 8V 4.77V 1 1.22V 0mA 4.77V 7.43V 3.27V 5.22V 1.33V 0.36mA 4.60V 7.24V 3.91V 4.71V 8 1.20V 0mA 4.71V 7.44V 3.24V 5.21V 1.34V 2.88mA 4.60V 6.91V 4.47V 20 1239015 13239twf.doc/006 下列的表格3-1與3-2顯〒圖6電路的軟體模擬結果，不 過是用電晶體模擬位元開關的電阻。下列表格顯示兩種狀況 一（1)只有一個抹除後的晶胞需要寫入，或〜條位元線需要過 抹除修正，以及（2)有八個抹除後的晶胞需要寫入，或八條位 元線需要過抹除修正。表格3-1與3_2的結果類似於表格2] 與2-2，其中的VBL相對穩定（也就是說，總位元線電流改 變造成的最大VBL改變只有大約0.2伏特）。 表格3-1。VCC/溫度=3.6伏特/攝氏〇度；VR=;l2伏特。其中 電壓單位「V」爲伏特，電流單位「mA」爲毫安培〇 VDQ1 VDQ2 需要寫入 的輸入輸 出端數量 VRP 總位元 線電流 VBL G(閘 極電 壓） VDP 6.2V 4.77V 1 1.22V 0mA 4.77V 5.36V 4.01V 5.37V 1.38V 0.29mA 4.97V 5.16V 4.61V 4.68V 8 1.20V 0mA 4.68V 5.36V 3.98V 5.25V 1.35V 2.28mA 4.86V 4.74V 5.0V 8V 4.80V 1 1.22V 0mA 4.80V 7.17V 3.99V 5.38V 1.38V 0.29mA 4.97V 6.97V 4.61V 4.69V 8 1.20V 0mA 4.69V 7.17V 3.97V 5.24V 1.35V 2.28mA 4.85V 6.57V 4.99V L_____—---- 表格3-2。VCC/溫度^2·5伏特7攝氏90度；VR=1·2伏特。其 中電壓單位「V」爲伏特，電流單位「mA」爲毫安培。 21 1239015 13239twf.doc/006VDQ1 VDQ2 Number of input and output terminals to be written VRP Total bit line current VBL G VDP 6V 4.76V 1 1.22V 0mA 4.76V 5.2V 4.12V 5.24V 1.34V 0.33mA 4.79V 5.05V 4.63V 4.68V 8 1.20V 0mA 4.68V 5.2V 4.09V 5.12V 1.32V 2.59mA 4.68V 4.78V 5.0V 8V 4.77V 1 1.22V 0mA 4.77V 7.23V 4.11V 5.23V 1.34V 0.33mA 4.78V 7.09V 4.61V 4.70V 8 1.20V 0mA 4.70 V 7.24V 4.08V 5.09V 1.31V 2.61mA 4.66V 6.84V 4.98V Table 2-2. VCC / temperature = 2. The medium voltage unit "V" is 5 volts / 90 degrees Celsius; VR = 1.2 volts. t, the current unit "mA" is milliampere. VDQ1 VDQ2 Number of input and output terminals to be written VRP Total bit line current VBL G VDP 6V 4.76V 1 1.22V 0mA 4.76V 5.4V 3.29V 5.36V 1.37V 0.36mA 4.71V 5.19V 4.02V 4.69V 8 1.20V 0mA 4.69V 5.4V 3.27V 5.14V 1.36V 2.87mA 4.65V 4.83V 4.53V 8V 4.77V 1 1.22V 0mA 4.77V 7.43V 3.27V 5.22V 1.33V 0.36mA 4.60V 7.24V 3.91V 4.71V 8 1.20V 0mA 4.71 V 7.44V 3.24V 5.21V 1.34V 2.88mA 4.60V 6.91V 4.47V 20 1239015 13239twf.doc / 006 The following tables 3-1 and 3-2 show the software simulation results of the circuit in Figure 6, but they are simulated with transistors. Bit switch resistance. The following table shows two conditions: (1) only one erased cell needs to be written, or ~ bit lines need to be erased and corrected, and (2) eight erased cells need to be written , Or eight bit lines need erasure correction. The results in Tables 3-1 and 3_2 are similar to those in Tables 2] and 2-2, where the VBL is relatively stable (that is, the maximum VBL change caused by the total bit line current change is only about 0.2 volts). Table 3-1. VCC / temperature = 3.6 volts / degrees Celsius; VR =; 12 volts. The voltage unit "V" is volts, and the current unit "mA" is milliamps. VDQ1 VDQ2 Number of input and output terminals to be written VRP Total bit line current VBL G (gate voltage) VDP 6.2V 4.77V 1 1.22V 0mA 4.77V 5.36V 4.01V 5.37V 1.38V 0.29mA 4.97V 5.16V 4.61V 4.68V 8 1.20V 0mA 4.68V 5.36V 3.98V 5.25V 1.35V 2.28mA 4.86V 4.74V 5.0V 8V 4.80V 1 1.22V 0mA 4.80 V 7.17V 3.99V 5.38V 1.38V 0.29mA 4.97V 6.97V 4.61V 4.69V 8 1.20V 0mA 4.69V 7.17V 3.97V 5.24V 1.35V 2.28mA 4.85V 6.57V 4.99V L _____-------- Table 3- 2. VCC / temperature ^ 2.5 Volts 7 ° C 90 ° C; VR = 1.2 Volts. The voltage unit "V" is volts and the current unit "mA" is milliamperes. 21 1239015 13239twf.doc / 006
VDQ1 VDQ2 需要寫入 的輸入輸 出端數量 VRP 總位元 線電流 VBL G (聞 極電 壓） VDP 6.2V 4.78V 1 1.22V 0mA 4.78V 5.56V 3.11V 5.48V 1.41V 0.3 1mA 4.92V 5.30V 3.95V 4.69V 8 1.20V 0mA 4.69V 5.56V 3.10V 5.38V 1.39V 2.47mA 4.83V 4.75V 4.47V 8V 4.80V 1 1.22V 0mA 4.80V 7.38V 3.10V 5.56V 1.42V 0.3 1mA 4.98V 7.11V 4.00V 4.68V 8 1.20V 0mA 4.68V 7.36V 3.10V 5.31V 1.37V 2.48mA 4.77V 6.59V 4.44V 圖7繪示電路200的另一個實施例，其係控管受到總位 元線電流影響的電壓VDQ2。在本實施例中’差動放大器122 的正輸入端（positive input)耦接至電壓VBLRP。在調整電路 500B 中，VBLR 設定爲 VR*(Ra+ Rb)/Ra。VBLRP 等於 VBLR + i*Rt。圖7的電路使用VDQ2做爲差動放大器的輸入，也就是 說，VDQ2是通過一回饋線路，耦接到差動放大器的負輸入端 (negative input)。這個電路與前面敘述的圖6電路有相同的VBL 控制效果。VBLRP是產生電壓VDQ2的參考電壓。模擬位元 開關的電阻比位元線開關本身的電阻大上Μ倍，而非 M*Ra/(Ra+Rb)倍。耦接VBLR的Ρ型金氧半電晶體QPn的Ν 井應有一高於VBLR的電壓VCXX，理由請參考前面關於圖6 之中電壓VCX的說明。 22 1239015 13239twf.doc/006 如前所述，應能看出本幾明是提供一種電路與方法，使 區域位元線電壓不易受到總位元線電流的變化影響，做法是 補償位元線上的電壓損耗，例如跨越啓動位元線的位元線開 關的損耗，藉以改善寫入與過抹除修正效率，以及晶胞壽命。 在一實施例中，因爲來自電源的總位元線電流的變動，而造 成的區域位元線電壓VBL的變動，小於〇.2伏特左右。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當 視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 圖1是繪示習知的典型實施例中一個包括一快閃EEPROM 記憶體陣列，以及對陣列做寫入、抹除、讀取、和過抹除修 正電路的積體電路，。 圖2是繪示一個習知在寫入與過抹除修正的過程中，提 供位元線電壓給快閃EEPROM記憶體陣列中的記憶體的電路 晶胞。 圖3是繪示供應固定位元線電壓的電路設計圖。 圖4到圖7是繪示圖3的電路設計的實施例。 【圖式標示說明】 100、1000 :記憶體陣列 102 :記憶體晶胞 104 :位元線 106 :位元線交換電路 108 :行解碼器 23 1239015 13239twf.doc/006 110 :列解碼器 、 112 :電源或電荷泵電路 114 :處理器或狀態機 116 :感應放大器 118 :參考陣列 120 :資料閂或緩衝區 122 :差動放大器 124 :位元開關 126、130 :電容器 128 :漏電路徑電路 200 :位元線電流偵測與參考電壓調整電路 500、500A、500B :調整電路 R、Ra、Rb、Rt :電阻器 Req :等效電阻 D:金氧半電晶體汲極 G:金氧半電晶體閘極 S:金氧半電晶體源極 QbsO、Qbsl、Qbs2 : N型金氧半電晶體 QP0、QP1、QP2、QP3、QPLo、QPLn、QPn ·· P 型金氧 半電晶體 I、i :電流 DL(0)、DL(n)、PD[0]、PD[n]、PDN[0]、PDN[n]、VBLo、 VBLn、VBLR、VBLRP、VCC、VCX、VCXX、VD、VDP、VDQ1、 VDQ2、VPP、VR、VRP、VSL、WLo、WLn :電壓信號 24VDQ1 VDQ2 Number of input and output terminals to be written VRP Total bit line current VBL G (Sensor voltage) VDP 6.2V 4.78V 1 1.22V 0mA 4.78V 5.56V 3.11V 5.48V 1.41V 0.3 1mA 4.92V 5.30V 3.95V 4.69V 8 1.20V 0mA 4.69V 5.56V 3.10V 5.38V 1.39V 2.47mA 4.83V 4.75V 4.47V 8V 4.80V 1 1.22V 0mA 4.80V 7.38V 3.10V 5.56V 1.42V 0.3 1mA 4.98V 7.11V 4.00V 4.68 V 8 1.20V 0mA 4.68V 7.36V 3.10V 5.31V 1.37V 2.48mA 4.77V 6.59V 4.44V FIG. 7 shows another embodiment of the circuit 200. The voltage VDQ2 of the control tube is affected by the total bit line current. In this embodiment, the positive input terminal of the 'differential amplifier 122 is coupled to the voltage VBLRP. In the adjustment circuit 500B, VBLR is set to VR * (Ra + Rb) / Ra. VBLRP is equal to VBLR + i * Rt. The circuit in Figure 7 uses VDQ2 as the input to the differential amplifier, that is, VDQ2 is coupled to the negative input of the differential amplifier through a feedback line. This circuit has the same VBL control effect as the circuit of Figure 6 described earlier. VBLRP is a reference voltage that generates voltage VDQ2. The resistance of the analog bit switch is M times greater than the resistance of the bit line switch itself, rather than M * Ra / (Ra + Rb) times. The N-well of the P-type metal-oxide semiconductor transistor QPn coupled to VBLR should have a voltage VCXX higher than VBLR. For the reason, please refer to the description of voltage VCX in FIG. 6 above. 22 1239015 13239twf.doc / 006 As mentioned above, it should be seen that Ben Guiming provides a circuit and method to make the regional bit line voltage not easily affected by the change of the total bit line current. The method is to compensate the bit line. Voltage loss, such as the loss of a bit line switch across the enabled bit line, thereby improving write and over-erase correction efficiency, and cell life. In one embodiment, the variation of the regional bit line voltage VBL due to the variation of the total bit line current from the power source is less than about 0.2 volts. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. [Brief description of the figure] FIG. 1 is a diagram showing a conventional exemplary embodiment including a flash EEPROM memory array and a write, erase, read, and over erase correction circuit for the array. Circuit. FIG. 2 is a circuit diagram showing a conventional circuit for supplying a bit line voltage to a memory in a flash EEPROM memory array during writing and erasing correction. FIG. 3 is a circuit design diagram for supplying a fixed bit line voltage. 4 to 7 illustrate embodiments of the circuit design of FIG. 3. [Schematic description] 100, 1000: memory array 102: memory cell 104: bit line 106: bit line switching circuit 108: row decoder 23 1239015 13239twf.doc / 006 110: column decoder, 112 : Power supply or charge pump circuit 114: processor or state machine 116: sense amplifier 118: reference array 120: data latch or buffer area 122: differential amplifier 124: bit switch 126, 130: capacitor 128: leakage path circuit 200: Bit line current detection and reference voltage adjustment circuits 500, 500A, 500B: adjustment circuits R, Ra, Rb, Rt: resistors Req: equivalent resistance D: metal oxide semiconductor transistor drain G: metal oxide semiconductor transistor Gate S: Metal oxide semiconductor source QbsO, Qbsl, Qbs2: N-type metal oxide semiconductor QP0, QP1, QP2, QP3, QPLo, QPLn, QPn · P-type metal oxide semiconductor I, i: Current DL (0), DL (n), PD [0], PD [n], PDN [0], PDN [n], VBLo, VBLn, VBLR, VBLRP, VCC, VCX, VCXX, VD, VDP, VDQ1 , VDQ2, VPP, VR, VRP, VSL, WLo, WLn: voltage signal 24