TW200525740A - Scalable paired stack-gate flash cell structure and its contactless nor-type flash memory array - Google Patents

Abstract

A scalable paired stack-gate flash cell structure comprises a virtual-gate region being formed between two common-source regions, wherein the virtual-gate region comprises a pair of scalable stack-gate regions and a scalable common-drain region being formed between the pair of scalable stack-gate regions. Each of the two common-source regions comprises a common-source diffusion region and the scalable common-drain region comprises a common-drain diffusion region. Each of the pair of scalable stack-gate regions comprises a buried implant layer being formed in a surface portion of the semiconductor substrate. A deeper diffusion region is formed in the scalable common-drain region or each of the two common-source regions for forming a double-diffused channel in each of the pair of scalable stack-gate regions. The scalable paired stack-gate flash cell structure is used to implement a contactless NOR-type flash memory array.

Description

200525740 V. Description of the invention α) [Technical field to which the invention belongs] > The present invention relates to a stack-gate flash cell and a flash memory array thereof, and particularly to a miniaturizable pair ( The paired) interstellar cardia, cell, and field cell structure and their non-contact non-or type-flash memory array are related. [Previous technology] A stack gate technology is used for NAND) or a type of fast-pass channel> a penetrating area or a stack that penetrates and scrubs the gate and flashes down to a flash memory with a small line width (Mi 1 a non-or type is used as a memory array to form a column of the CHEI method cell has a gate length by the mum feature size) to define the application that is often stored as a stone horse and a non- (For file storage applications, in which the non-stack gate flash memory cell is usually written using the Fuller-Zhude Han (FN floating gate layer to penetrate a common source expansion; the non-type flash memory A full cross-section of a stack of cells in a non-OR flash memory array is written in the array by writing Fuller-Nordhandis, f electricity and a semiconductor substrate. In the figure, one of the gate regions is composed of a control gate conductive layer 104, a dielectric layer 103, an ice floating gate layer 102, and a penetrating dielectric layer 101. Flash memory thermoelectric method makes a half gate faster than a flash memory. A substrate separated by the separator to a scrub ternary memory cell from the floating gate layer packet memory less isolation

200525740 V. Description of the invention (2) Above P-type semiconductor substrate 1000; a double-diffused region 106a / 105a of the second conductivity type is formed by the semiconductor within a common source region A surface portion of the substrate 100 is a common source diffusion region 1 0 6 a / 1 having a highly doped n + diffusion region 106a formed within a lightly doped n_ diffusion region 105a. 0 5 a; and a highly doped n + diffusion region 106 b formed on a surface portion of the semiconductor substrate 100 in a common-drain region as a common-drain diffusion region 106 b. It is worth noting here that the lightly doped n-diffusion region 105a is used to eliminate the band-to-band penetration effect generated during scrubbing as shown in Fig. 1A. For a write operation, a relatively high positive voltage (10 volts to 12 volts) is applied to the control gate, layer 104, a moderately high positive voltage (6 volts to 8 volts) ) Is added to the common-diffusion region 106b, and the common-source diffusion region 106a / 10a is grounded. Hot electrons will be generated via a high-drain electric field and injected into the isolated floating gate layer 102. For a scrubbing operation, the electrons stored in the isolation floating gate layer 102 are applied with a relatively high negative voltage (-i 0 volt ^-12 volt) to the control gate conductive layer 1 〇 4 and a moderately high positive voltage (5 volts) is applied to the common source diffusion region 〇06a / 1 05a, and penetrates the common source diffusion region through the f floating gate layer 102 106a / 105a is extended by 4 parts of the penetrating dielectric layer 101 to be scrubbed. It can be clearly seen here that the write power of the hot electron injection method is large and the write efficiency is low. In addition, when the stack gate is reduced in length, the penetration effect will become the main concern; * When the junction depth is reduced, the extension of the common source diffusion area i 0 6a / 丨 0 5a will also be reduced. FIG. 1B shows the lightly doped n-diffusion region 105 in FIG. 1A.

200525740 V. Description of Invention (3) Except. The stack of flash memory cells stores electrons through the Fuller body substrate 100. This simple structure can write electrons into the half gate layer 102 within the array. Although the stack gate flash memory cell has a slow reading speed within the writing function of the non-stack gate flash memory cell. Therefore, a flash memory array of stacked flash memory cells in the present invention, wherein each of the miniaturizable ones includes at least a first conductive channel formed in a buried one of a second conductive type and a two conductive type. Penetration effect caused by layer ion implantation length. Another object of the present invention is a gate-lifting flash cell structure having a second and the second conductivity type, a highly doped type, non-contact non-or type flash memory array, and a further object of the present invention. The flash cell structure has a high-type second contactless non-or plastic flash with the plant layer and the second conductive plastic. An additional purpose of the present invention is that the scrubbing operation system will be located in the float. Scrubbing until the semiconductor is commonly used in the non-flash memory conductor substrate 100 penetrates into the floating flash memory array, the stacking rate is small, but a string element system is connected in series The purpose is to provide a micronizable couple to form a contactless non-or type dual-pair stacked gate flash cell structure of the flash cell, a miniaturizable double diffusion, a common source or sink diffusion region, and The first layer is formed by eliminating a micronization gate between the first layer and a buried type ion implantation layer of a first type of micronizable stack conductivity type to form a first column. A second type of miniaturizable second conductivity type is provided to connect the buried ion diffusion heterodiffusion regions to form a memory array. Provides a miniaturizable dual pair stack

200525740 V. Description of the invention (4) The gate flash cell structure has a unit cell size smaller than 4F 2. Other features and advantages of the present invention will be more apparent in the subsequent description. [Summary of the Invention] The present invention discloses a flash memory cell structure capable of miniaturizing a pair of stacked gates and a flash memory array having no contact non-or type. The miniaturizable stack gate flash cell structure is formed on a semiconductor substrate of a first conductivity type and includes at least one virtual gate region (VGR) formed between two common source regions (CSR), wherein the semiconductor The substrate includes at least one active region (AA) formed between two parallel shallow groove isolation regions (STI). The virtual gate region (VGR) includes at least a pair of micronizable stack gate regions and a micronizable common sink region (SCDR) formed between the pair of minimizable stack gate regions. Each of the pair of miniaturizable stack gate areas includes at least a second side wall dielectric cushion layer, a control gate conductive layer, an inter-gate dielectric layer and an integrated floating gate layer from top to bottom. The integrated floating gate layer includes at least one main floating gate layer formed on a penetrating dielectric layer within the active area (AA) and two extended floating gate layers formed on the side of the main floating gate layer. Above the side wall and above the side portions of the two etch-back first protruding field oxide layers within the two parallel shallow groove isolation regions. Each of the pair of miniaturizable stack gate regions further includes at least one dual diffusion source or drain region having a common source or drain diffusion region of the second conductivity type formed in a deeper diffusion region of the first conductivity type. A buried ion implantation layer inside and of the second conductivity type is formed on a surface portion of the semiconductor substrate under the penetrating dielectric layer, and one of them can be miniaturized and double-expanded.

Page 10 200525740 V. Description of the invention (5) A diffuse channel is formed between the common source or drain diffusion region and the buried ion implantation layer and is located on a surface portion of the semiconductor substrate. Each of the two common source regions (CSR) includes at least one double diffusion region formed in the active region (AA), a surface portion of the semiconductor substrate, and a first side wall dielectric pad layer formed in Above each side wall of the virtual gate region (VGR) and placed inside the penetrating dielectric layer and the two parallel shallow groove isolation regions (STI) within the active region (AA) The two back #second protruding field oxide layers are formed on a flat surface, and a highly doped source diffusion region is formed in the double diffusion region outside the first side wall dielectric pad layer. ; The miniaturizable common drain region (SCDR) includes at least a pair of third side wall dielectric pads formed on the side walls of the pair of miniaturizable stack gate regions (SGR) and placed on the flat surface A highly doped drain diffusion region above and of the second conductivity type is formed on a surface portion of the semiconductor substrate within the active region (AA) between the pair of third side wall dielectric pads, The highly doped drain diffusion region is connected to the buried ion implantation layer, and the highly doped source diffusion region is formed in the double diffusion. To constitute the zone type may be one first gate stack structure miniaturization. Each of the two common source regions (CSR) includes at least one first side wall dielectric layer formed on each side wall of the virtual gate region (VGR) and placed on the flat surface, And a highly doped source diffusion region of the second conductivity type is formed on a surface portion of the semiconductor substrate of the active region (AA) outside the first side wall dielectric pad; the micronizable common The drain region (SCDR) includes at least one double diffusion region formed on the surface portion of the semiconductor substrate between the pair of micronizable stack gate regions, and a pair of third side wall dielectric pads formed on the pair of micronizable On the side wall of the stack gate area (SGR) and on the flat surface

200525740 V. Description of the invention (6), and a highly doped drain diffusion region of the second conductivity type is formed in the double diffusion region between the pair of third sidewall spacers, wherein the highly doped diffusion region The heterogeneous diffusion region is connected to the buried ion implantation layer and the highly doped drain diffusion region is formed within the double diffusion region to form a second type of micronizable stack gate flash cell structure. The first / second type miniaturizable stack gate structure further includes a common-drain conductive island formed on the highly doped drain-diffusion region between the pair of third side wall dielectric pads and a common-drain conductive island. A source conductive pipeline is formed outside the pair of first side wall dielectric pads and placed within the highly doped source diffusion region and the two parallel shallow groove isolation regions within the active region (AA). The two back #three protruding field oxide layers are formed on a flat bed, and a planarized oxide layer is formed outside the first side wall dielectric cushion layer and placed on the common source conductive pipeline. Above, one of the metal bit lines and the common conductive island system are aligned on the active area (AA) to be simultaneously formed. A non-contact non-or-type flash memory array of the present invention includes at least a plurality of micronizable dual-pair stacked gate flash cell structures formed on a semiconductor substrate of the first conductivity type, wherein a plurality of active regions (AA ) And a plurality of parallel shallow groove isolation regions (ST I) are alternately formed on the semiconductor substrate. Each of the plurality of miniaturizable dual stack gate flash cell structures is formed between a pair of common source regions and includes at least a pair of miniaturizable stack gate regions (SGR) and a micronizable common drain region ( SCDR) is formed between the pair of miniaturizable stack gate regions (SGR). The plurality of common source conductive pipelines are perpendicular to the plurality of parallel shallow groove isolation regions (STIs) and each of the plurality of common source conductive pipelines is formed between a pair of first side wall dielectric pads and placed The third protrusion is etched back by one within each of the plurality of parallel shallow groove isolation regions (STI)

Page 12 Formula Implementation RT

200525740 V. Description of the Invention (7) The field oxide layer and a highly doped source diffusion region within each of the plurality of active regions (AA) are alternately formed on a flat bed, and a planarized oxide An object layer is formed between the pair of first side wall dielectric pads and is placed on each of the plurality of common source conductive pipelines; a plurality of common drain islands are formed on the pair of third side wall dielectrics. Between the underlayers and placed on the plurality of highly doped drain diffusion regions; and a plurality of metal bit lines together with the plurality of common drain islands within the scalable common drain region (SCDR) are aligned with the plurality The active area (AA ^) is formed at the same time. Each of the two-dimension i of the pair of miniaturizable stack gate areas (SGR) includes at least one second side bile dielectric layer, a control ^ f, A leisure dielectric layer and a plurality of integrated floating gates, each layer of which is composed of at least one main floating gate layer including each of the floating gates, and each of the plurality of active regions (AA) An internal penetrating dielectric layer is placed on the side of the main floating gate layer. Within the second isolation zone (STI), the two flashes are stacked on top of each other. The first type can be scaled down to form a plurality of first-type scaleable contact non-or type flashes. d; 冓 jj The present invention is a kind of the first-type elementless structure to form the micro-invention of the present invention: a pair of pairs ... a 5 flash memory array of the first type.

Page 13

200525740 V. Description of the invention (8) Refer to Fig. 2A and Fig. 2B, where Fig. 2A shows a first type of the present invention, a first type of shrinkable cascaded flash cell structure Microbial flash cell structure of Fengdui gate can be miniaturized; FIG. 2B shows a first type of miniaturizable stack gate flash cell according to the present invention. A sectional view of the metastructure. / As shown in FIG. F A, the first type of micronizable stack gate flash cell system is formed on a semiconductor substrate 300 of the first type of conductive pattern and includes at least one Γ micronized stack gate. Region (SGR), a common source region (CSR), and a / micronizable common sink region (SCDR). The minimizable stack gate region (SGR) is formed in the common source region (CSR) and Between the miniaturizable co-drain regions (SCDRs). The miniaturizable stack gate area (SGR) from top to bottom includes at least one second side wall dielectric cushion layer 3 1 6 a, a control gate conductive layer 3 0 9 b, and an inter-gate dielectric layer 3 0 8b, and an integrated floating gate layer 303c / 3〇6e, wherein the integrated floating gate layer 3 0 3c / 3 0 6e includes at least one main floating gate layer 3 0 3c formed in an active area (AA) one penetrating dielectric layer 3 02c and two extending floating gate layers 3 0 6 e (not shown) are formed on the side walls of the main floating gate layer 3 0 3 c and Two side portions of the two etched back first protruding field oxide layers 305b (not shown) disposed within the two parallel shallow groove isolation regions (STj) are disposed. The miniaturizable stack gate region (SGR) further includes at least an extension of a double diffusion source region 31 lb / 31 la within the common source region (CSR) and has a second conductivity type. A common source diffusion region 3 1 1 b is formed within a deeper diffusion region 3 1 1 a of the first conductivity type, and a buried ion implantation layer 3 〇c of the second conductivity type is formed on the Minimize the semiconductor substrate under the penetrating dielectric layer 30c within the stacked gate region (SGR)

Page 14 200525740 V. Description of the invention (9) A surface part of the plate 3 0 0. A first side wall dielectric cushion layer 3 1 2 a is formed on a side wall of the miniaturizable stack gate area (SGR) and placed in the penetration from the active area (AA) Dielectric layer 3 0 2c and two etch-back second protruding field oxide layers (3 0 5 c) of the two parallel shallow groove isolation regions (STI) located within the common source region (CSR) (not shown) (Illustrated) on a flat surface. The common source region (CSR) further includes at least a highly doped source diffusion region 3 1 1 c of the second conductivity type formed within the common source diffusion region 3 1 1 b and a common source conductive line 31 4b / 3 13b is a highly doped source diffusion region 311c and two parallel shallow groove isolation regions (a highly doped source diffusion region 311c) formed outside the first side wall dielectric pad 31 2a and placed within the active region (AA). STI) within a flat bed composed of two etch-back third protruding field oxide layers 3 0 5d (not shown) and a planarized oxide layer 315 a are formed on the first side wall The electric pad layer 31 2a is outside and placed on the common source conductive line 31 4b / 31 3b. The miniaturizable common drain region (SCDR) includes at least one third side wall dielectric cushion layer 3 1 7a formed on the other side wall of the miniaturizable stack gate region (SGR) and placed on the side wall. The semiconductor of the second conductivity type with a highly doped drain diffusion region 3 1 8a formed on the flat surface is formed within the active region (AA) outside the third side wall dielectric pad layer 3 1 7a A surface portion of the substrate 300 and a common-drain conductive island 3 1 9b are formed outside the third side wall dielectric pad layer 3 1 7a and disposed on the highly doped drain diffusion region 3 1 8a. A metal bit line 3 20a and the common drain conductive island 3 1 9 b are aligned on the active area (A A) to form simultaneously. This first type of miniaturizable stack gate flash cell can be written using three methods. The first writing method is to add a positive voltage of 3 volts to 6 volts to

Page 15 200525740 V. Description of the invention (ίο) The double-diffusion channel 31 la is turned on just above the conductive layer 3 0 9b of the control gate, and the conductive island 31 9b together with the bit line 32 0a is applied with a positive voltage. 1 volt to 3 volts, and the common source conductive line 3 1 4b and the semiconductor substrate are grounded. Hot electrons are generated by a high lateral electric field near the interface between the double diffusion channel 3 11 a and the buried ion implant layer 3 0 1 c, and then injected into the integrated floating gate layer 3 0 3 c / 3 0 6 c. This writing method is very similar to the traditional split-gate middle-channel hot electron injection (MCHEI) method, which has a smaller writing current and higher writing efficiency. The second writing method is to intermodulate the applied voltages applied to the common source conductive line 314b / 313b and the common drain conductive island, and the hot electrons will be controlled by the double diffusion channel 3 1 1 a and the common source diffusion area 3 1 1 The high lateral electric field at the junction between b is generated, and then injected into the integrated floating gate layer 3 0 3 c / 3 0 6e. This writing method is very similar to the traditional hot electron injection (CHEI) method, but because it has a short channel length, its writing power is small and writing efficiency is high. The third writing method is to add a high positive voltage of 10 volts to 12 volts to the control gate conductive layer 3 009 b, the common drain conductive island 3 1 9b and the bit line 3 2 0 a is grounded, and the common source conductive line and the semiconductor substrate 3 0 0 are floating (f 1 0 at 丨 ng), the electrons in the buried ion implantation layer 3 0 1 c will pass through Fuller —Nordheim (F n) penetration method penetrates into the integrated floating gate layer 3 0 3 c / 3 0 6 e to obtain a very low write current. Since the present invention provides that the common source diffusion region 3b has a deep junction, the depth provides a large scrubbing surface area, so the first type of miniaturizable stack gate flash cell is smaller than the traditional source edge The scrub method is more efficient. In addition, the first type of miniaturizable stack gate flash cell can apply a relatively high negative voltage to the control gate via the buried ion implantation layer 3 0 1 c.

200525740 V. Description of the invention (11) A positive voltage is applied to the metal bit line 309b and a positive voltage is applied to the metal bit line 32a = to perform a bit-by-bit scrubbing, wherein the common source conductive line 314b / 3 0 3b and this semiconductor substrate 300 are floating. Figure 2B shows a cross-sectional view of a second type of miniaturizable stack flash flash cell structure of the present invention. Comparing Fig. 2A and Fig. 2B, it can be clearly seen that 'Fig. 2 β can be obtained by the doped structure and its extensions located within the common source region (CSR) and the micronizable common drain region (SCDR). Intermodulation is obtained, so further discussion will not be repeated here. Similarly, the second type of miniaturizable stack gate flash cell can be written via the intermodulation of the source / drain voltage plus the source of the first type of miniaturizable stack gate flash cell structure. It can be clearly seen here that the second type of miniaturizable stack gate flash cell provides electrons from the integrated floating gate layer 303c / 306e to the buried ion implantation region 301c. Dehan penetrates and has a large area for scrubbing, however, the electron from 31 lb of the common source diffusion region to the integrated floating gate layer 3 0 3c / 3 0 6e has a Fuller-Nordhan penetration ratio that is larger than that The writing of the first type of miniaturizable stack gate flash cells has a smaller surface area. Similarly, the second type of miniaturizable stack gate flash cell can be written via the aforementioned middle channel hot electron injection (MCHEI) or hot electron channel injection (CHE I) method. Please refer to FIG. 3A to FIG. 3I, which disclose the fabrication of a miniaturizable dual-stack stack gate flash cell structure of the present invention and its non-contact non-or flash memory array with an automatic alignment product. Process steps and sectional views of a shallow groove isolation (ST I) structure for a bulk floating gate structure. It is worth noting here that the shallow groove isolation structure shown in FIGS.

$ 17 pages 200525740 V. Description of the invention (12) The self-aligning integrated floating gate structure is only used to make the miniaturized dual-stack stack interstitial cell 70 structure and its non-contact non-or type flash memory An example of an array 'Other self-aligning integrated floating gate structures can also be used

Fig. 2A shows a buried ion implantation layer 301 of a second conductivity type formed on a semiconductor substrate 300 of a first conductivity type. One table = 1 part, and then a penetration dielectric layer. 3 0 2 is formed on the buried ion 301 and a first conductive layer 3 0 3 is formed on the penetrating dielectric layer 2. Next, a covering dielectric layer 304 is formed on the first conductive layer. on. The semiconductor substrate 300 may be a #M I 70% of the first conductivity type, and within a well region of the second conductivity type. The buried layer ions are formed on a surface portion of a conductive substrate 300 by implanting a dopant QT conductive substrate 300 across a sacrificial oxide layer (not shown). The penetrating dielectric!. • At least one thermal (therma 1) silicon dioxide layer or one nitride gate 1 Y 丨 ^ 6 d) thermal oxide layer, its thickness is between 70 angstroms and 1 2 0 angstrom 1 4 first conductive layer 3 0 3 contains at least one doped polycrystalline silicon layer 1 doped amorphous silicon layer and is deposited using a low pressure chemical vapor deposition (Lpcv)) method Between Angstroms and 2000 Angstroms. The overlay contains at least one nitride layer and the utilization area is between 100 Angstroms and 300 Angstroms. Μ /, order

Yifu f shows a mask photoresistor (PR1) step (not shown), which is used to determine the location of the parallel shallow groove isolation area (sti); and then cover the parallel shallow groove isolation area (STI) the overlay " electrical layer 304, the first conductive layer 303, the penetrating dielectric layer 302, and

Page 18 200525740 V. Description of the invention (13) The semiconductor substrate 300 is sequentially etched by anisotropic dry etching to form a shallow groove within the semiconductor substrate 300. The shallow grooves within the semiconductor substrate 300 are between 400 angstroms and 800 angstroms. FIG. 3C shows that a planarized field oxide layer 3 05 a is used to fill the voids within each of the plurality of parallel shallow groove isolation regions (S T I). The planarized field oxide layer 3 0 5 a is composed of silicon dioxide, glass-filled (p-g 1 ass) or boro-phosphorus glass (BP-glass) and uses high-density plasma (HDP) CVD and plasma. Reinforced (PE) CVD or LPCVD methods are used to deposit. A thick oxide layer 3 05 is first deposited to fill the voids within each of the plurality of parallel shallow groove isolation regions (ST 丨), and then chemically- The mechanical polishing (CMP) method planarizes the thick oxide layer 305 deposited and covers the dielectric layer 304 with the shape as a polishing stop. It is worth noting here that, before the planarized field oxide layer 3 0 5 a is not formed, a thermal oxidation process may be performed to form a 1 iner oxide layer (not shown) on the semiconductor surface of the groove. To eliminate defects caused by grooves. FIG. 2D shows that the planarized field oxide layer 3 0 5 a located within each of the plurality of parallel shallow groove isolation regions (s τ 丨) is back to a predetermined thickness; then, a planarization is performed. The conductive layer 3 0 6a fills a gap in each of the plurality of parallel shallow groove isolation regions (STI). The planarized conductive layer 3 06a is composed of doped polycrystalline silicon or doped amorphous silicon and is stacked using LpcVD ^. A conductive layer 3 06 is deposited on the surface of a structure, and then The CMP method is used to planarize the stacked conductive layer 306, and the formed covering dielectric layer 304a is used as a smoothing stop layer.

Page 19, 200525740 V. Description of the invention (14) Figure 3E shows the planarized conductive layer 3 within each of the plurality of parallel shallow groove isolation regions (STI). 3 063 is back and forth using non-isotropic dry etching Etching to a top surface level of the shaped first conductive layer 303a to form an etch-back conductive layer 306b within each of the plurality of parallel shallow groove isolation regions (STIs). FIG. 2F shows that a pair of side wall dielectric spacers (Spacer) g07a are formed on the side wall adjacent to the forming and covering dielectric layer 3 0 4 a and are located in the plurality of parallel shallow groove isolation regions (STI). Within each of them. The pair of side wall dielectric cushion layers 3 0 7a is composed of nitride nitride and is stacked using the lpcvd method. A dielectric layer 307 (not shown) is first deposited on a formed structure surface, and then One thickness of the stacked dielectric layer 3007 is returned. FIG. 3G shows that within each of the plurality of parallel shallow groove isolation regions (ST 丨), the etch-back conductive layer 3 0 6b between the pair of side wall dielectric pads 3 0a is anisotropic The ground is carved into a tape red side wall structure. FIG. 3A shows that the formed overlying dielectric layer 304a and the pair of side wall dielectric layers 30 7a are added and removed by using hot phosphoric acid or anisotropic dry etching. It can be clearly seen here that an integrated floating gate structure 3 0 3a / 3 0 6c includes at least one shaped first conductive layer 3 03a and two etched back conductive layers 3 0 6c, which are used to increase each stack Coupling ratio of gate flash cells (c0Up 1 ing ratio) 0 Figure III 1 shows an intergate dielectric layer 3 08 is formed on the surface of a structure shown in Figure III. ; Then, a second conductive layer 3 0 9 is formed on the inter-gate dielectric layer 3 0 8; then, a mask dielectric layer 3 1 0 is formed on the second conductive layer 3 0 9 . The Intermediate

Page 20 200525740 V. Description of the invention (15) _-- 'The electric layer 30 is a silicon dioxide / nitride nitride / silicon dioxide (N〇) structure and [^ silicon— (0N0) structure or Between 100 Angstroms and 300 Angstroms. The first] conductivity / electrical J ::: evening: degree-based crystalline silicon layer and using LPCVD method to stack ^ ^ 9 is a doped complex (W) ,,,-, #,, Λν ?.-Its thickness is referred to At 250 angstroms and 500 angstroms. Between Egypt]. With these two, doped with polycrystalite can further implant the second conductive] two =. Along the active area (AA) in FIG. 31, as shown in FIG. 5A, it is shown in FIG. 4A. It can be clearly seen here that only a single photoresist (PR1) step is required to form a shallow groove isolation (SU) with a movable, quasi-integrated floating gate structure 3〇3a / 3〇6c. )structure. It is worth emphasizing here that a pair of conductive side wall cushioning layers (not shown) are formed on the side wall adjacent to the first conductive layer 30a formed to replace the planarized conductive layer 3 shown in FIG. 3B. 〇6a, wherein the forming and covering dielectric layer 304a is removed before forming the pair of conductive sidewall spacers. See Fig. 4A to Fig. 4K, which shows that a first type of the present invention can be manufactured. The structure of the miniature paired stack gate flash cell structure and the continuation of the first type of contactless non-or type flash memory array are shown in FIG. FIG. 4A shows a cross-sectional view of a multi-layer structure within an active area (AA) along an I_Γ line indicated in FIG. 3I. FIG. 4B shows that a photomask (PR2) dream step (not shown) is used to form a plurality of virtual stacked gate regions (VGR) alternately formed on the semiconductor substrate.

200525740 V. Description of the invention (16) 3 0 0; then, the mask dielectric layer 3 1 0, the second conductive layer 3 0 9, which is located within each of the plurality of common source regions (CSR) The inter-gate dielectric layer 3 0 8 and the complex integrated floating gate structure 3 03a / 30 6c are sequentially removed using the non-isotropic dry-cut method; and the first protruding field oxide layer of the money back 305b (see Figure III) is etched back to a top surface level of the penetrating dielectric layer 302a at the same time to form a second protrusion that is located within each of the plurality of active regions (AA). Field oxide layer 3 0 5 c (not shown); and then, forming a surface portion of the semiconductor substrate 3 0 0 doped within the active area (AA) in an automatic alignment manner The complex double diffusion region 3 1 1 b / 311a. Each of the plurality of double diffusion regions 31 lb / 3 11 a includes at least a deeper diffusion region 311 a of the first conductivity type formed in a common source diffusion region 3 1 1 b of the second conductivity type. The deeper diffusion region 3 11 a is moderately doped and the dopants are implanted across the penetrating dielectric layer 30 2 a by the auto-alignment method in the region between adjacent virtual gate regions (VGR). A surface portion of the semiconductor substrate 300 within a plurality of active regions (AA), and then the implanted dopants are driven to a desired depth by using a high temperature furnace or a rapid thermal annealing (RTA) system . Similarly, the common source diffusion region 3 1 1 b is formed using the same process steps of the deeper diffusion region 3 11 a. It can be clearly seen here that a micronizable double diffusion channel of the first conductivity type is formed in the common source diffusion region 3 11 b of the second conductivity type and the buried ion implantation of the second conductivity type. The three parts of the semiconductor substrate 300 between the layers 3 0 1 b can be easily controlled to obtain a short channel length. ^ ^ It is worth noting that the common source diffusion region 3 1 1 b may be highly doped (modealy-doped) or moderately-doped.

Page 22 200525740 V. Description of the invention (17) Figure 4c shows that a pair of first side wall dielectric pads 312a are formed adjacent to each other, and are placed on the side walls of the pseudo gate area (VGR) and placed in the plurality of total Source region (CSR) =: one within a portion of the flat surface; then, ion implantation is performed in an automatic j-alignment manner to form the complex conductivity of the second conductivity type = common source diffusion region 31 lc is within the complex of each of the plurality of common source regions (CSR), within the diffusion region 3 11 b. The pair of first side wall dielectric pads 3 丨 2 & is composed of tSi dagger f / kg and is stacked using LPCVD method, and a two-Si structure chart is first stacked to show the structure table, ... A thickness of the deposited dielectric layer 3 1 2 is then etched back. Figure 4D shows that the penetrating dielectric layer 3 0 2a located on the first side of the pair uses: Rong: 2 layers 312a on the pair of -side wall dielectric pads: ^: S :: The in-situ oxide layer 305c is composed of the highly doped sequence residues within each of the etched-back second protruding fields at the same time to form each 侗, κ of the isolation region (STI) of the complex active region (AA). Alternating area 311 c and the plurality of parallel shallow groove layers 305d (not shown) = ^ = one 2 times = third protruding field oxide planarization third conductive sound 3 1 卩 / and a flat bed ; Then, the pair i-gamma-a system within one by one is formed in each of the plurality of common source regions (CSR). A gap between the planarized third conductive screen f wall dielectric pad 3128 and the LPCVD method is used to deposit "", which is composed of doped polycrystalline silicon and uses the complex common source region (csut product). A third conductive layer 313 (not shown) within the pair of first side wall dielectrics: gaps within the pad layer 3 1 2a ^ gate = mother, and then using CMP * to stack the first The mask dielectric layer 31a serves as a

200525740 V. Description of the invention (18) Figure 4E shows that the planarized third conductive layer 3 1 3 a located within each of the plurality of common source regions (CSR) is etched back to a predetermined thickness to form a The common source conductive layer 31 3b; then, the common source conductive layer 3b in each of the plurality of common source regions (CSR) is implanted with a high-dose dopant of the second conductivity type. FIG. 4F shows that a common source conductive layer 3 1 4b is formed on the common source conductive layer 3 丨 3b within each of the plurality of common source regions (CSR); then, a planarized oxide layer 3 5a is formed between the pair of first side wall dielectric pads 31 2a and is placed on the common source conductive line 314b / 3 13b within each of the plurality of common source regions (CSR). The covering conductive layer 314b is composed of siliconized crane (WSi 2) or tungsten and is stacked by LpcVD method or sput tering, and is formed by the same process steps for manufacturing the common source conductive layer 3Ub ^. It is worth noting here that the common source conductive pipeline 3 14d / 3 13b can be replaced by a highly doped polycrystalline silicon layer or a tungsten-rhenium layer lined with a barrier metal layer. FIG. 4G shows that the mask dielectric layer 3 1 Oa located within the plurality of virtual gate regions (VGR) is selectively added and removed by using hot phosphoric acid or anisotropic dry etching. Then, a pair of first The two side wall dielectric pads 3 丨 6a are the formed second conductive layers formed on the side walls adjacent to the common source region (CSR) and placed within each of the plurality of virtual regions (, VGR). A part of the & plane of layer 3 0 93 defines a pair of shrinkable stack gate regions (SGR) and simultaneously defines a shrinkable common sink region (SCDR), as shown in Fig. 4; Perform a non-critical mask photoresistor (PR3) step to place a photoresistor PR3 in each of the plurality of common source regions (CSR) and adjacent second

200525740 V. Description of the invention (19) A dielectric pad layer 3 1 6 a is integrated with a dielectric, and then etched back. Part of the surface. A thickness of the pair of first dielectric layers 3 1 6 composed of silicon nitride and using the LPCVD electrical layer 3 1 6 (not shown) is shown on the second side of the pair. The wall dielectric two conductive layer 3 0 a. The shaped inter-gate dielectric floating gate structure 3 0 3b / 3 0 6d is formed by sequentially adding a field oxide layer 3 0 5 b at the same time by etching back to the surface level of the part to form A flat surface, PR3, and a dielectric layer on the side wall, are stacked on top of the structure surface of the stack.) The layer 3 0 6 a between the cushion layer 3 1 6 a and the complex number is removed and the remnant penetrates the dielectric layer. Electrical layer 302b; then, remove the

μ, 4 1 shows that a pair of third side wall dielectric pads 30 7a are formed in the miniaturizable common subregion (SCDR) and the side walls of the miniaturizable stack gate region (SGR) And placed on the flat surface; then, ion implantation is performed in an automatically aligned manner to form the plurality of highly doped non-diffused regions 31 8a of the second conductivity type in the micronizable common-drain region ( The surface portion of the semiconductor substrate within the plurality of active regions (AA) between the pair of third side wall dielectric chirp layers 3 1 7a within SCDR). The pair of third side wall dielectric pads 3 丨 7a are composed of silicon dioxide or silicon nitride and are stacked using the LPCVDE method. A dielectric layer 317 (not shown) is first deposited on one On the surface of the structure, and then return a thickness of the stacked dielectric layers 3 丨 7.

FIG. 4J shows that the flat surface located between the pair of third side wall dielectric pads 3 and 7a is an anisotropic etch to form a flat bed within the micronizable common drain region (SCDR). ; Then, a planarized common-sinking conductive layer 3198 is formed on the pair of third sides within the micronizable common-sinking region (3 (: 1) 10)

Page 25 200525740 V. Description of the invention (20) Between the wall dielectric pads 3 1 7a. The planarized common-drawing conductive layer 3 丨 9a is composed of doped polycrystalline spar and is stacked by LpCVD method. It is further implanted with a high-dose dopant (not shown) Show). It is worth thinking here, that a refractory metal silicide layer (not shown) can be formed using an auto-aligned silicidation process within the micronizable region (SCDR). The planarized common-drain conductive layers 31 to 9a. The refractory metal petrified layer is composed of titanium silicide (Ti Si 2) or cobalt silicide (CoS 丨 2). ^ Figure 4 shows that a metal layer 32 0 (not shown) is formed on a flat surface as shown in Figure 4 J; the metal layer 32 0 together with the inside of the micronizable common area (SCDR) The planarized common-drain conductive layer 31 9a is formed by aligning over the active area (AA) with a mask photoresist (PR4) step (not shown) to form a plurality of metal bit lines 3 2 0 a is integrated with the plurality of total conductive islands 3 9b within the micronizable common area. The metal layer 3 2 0 is a tungsten (ψ), aluminum (a 1), or copper (Cu) layer formed on a barrier metal layer, such as a titanium nitride (TiN) or tantalum nitride (TaN) layer. The mask photoresist (PR4) step may include at least a plurality of mask photoresist PR4 formed into a beveled side wall structure or a plurality of mask dielectric layers formed by a plurality of mask light 1¾ PR4 and a pair of sides A wall dielectric pad is formed on a side wall of each of the plurality of mask dielectric pads to serve as a hard mask to etch the metal layer 3 2 0 and the micronizable common drain region. The planarized common-drain conductive layer 3 1 9 a. It can be clearly seen here that the present invention only needs three rigorous mask photoresist steps (PR1, PR2, and PR4) and one non-rigid mask photoresist step (PR3) to produce a first type of micronizable Fast flashing of dual-pair stack gate

Page 26 200525740 V. Description of the invention (21) The cell structure is indicated by a dashed square in Figure 4K, and its first type of non-contact non-or type flash memory array. Please refer to FIG. 5, which shows a brief top-view layout diagram of the flash memory cell structure of the first type of miniaturizable dual-pair stack gate of the present invention and the first type of contactless non-or type flash memory array. ; And along AA, a brief cross-sectional view of the line is shown in Figure 4K. FIG. 5 shows that a plurality of active regions (AA) and a plurality of parallel shallow groove isolation regions (STI) are alternately formed on a semiconductor substrate 300; a pair of micronizable word line regions (WL) 3 0 9b are formed on the semiconductor substrate 300. Each of the plurality of virtual gate regions (VGR) is formed between two common source regions (CSRs), and the plurality of common drain islands 31 9b are formed within the scalable common drain region (SCDR). A pair of third side wall dielectric pads 3 1 7 a are placed on the plurality of highly doped drain diffusion regions 318 a within the plurality of active regions (AA) and the two common source regions (CSR) Each of them contains at least one common source conductive line (CSBL) 31 4d / 3 13d formed between a pair of first side wall dielectric pads 3 1 2 a and placed in the isolation region by the plurality of parallel shallow grooves ( STI) are formed alternately in each of the etchback third protruding field oxide layer 30 5b and a highly doped source diffusion region 3 1 1 c in each of the plurality of active regions (AA) On a flat bed; each of the pair of micronizable word lines (WL) 3 0 9b includes at least one control gate conductive layer 3 0 9b formed on a gate dielectric layer 3 08b is further formed on the plurality of integrated floating gates 30 3c / 3 0 6e, wherein each of the plurality of integrated floating gates 30 3c / 3 0 6e includes at least one main floating gate 30 3 c and its two extended floating gate layers 3 0 6e; and a plurality of metal bit lines (BL) 32 0a and the micronizable common drain region (the complex total drain conductive island 3191 within 30010) are integrated even

Page 27 200525740 V. Description of the invention (22) The junction is formed by aligning on the plural active area (AA). Figure 5 also shows that a unit cell (UC), as indicated by a dashed box, is equal to 2ρ · X, where X is a scaleable coefficient and may be equal to 2 f or less than / greater than 2 ρ. Because, 'the unit cell size (uc) can be miniaturized and the virtual gate region (VGR) > and the first and second elements used to define each of the pair of miniaturizable stack gate regions (SGR) The width of the two side wall dielectric pads 3 丨 6 a is controlled. Please refer to Fig. 6A to Fig. 6e, which show various cross-sectional views indicated in Fig. 5. FIG. 6A shows a schematic cross-sectional view taken along a line B--B in FIG. 5, in which a common source conductive line 314b / 31 3b is formed in each of the plurality of parallel shallow groove isolation regions (STI). An internal # 3rd protruding field oxide layer 305d and an erbium-doped source diffusion region 3 located within each of the plurality of active regions (AA) and formed within a double diffusion region 311b / 311a 1 1 c on a flat bed composed alternately; a planarized field oxide layer 315a is formed on the common source conductive line 314b / 3 1 3 b; and a plurality of metal bit lines 3 2 〇a Alternately formed on the planarized oxide layer 3 1 5a and formed and etched by aligning the mask photoresist (PR4) step on the multiple active area (AA) as described in FIG. . FIG. 6 β shows a schematic cross-sectional view along a CC line in FIG. 5, in which a first side wall dielectric cushion layer 3 丨 2a is formed by the plurality of parallel shallow groove isolation regions (STI). ^ One back-to-back second protruding field oxide layer 305c and one penetrating dielectric layer 302c over a double diffusion region 311b / 311a within each of the plurality of active regions (AA) And a plurality of metal bit lines 3 2 0a are alternately formed on the first side wall dielectric pad 31 2a and borrow

Page 28 200525740 V. Description of the invention (23) The mask photoresist (PR4) step is aligned on the multiple active area (AA) to form and engrav. FIG. 6C shows a schematic cross-sectional view taken along a line d-D in FIG. 5, in which a control gate conductive layer 3 0 9 b is formed on a gate dielectric layer 3 8 b as a word. Line (WL); the inter-gate dielectric layer 3 0 8b is formed on the plural integrated floating gate layer 303c / 306e and is placed between the adjacent integrated floating gate layer 3 0 3 c / 3 0 6 e An etchback of the first protruding field oxide layer over 3 0 5 b 'wherein the e plural complex integrated floating gate layer 3 0 3 c / 3 0 6 e each contains at least one main floating gate layer 3 0 3 The Buddha is formed on a buried ion implantation layer 3 0 1 c above a penetrating dielectric layer 3 0 2 c and two extended floating gate layers 3 0 6 e are formed on the main floating gate layer 3 0 3 c is on the side wall and is positioned adjacent to the side part of the first protruding field oxide layer 3 0 5 b; a second side wall dielectric pad layer 3 1 6 a is formed on the side wall A control gate layer 3 0 9 b; and a plurality of metal bit lines (BL) 3 2 0a are alternately formed on the second side wall dielectric pad layer 316 a and aligned with the plurality of active regions (Aa). FIG. 6D shows a schematic cross-sectional view along an eE line in FIG. 5 where one of the third side wall dielectric pads 3 1 7a is formed in each of the plurality of active regions (AA). A buried dielectric ion implantation layer 301c, a penetrating dielectric layer 3 0 2c and an etch-back second protruding field oxide layer 3 within each of the plurality of parallel shallow groove isolation regions (STI) 〇5 c is formed on a flat surface alternately; and a plurality of metal bit lines (BL) 3 2 0a are alternately formed on the third side wall dielectric pad layer 317a and through the The mask photoresist (PR4) step is aligned on the plurality of active areas (AA) to form.

Page 29, 200525740 V. Description of the invention (24) ~ ', $ 5, not a brief cross section along a line FF in Figure 5, metal only element line (BL) 3 2 0a is electrically conductive with the complex number The island is replaced by her, and it is placed in the plural active area (AA) above the plural high 22 L t ί Ϊ 3 1 8a and the plural conductive island 3 1 91) is formed in the f lamp The adjacent etch-back third protrusion within the shallow trench isolation region (STI) is a small portion of the upper service layer 3 0 5 d. As shown in FIG. 4K, the step “f number ΐ t S” may include at least a plurality of mask photoresistors PR4 aligned on the Ξ ί 5 ί UA) and #etched into a beveled side wall structure or Plural Φ: Two, one side is formed by a plurality of mask photoresistors PR4 and a side wall is A —: t ΐ 之上 Each side wall of the dielectric layer of the plurality of masks is used as ^: a, The mask is used to form the complex metal bit line (BL) 32〇a and the complex octave, and the electric island 3 1 9b is integrated and connected, as shown in FIG. 6E. Now, see FIGS. 7A to 7 κ, which reveals the manufacturing of a first type of micronizable dual-pair stack gate flash cell structure and its continuation of non-or-type non-or flash memory array. FIG. Comparing Fig. 4K and Fig. 7κ, it can be clearly seen that the dopant structure within each of the plurality of common source regions (CSR) in Fig. 4K is formed in the complex number in Fig. 7K that can be miniaturized Within each of the common drain regions (SCDRs) and the plural miniaturizable common drain regions in FIG. 4K, the dopant structure within each of the CDRs is formed as shown in FIG. Within each of the plurality of common source regions (CSRs). Therefore, the detailed process steps of FIG. 7A to FIG. 7κ and their other views are not repeated. Similarly, a brief top-view layout diagram shown in FIG. It can still be used to describe the structure of the second type of miniaturizable dual-stack stacked flash cell and its second type of non-contact non-or type flash memory array. However, the

Page 30 200525740 V. Description of the invention (25) Various different cross-sectional views can be described by the following amendments: One dopant structure in Fig. 6A is 3 1 1 c / 3 1 1 b / 3 11 a. Dopant structure 318 & to replace; one dopant structure 3111) / 311 & in FIG. 6 may be replaced by one dopant structure 3 0 1 c; one dopant structure 3 0 1 in FIG. 6e c can be replaced by a dopant structure 3 丨 丨 b / 3 丨 丨 c; and a dopant structure 3 1 8 a in FIG. 6E can be replaced by a dopant structure 3 1 1 c / 31 lb / 31 la instead. It can be clearly seen here that the rigorous and non-rigid mask photoresist steps required to form FIG. 7κ are the same as those in FIG. 4]. (It is worth emphasizing that the highly doped drain diffusion region in FIG. 318a may be formed in a common diffusion region 318b (not shown) of the second conductivity type and the highly doped source diffusion region 3 1 8a in FIG. 7K may be formed in a second conductivity type Within the common source diffusion region 31 8b (not shown). The common source / drain diffusion region 318b includes at least one moderately or highly doped diffusion region. According to the above description, the features and advantages of the present invention can be summarized as ( a) The miniaturizable dual-stack gate cell structure of the present invention provides a pair of miniaturizable stack gate region (SGR) and a micronizable pooling region (SCDR) to obtain a micronizable unit cell The size is less than or equal to 4F 2. (b) The miniaturizable dual-stacked stack gate cell structure of the present invention and its non-contact non-or flash memory array can use less rigorous and non-rigid mask photoresistors. Steps to manufacture.

200525740 V. Description of the invention (26) (C) The micronizable couple region and the micronizable common zone of the present invention provide a total of additional mask photoresist steps. A variety of different impurity distributions are not required (d) The micronizable pair of the present invention-a micronizable gate length of the _pair 3: ^ structure provides the element without the need to worry about the puncture effect. (B) Side stack gate flash cells (e) The micronizable couple of the present invention

Reducing the size of the stacker gate intermediary cell; a stack; via: the structure provides the pair of) penetrating, middle channel hot electron injection method, ft by; Le-Nordheim (FN

Si: come to write efficiently and by Fuller-ϊίίί :; scrubbing efficiently with edge or edge. The region that penetrates to the source is interspersed with the source and the number of spreading plates is not complex. The donor is doped and the derivative is high. Recalling in the inscription, the interrogation of the flash phase island is fast and the electrical connection type resistance is eliminated or the electric drain is eliminated. The number of non-linear reconnection points is blocked. Compared with the present invention, although the circuit diagram and the description of the f C circuit are specifically illustrated and described with reference to the attached examples or connotations, they are merely representative statements and not limitations. Furthermore, the present invention is not limited to the details listed, and those skilled in the art can also understand that changes in various shapes or details can be made without departing from the true spirit and scope of the present invention.

200525740 V. Description of Invention (27) It is also within the scope of the present invention. Η · Ι Page 33 200525740 Brief Description of Drawings Figures 1A and 1B show a brief cross-sectional view of a stack gate flash cell in the prior art, of which Figure 1A shows a structure with a dual diffusion source and a single diffusion drain. A cross-sectional view of a stack gate flash cell of a structure; FIG. 1B shows a cross-section view of a stack gate flash cell with a single diffusion source / drain structure. FIG. 2A and FIG. 2B show a schematic cross-sectional view of a flash cell structure of a stack gate of the present invention, wherein FIG. 2A shows a cross-sectional view of a first type of miniaturizable stack gate flash cell structure; Section B reveals a cross-sectional view of the flash cell structure of a second type of miniaturizable stack gate. FIG. 3A to FIG. 3I show the manufacturing of a flash cell structure of a miniaturizable dual-stack stacked gate of the present invention and a non-contact non-or type flash memory array with an auto-aligned integrated floating gate structure. The process steps of a shallow groove isolation (ST I) structure and its sectional view. FIG. 4A to FIG. 4K show the manufacturing process of the first type of miniaturizable dual-pair stack gate flash cell structure of the present invention and the first type of non-contact non-or type flash memory array. FIG. Steps and its section. FIG. 5 is a schematic top-view layout diagram of the flash memory cell structure of a first type of miniaturizable dual-stack stacked gate of the present invention and its first type of non-contact non-or type flash memory array. A sectional view of an AA 'line is shown in FIG. 4K. Figures 6A to 6E show the various cross-sectional views marked in Figure 5, where Figure 6A shows a cross-section view along a line B-B '; Figure 6B shows a cross-section line C-C' A cross-sectional view of FIG. 6C reveals a cross-sectional view along a line D-D '; FIG. 6D reveals a cross-section of a line E-E'

Page 34 200525740 Brief description of the drawings Sectional view; and Fig. 6E reveals a sectional view along an F-F 'line. FIG. 7A to FIG. 7K show the fabrication of a second type of miniaturizable dual-pair stack gate flash cell structure and the continuation of the second type of contactless non-or type flash memory array of FIG. Process steps and sectional views. Representative drawing number description: 300 semiconductor substrate 301 buried ion implanted layer 301a / 3 01b / 301c formed buried ion implanted layer 3 0 2 penetrating dielectric layer 302a / 302b302c forming penetrating dielectric layer 303 second conductive layer 303a / 303b forming the second conductive layer 303c main floating gate layer 304 covering the dielectric layer 3 04a forming covering the dielectric layer 30 5a planarization field oxide layer 3 0 5b etch back the first protruding field oxide layer 305c etch back the second The protruding field oxide layer 305d etches back the third protruding field oxide layer 306a, the planarized conductive layer 306b, the etched back conductive layer 306c / 306d, the etched back conductive layer 306e, and the extended floating gate layer 3 0 7a. Inter-gate dielectric layer 3 0 8a / 3 0 8b forming inter-gate dielectric layer 30 9 second conductive layer 3 0 9a forming second conductive layer 3 0 9b control gate conductive layer 310 mask dielectric layer 310a forming mask dielectric Electrical layer 3 1 1 a Deeper diffusion region 3 1 1 b Common source / drain diffusion region

200525740 Brief description of the diagram 3 1 1 c Highly doped source / drain diffusion region 313a Planar third conductive layer 314b Cover common source conductive layer 3 1 5a Planar oxide layer 317a Third side wall dielectric pad layer 319a Planar common drain conductive layer 3 2 0 metal layer 312a first side wall dielectric pad 3 1 3 b common source conductive layer 314b / 313b common source conductive pipeline 316a second side wall dielectric pad 3 1 8 a Highly doped drain / source diffusion region 31 9b common drain conductive island 3 2 0 a metal bit line

Page 36

Claims (1)

200525740 VI. Scope of patent application 1. A miniaturizable dual-stack gate flash cell structure including at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes at least an active area (AA) formed in Between two parallel shallow groove isolation regions (STI); a virtual gate region (VGR) is formed between two common source regions (CSR) and is placed on the semiconductor substrate, wherein the virtual gate region (VGR) At least a pair of miniaturizable stack gate regions (SGR) and a miniaturizable common drain region (SCDR) are formed between the pair of miniaturizable stack gate regions (SGR); each of the two common source regions A penetrating dielectric layer including at least one first side wall dielectric cushion layer formed on each side wall of the virtual gate region (VGR) and placed within the active region (AA) and Above a portion of a flat surface composed of two etched-back second field oxide layers within the two parallel shallow trench isolation regions (STI), a highly doped source of a second conductivity type Diffusion area through the virtual gate area (VGR) and the first side wall dielectric pad As an ion implantation mask, a surface portion of the semiconductor substrate doped with dopants in the active area (AA) and a common source conductive line are formed on the first side wall dielectric cushion layer. Outside and placed by the highly doped source diffusion region inside the active region (AA) and two etched back third field oxide layers inside the two parallel shallow groove isolation regions (STI) A flat bed and a planarized oxide layer are formed outside the first side wall dielectric cushion layer and placed on the common source conductive pipeline; the pair of micronizable stack gate regions (SGR Each of the above) includes at least a second side wall dielectric cushion layer, a control gate conductive layer, an inter-gate dielectric layer, and an integrated floating gate layer, wherein the integrated floating gate layer Page 37 200525740 VI. Application scope Zha Guang i — ί — A main floating gate layer is formed on the crossing 11 in the active area (aa) and two extended floating gate layers are formed on the main floating gate Layer above the wall of the layer and placed within the two parallel shallow groove isolation regions (sTI) above the side portion of the oxide layer of the oblique first protruding field; ) Includes at least a pair of third side wall dielectrics on top of the true ditan surface on the side walls of the pair of miniaturizable stack gate areas (SGR), one of the second conductivity type A highly doped diffusive layer is implanted with dopants in the semiconductor substrate between the pair of thirds, and a conductive conductive island is formed between the pair of third side wall dielectric pads. And placed on the high-efficiency miscellaneous diffusion region; a double diffusion structure is formed on each of the two common source regions or a surface portion of the semiconductor substrate within the shrinkable > common region Moreover, a south-exchanged heterodyne or a drain diffusion region is formed in the double-diffusion structure, wherein the double-diffusion structure includes at least the A common source or common drain diffusion of the second conductivity type is formed implicitly in a deeper diffusion region of the first conductive chirp; and a buried ion implantation layer is formed on the double diffusion structure and the highly doped wave ring. Under the permeable dielectric layer between the source diffusion regions, a double diffusion channel of the first conductive frame is formed between the buried ion implantation layer and the plutonium between the common source or submerged diffusion region. A semiconductor surface part of the deep diffusion region 2 · The miniaturizable dual-pair stack gate flash cell structure described in / of the patent application scope 1 'One of the metal bit lines together with the common drain island is borrowed Page 38 200525740 6. Scope of patent application A mask photoresist step is aligned on the active area to form and etch at the same time. 3. The flash cell structure of the miniaturizable dual-pair stack gate as described in item 1 of the scope of the patent application, wherein the pair of miniaturizable stack gate regions is formed by the two common source regions. The pair of second side wall dielectric pads above the inner side wall of the first side wall dielectric pad is defined. 4. The miniaturizable dual-stack stack gate flash cell structure described in item 1 of the scope of the patent application, wherein each of the two extended floating gate layers includes at least one extension having a beveled side wall structure A conductive layer or a layer of conductive side walls. 5. The miniaturizable dual-stack stacked gate flash cell structure described in item 1 of the patent application scope, wherein the dual diffusion channel is formed in the common source diffusion region and connected to the highly doped drain diffusion region. The buried layer is implanted between ion implantation layers. 6. The flashable cell structure of the miniaturizable dual-stack stack gate as described in item 1 of the scope of the patent application, wherein the dual diffusion channel is formed in the common-drain diffusion region and the diffusion region connected to the highly doped source diffusion region. The buried layer is implanted between ion implantation layers. 7. The flash cell structure of the miniaturizable paired stack gate described in item 1 of the scope of the patent application, wherein the double diffusion structure is first formed by an auto-aligned ion implantation technology and an impurity drive-in technology A deeper diffusion zone Page 39 200525740 VI. Scope of patent application A common source or drain region is within each of the two common source regions or the scalable common source region. 8. A miniaturizable dual-stack gate flash cell structure, including at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes at least one active area (AA) formed in two parallel shallow recesses Between trench isolation regions (STI); a virtual gate region (VGR) is formed between two common source regions (CSR) and is placed on the semiconductor substrate, wherein the virtual gate region (VGR) includes at least one pair of The miniaturized stacked gate area (SGR) is defined by a pair of second side wall dielectric pads formed on the side walls of the two common source areas and a minimizable common drain area (SCDR) Formed between the pair of miniaturizable stack gate regions (SGR), each of the two common source regions including at least one first side wall dielectric pad formed in each of the virtual gate regions (VGR) Two etched back second field oxidations above the side wall and placed within the active region (AA) by a penetrating dielectric layer and within the two parallel shallow groove isolation regions (ST I) A part of a flat surface composed of an object layer, a highly doped source of a second conductivity type expands The scattered region uses the virtual gate region (VGR) and the first side wall dielectric cushion layer as an ion implantation mask to implant one of the semiconductor substrates doped in the active region (AA). A surface portion, a common source conductive pipeline formed outside the first side wall dielectric pad and placed in the active region (AA), the highly doped source diffusion region and the two parallel shallow recesses One of two etched back third field oxide layers within the trench isolation region (STI) Page 40 200525740 6. The scope of the patent application is on a flat bed, and a planarized oxide layer is formed outside the first side wall dielectric cushion layer and placed on the common source conductive pipeline; the pair can be scaled down Each of the stacked gate areas (SGR) from top to bottom includes at least one of the pair of second side wall dielectric pads, a control gate conductive layer, an inter-gate dielectric layer, and an integrated floating The gate layer has a main floating gate layer formed on the penetrating dielectric layer within the active area (AA) and two extended floating gate layers formed on side walls of the main floating gate layer and placed on Above the side portions of the two parallel shallow trench isolation regions (STI) that etch back the first protruding field oxide layer, wherein each of the two extended floating gate layers includes at least one slope An extended conductive layer or a conductive side wall cushion layer of the corner side wall structure; the miniaturizable common drain region (SCDR) includes at least a pair of third side wall dielectric cushion layers formed on the pair of miniaturizable stacks The side wall of the stack gate area is placed on the flat surface, the second guide A highly doped drain diffusion region of a type by implanting a dopant in a surface portion of the semiconductor substrate within the active region (AA) between the pair of third side wall dielectric pads, and A common-drain conductive island is formed between the pair of third side wall dielectric pads and is placed over the highly doped non-diffused region; a double-diffusion structure is formed in each of the two common source regions or the A surface portion of the semiconductor substrate within the common-drain region and having a highly doped source or drain-diffusion region is formed in the double-diffusion structure, wherein the double-diffusion structure includes at least the second conductive type A common source or common drain region is formed in a deeper diffusion region of the first conductivity type; a buried ion implantation layer is formed in the double diffusion structure and the high doping Page 41 200525740 6. The scope of the patent application is below the penetrating dielectric layer between the drain or source diffusion region, wherein a double diffusion channel of the first conductivity type is formed in the connection with the highly doped drain diffusion region. A semiconductor between the buried ion implantation layer and the deep diffusion region between the buried ion implantation layer and the common doped source diffusion region or the highly doped source diffusion region The surface portion; and a metal bit line together with a common-drain conductive island are aligned and etched simultaneously on the active area (AA) through a mask photoresist step. 9. The miniaturizable dual-stack stacked gate flash cell structure according to item 8 of the patent application scope, wherein the common source / drain diffusion region includes at least one moderately doped diffusion region or one highly doped diffusion region The deeper diffusion region includes at least one moderately doped diffusion region. 10. The flashable cell structure of the miniaturizable dual-stack stack gate as described in item 8 of the scope of the patent application, wherein the buried ion implantation layer includes at least one lightly doped diffusion region or one moderately doped diffusion region. Area. 1 1. The miniaturizable dual-pair stack gate flash cell structure described in item 8 of the scope of patent application, wherein the common source conductive pipeline includes at least one highly doped polycrystalline silicon layer and one highly doped polycrystalline silicon layer The silicon layer is covered with a tungsten silicide (WS i 2), or a crane (W) layer, or an obstructed metal layer. 12. The miniaturizable dual-pair stack gate flash cell structure as described in item 8 of the scope of patent application, wherein the common-drawing conductive island includes at least one highly doped complex crystal Page 42 200525740 6. Scope of patent application Silicon island, a highly doped compound silicon island is covered or silicided with a high temperature resistant metal silicide layer, or a tungsten (w) island is lined with a barrier metal layer. 1 3. The flashable cell structure of the miniaturizable dual-stack stack gate as described in item 8 of the scope of the patent application, wherein the metal bit line includes at least one tungsten (W), aluminum (A1), or copper (Cu ) Layer is formed on a barrier metal layer. 1 4. A non-contact non-or type flash memory array, comprising at least: a semiconductor substrate of a first conductivity type, wherein a plurality of parallel shallow groove isolation regions (STI) and a plurality of active regions (AA) are alternately grounded. Formed on the semiconductor substrate; a plurality of virtual gate regions (VGR) are alternately formed on the semiconductor substrate and perpendicular to the plurality of active regions (AA), wherein each of the plurality of virtual gate regions (VGR) Formed between two common source regions including at least a pair of miniaturizable stack gate regions (SGR) and a miniaturizable common drain region (SCDR) formed between the pair of miniaturizable stack gate regions; the two Each of the common source regions includes at least a pair of first side wall dielectric pads formed on the side walls adjacent to the virtual gate region (VGR) and placed between each of the plurality of active regions (AA). A portion of a flat surface alternately formed by a penetrating dielectric layer and an etchback second protruding field oxide layer within each of the plurality of parallel shallow groove isolation regions (STIs) A plurality of highly doped source diffusion regions of a second conductivity type Dopant in the first side wall of the plurality of active regions between the dielectric underlayer (A A) of the inner surface portion of the semiconductor substrate, a common source line is formed on the conductive Page 43 200525740 VI. Scope of patent application: An etch-back third protrusion field oxidation between the first side wall dielectric cushion layer and placed within each of the plurality of parallel shallow groove isolation regions (STI) An object layer and a flat bed of an alternately composed of the plurality of highly doped source diffusion regions within each of the plurality of active regions (AA), and a planarized oxide layer are formed on the pair of first One side wall dielectric cushion layer is placed on the common source conductive pipeline; each of the pair of miniaturizable stack gate areas (SGR) includes at least one second side wall dielectric from top to bottom The plutonium layer, a control gate conductive layer, an inter-gate dielectric layer, and a plurality of integrated floating gate layers, wherein each of the plurality of integrated floating gate layers includes at least one main floating gate layer formed in the plurality of active regions Above each of (AA) the penetrating dielectric layer and two extended floating gate layers are formed on the side walls of the main floating gate layer and placed adjacent to the parallel shallow groove isolation region (STI) Two of them etch back a side portion of the first protruding field oxide layer; The micronized common drain region includes at least a pair of third side wall dielectric pads formed on the side walls of the pair of miniaturizable stack gate regions and placed on the flat surface. The second conductive type A plurality of highly doped drain diffusion regions are formed by implanting dopants in the surface area of the semiconductor substrate within the plurality of active regions (AA) between the pair of third side wall dielectric pads, and a plurality of A drain conductive island is formed between the pair of third side wall dielectric pads and is placed on the plurality of highly doped drain diffusion regions; a plurality of double diffusion structures are implanted with dopants in the plurality of active regions (AA ), The surface portion of the semiconductor substrate is formed within each of the two common source regions or within the micronizable common drain region; and Page 44r 200525740 6. Scope of patent application The second buried conductive ion implantation layer is formed between the multiple double diffusion structure and the penetrating dielectric layer between the plurality of highly doped drain or source diffusion regions. The surface portion of the semiconductor substrate of the plurality of active regions (AA) below, wherein a double diffusion channel of the first conductivity type is formed in each of the plurality of buried ion implantation layers and the common source or common A semiconductor surface portion of a deeper diffusion region of the first conductivity type between the drain diffusion regions. 1 5. The non-contact non-or type flash memory array as described in item 14 of the scope of the patent application, wherein the plurality of metal bit lines together with the plurality of common sinking conductive islands within the scaleable common sinking region are borrowed. A mask photoresist step is aligned on the plurality of active areas (AA) to simultaneously form and etch. Recall that there are flashing fast-packing packages or less non-exhaustive storyboards floating items 4 1 drifting and enlarging Fan Fanli and the two specialties, please apply for them, column 6 1 array of side walls with side guides 1 or layer guides extending sideways with 1 side slopes. The type of memory expansion and expansion of the source and flash is fast. The type is extended in the NOR position. The expanded term is 4 1 / the source range of the common norm. 7 1 array of cloth. The sub-connected * -ec layers are buried one by one in this area and the number of spurs in the diffused area is increased by the number of spurs in the area. Scattered-It expands the memory of the flash, and the type is described in the following paragraphs. The expanded term is 4 1 miscellaneous mixed with a high norm, and the compound should be applied. Column 8 1 array, page 45, 200525740 VI. The area within the patent application area is formed in the deeper diffusion area and each of the plurality of buried ion implantation layers is related to the plurality of highly doped source diffusion areas. Every connection. 19. The non-contact non-or type flash memory array as described in item 14 of the scope of patent application, wherein the common source / drain diffusion region includes at least one moderately doped diffusion region or one highly doped diffusion region and The deeper diffusion region includes at least one moderately doped diffusion region. 20. The non-contact non-or-type flash memory array as described in item 14 of the scope of patent application, wherein each of the plurality of buried ion implantation layers includes at least one moderately doped diffusion region or one lightly doped region. Miscellaneous diffusion area. Page 46