TW200524490A - Method for fabricating electrically conductive via of build-up type packaging substrate by laser drilling - Google Patents

Abstract

A method for fabricating electrically conductive via of build-up type packaging substrate is proposed, which includes: providing an inner substrate having at least an inner circuit layer and a laminated layer with a conductive metal layer formed on the surface of the inner substrate; oxidizing the conductive metal layer by Brown Oxidation to form a rough oxidized layer with laser reflection smaller than thereon. Laser ablating the rough oxidized layer and the laminated layer to form a plurality of blind vias through the laminated layer, and then forming another build-up circuit layer onto the circuit layer including above vias. Adding the rough laminated layer can reduce laser reflection of surface of metal layer, to directly ablate the conductive metal layer by CO2 laser. Therefore, the conductive metal layer is unnecessary to be patterned prior to laser drilling, so as to simplify processes of conductive vias.

Description

200524490 V. Description of the invention (1) [Technical field to which the invention belongs]: The present invention relates to a method for manufacturing a conductive blind hole of a circuit board, and particularly to a ball grid array (BGA) package substrate. A manufacturing method for forming a conductive blind hole (E 1 ectr 1 ca 1 1 y Conductive Via) by a laser drilling process. [Previous technology]: P is living in the electronics industry, and electronic products have gradually entered the trend of multi-functional and high-speed research and development. In order to meet the packaging requirements of highly integrated and miniaturized semiconductor packages, the number of packaging circuit board layers is gradually increasing to form a multi-layer (Multl — layer B0ard) structure in which insulating layers and conductive layers are stacked alternately, and this multilayer The upper and lower circuit layers of the board structure can be connected to each other through a plurality of conductive blind vias (Electrica Hy conductive Vias) provided in each insulation layer, thereby increasing the wiring density of the circuit. However, a conductive blind via (g ^ ctrically Conducts Ve Via) is provided between the layers of the multilayer board. The blind via (B1 lnd Via) must penetrate the upper conductive layer and the insulating layer of different materials to expose the lower circuit layer; and it is in line with high-density wiring ^ Fine pitch (Fme Pltch) and electrical board ruler; the trend of two-type packaging _, the hole diameter of the blind hole has been reduced to 100 micrometers, in order to use the energy ... focused laser light as a drilling tool. In the following, FIGS. 3A to 3D are detailed descriptions of the manufacturing process of Wen Tian conductive blind vias for drilling packaged circuit boards by the Co2 Laser method. "In the layer circuit board, as shown in Figure 3A, first prepare an inner layer circuit topology. 々 久 ^ 0 Γ Τππργ

Circuits Board), the inner surface of the inner circuit board 30 and the surface of the board are formed separately.

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17556 全懋 .ptd Page 7 200524490 V. Description of the invention (2) There is an inner circuit layer 3b and a compression layer 3 2 is formed on the inner circuit layer 31. The 'compression layer 3 2 includes an insulating layer 3 2 0 and a copper foil layer 321, and the thickness of the 'copper foil layer 321 is almost the same as the thickness of the circuit layer ^ 31 on the surface of the inner circuit board 30. 3 As shown in Figure 3B, a surface Unifonn Etching Process (SUEP) is then performed on the copper box layer 3 2 1 on the surface of the bonding layer 3 2 to micro-etch copper pigs to improve copper. The adhesion between the falling layer 321 and the bonding layer thereon is maintained, and the thickness of the copper layer 3 2 1 is maintained uniform. As shown in Figure 3C ', then cover a surface such as a dry film (dry F i 1 m >-reference resistance layer 3 3 to the copper fg layer 3 2 1 of the laminated layer 3 2 and as shown in Figure 3 D -Show, perform processes such as exposure, development, etc., to determine the formation position of each blind hole by the opening 3 3 0 of the photoresist layer 3 3 = 0 as shown in Figure 3E A physical or chemical #engraving technique is used to remove the copper foil layer 3 2 1 exposed on the photoresist layer 3 3 opening 3 3 0, so that the copper foil 3 2 1 is etched, and the copper foil layer 3 2 1 is opened. The insulating layer j 2 0 under the copper foil layer 3 2 f can be exposed, as shown in Fig. 3 F. As shown in Fig. 3 G, 'After that, the photoresist layer (not shown) is removed.'- '乂 不 丨 j Use a weaker penetrating r · dioxide 5 anti-laser surname to remove the exposed layer 3 2 丨 卩, the insulating layer 3 2 0, and 馆 form a continuous penetration of the copper foil Layer 3 2 1 and 纟 邑 缘 # Layer 3 2 0 of the blind hole 3 4 (B 1 ind V ia) 'makes part of the inner circuit layer 3 1 buried under the insulating layer 3 2 q exposed in the blind hole 3 4 As shown in Figure 3, finally, electroless plating 3 & lt blind bore; off layer and copper seed layer 321 formed on the surface 36 (Seed Layer), and forming

17556 全 想 .ptd Page 8 200524490 V. Invention description (3) A patterned plating resist layer (not shown in the figure) is applied to the seed layer 3 6 1 and then the plating layer is applied to the seed layer 3 6 A metal layer with sufficient thickness is plated, and then the plating resist layer (not shown) and the seed layer 36 overlying it are removed to obtain a patterned conductive circuit layer 38, and a conductive blind hole (E 1 e C trica 11 y Com iu C: Production of tive Vi < a). However, when the conductive blind hole (E 1 e 2 tri 3 a 11, y 20di JC tive Via) of the build-up circuit board is made by the above method. Due to the copper: Ατλτ berth surface, the carbon dioxide laser with weak penetration caused by laser light #% > Method to melt 1 insect copper foil, you must first perform a patterning step to remove some of the copper foil to make the insulation The carbon dioxide field can only be used for melting after the exposed layer is exposed. The insulation layer 5 is too complicated and the photoresist pattern The alignment error generated during the case (P a 11 er η) can easily lead to the deviation of the drilling position and damage the line, which will further reduce the process yield of the build-up circuit board. 0 [Inventive Content] ·· In view of the above-mentioned habits Knowing the disadvantages of the technology, the main thing of the present invention is to provide a method for improving the penetrating power of laser light to the conductive metal layer so that the surface of the circuit board can be opened with blind drilling (V lal pain) by laser drilling technology (I; er drilling ing). It is sometimes necessary to dispense with a patterning process to remove a part of the conductive metal layer, thereby reducing the complexity of the circuit board manufacturing process. A method for manufacturing a conductive blind hole of an increased layer circuit board. Another aspect of the present invention is to provide a method for improving the laser light pair. The penetrating force of the conductive metal layer causes the circuit board surface to be opened with laser drilling technology and blind holes. Patterning must be implemented. This reduces the problem of hole displacement caused by misalignment when the patterned layers overlap. Blind hole manufacturing method for layered circuit board

] 7556 全 想 .ptd Page 9 200524490 V. Description of the invention (4) The manufacturing method of the conductive blind hole (E 1 ectrica 11 y Coon (iu: tive Vi a)) of the layered circuit board of the present invention includes the following steps: An inner layer circuit board with an inner circuit layer is prepared first. The inner layer of the circuit board is formed with a pressure-bonding layer, and the pressure-bonding layer includes at least a conductive metal layer y. The conductive metal layer is subjected to, for example, a Bn own process. 1 Ox i da ti on) oxidation treatment> to form a rough oxide layer on the metal conducting layer for laser fusion ik the rough oxide layer and the laminated layer 1 to form a through layer and pass through the laminated layer A plurality of blinds of the conductive circuit layer buried under the bonding layer and forming a patterned conductive circuit layer on each blind hole and the conductive metal layer to form a plurality of electrical connections The conductive blind holes between the layers of the build-up circuit board are different from those in traditional field drilling technology because the carbon oxide laser has a penetrating power of less than 5 and causes the conductive metal layer to be patterned before drilling. The invention abandoned the patterning process 5 and changed to oxidation to form a rough oxide layer 7 on the conductive metal layer (such as a copper layer) to make the surface color of the metal darker after the standardization process J, resulting in the reflectivity of the field light — low> Carbon dioxide laser light with weaker penetrability due to increased light absorption can also be directly eroded-the conductive metal layer does not need to be pre-arranged in the name of Takima • Patterning can simplify the process and reduce costs 0 [Implementation] : The following is a description of specific embodiments of the present invention. Those skilled in the art can use this SHEET reveals the content of the light and easy to understand the present invention and the advantages which he efficacy of the present invention also square by means of which he may be different

17556 懋 .ptd Page 10 200524490

200524490 V. Description of the invention (6) The copper percentage (RCC) is explained. As shown in FIG. 1C, a surface Uniform Etching Process (SUEP-) is performed on the conductive metal layer 121 to reduce the thickness of the conductive metal layer; and the conductive metal layer 1 2 1 After the surface is slightly etched, it has better bonding with the bonding layer thereon, and the flatness of the conductive metal layer 1 2 1 is more uniform. As shown in FIG. 1D, then, while the conductive metal layer 1 2 1 is micro-etched, a browning process (B r0w η〇X idati〇η) or a blackening process (B 1 ack) is performed. Ox i da ti on) and other metal oxidation processes, a rough surface oxide layer 122 having a laser light reflectivity lower than that of the conductive metal-layer 121 is formed on the surface of the conductive metal layer 1 2 1. As shown in FIG. 1 E As shown, further, the semi-finished circuit board with the rough oxide layer 1 2 2 formed is moved into a positioning machine 13 to perform rough positioning, so that the outer edge of the pressing layer 1 2 provided with the alignment pad 1 10 is immediately adjacent A positioning pin 130 (Pin) is provided on the positioning machine 13. As shown in FIG. 1F, a laser excavation target technique is performed to remove the surface of the positioning pad J 1 0. Compression layer 12 whose removal_surface_ < product is at least larger than the alignment error caused by coarse positioning (generally about 100 microns), so that it is hidden under the insulation layer 12 The target point (here the target point refers to the alignment. Pad_1 0) is exposed. Then, scan with a CCD automatic scanner (not shown) and search for the correct position of the alignment pad 1 1 0, which is complete. Positioning: As shown in Figure 1G, the opening distance is calculated based on the target position detected by the CCD automatic scanner (not shown), and the predetermined formation position of each blind hole is defined; then a carbon dioxide laser is used. 1 5 to drill a plurality of connected

17556 全懋 .ptd Page 12 200524490 V. Description of the invention (7) Blind hole 14 of layer 11 of circuit layer. As shown in the first figure, after that, Mengbu and Guangxi, Bing / Yi Xi Road privately removed the rough oxide layer on the surface of the road board (not shown), so that the conductive metal layer m was exposed again. As in the first I, the next step is to use the electroless mining technology to deposit a seed layer i6 (Seed Layer) on each of the blind holes i 4 and the conductive metal layer 121. The seed layer 16 is mainly used as a follow-up process. The current conduction path required for the plating circuit layer. The type can be composed of metal, alloy or deposited several metal layers. Its material can be selected from one of the group consisting of copper, tin, nickel, chromium, titanium and copper-chromium alloy. Formed. The seed layer 16 can also be formed by physical vapor deposition (pv D), chemical vapor phase (CVD), sputtering, evaporation, arc vapor deposition (A rc V a ρ 〇r D ep 〇sit 丨 〇n), ion beam sputtering (Ion Bean Sputtering), laser ablation deposition (Laser Ab 1 ati ο n D e ρo si 11 οn) or plasma-assisted chemical vapor deposition, etc. Method formation. Then, the patterned circuit layer-adding process is performed. The patterned conductive circuit layer of the build-up circuit board of the present invention is preferably the addition method (A ddi li i ν e) shown in Figures 1 j to 1 L, and the figures 1 J 'to 1 Μ', respectively. The subtraction method Su btracti ν e) shown is obtained. Therefore, the following process steps will be described separately with the first J to 1 L diagrams and the first J 'to iM' diagrams. As shown in FIG. 1J, the seed layer 16 is covered with a patterned plating resist layer 17. The plating resist layer 17 may be one of a dry film and a liquid photoresist. The known lithography process (Photol 1 thography) transfers a pre-designed thin circuit pattern onto the plating resist layer 17 so that the plating resist layer 17 has an opening 17 and a part of the seed layer 16 is exposed.

17556 Quan 懋 .ptd Page 13 200524490 V. Description of the invention (8) As shown in Figure 1K, then the plating process is performed to expose the plating resist layer 1 7 opening 1 7 0 seed layer 1 6 A conductive_electrical circuit layer 18, such as metallic copper, is deposited thereon. It is also not necessary to plate full metal in the plating resist layer 17 opening _ 170 ° As shown in Figure 1L, finally, remove the electric resistance layer 17 and the seed layer 1 covered by the plating resist layer 17 6 and the conductive metal layer 1 2 1 below, that is, the conductive blind hole of the build-up circuit board is completed, so that the inner layer circuit layer 1 1 under the blind hole can be electrically conductive by the conductive blind hole prepared by the method of the present invention. Connected to the conductive circuit layer 18 above the blind via. Another patterned circuit layer increasing technology disclosed in this embodiment is to form the conductive circuit layer 18 by using a subtractive method. As shown in FIGS. 1I and 1J ′, a plating process is performed on the surface of the seed layer 16 so that the surface of the seed layer 16 is formed with an electroplated metal layer 19 having a sufficient thickness, and the electroplated metal layer 19 is preferably a metal copper foil. As shown in FIG. 1K ′, a patterned resist layer 19 (similar to the above-mentioned plating resist layer) is formed on the electroplated metal layer 19, and the resist layer 19 0 uses exposure, shadowing And baking technology, a pre-designed fine image is transferred to the resist layer 190 as a pattern, so that a plurality of openings are formed in the resist layer 190 to expose a part of the condensed metal layer 19. As shown in the first L ′ diagram, the electroplated metal layer 19 and the seed layer 16 and the conductive metals underneath the openings of the resist layers 1 90 are removed by the etching technique (E tching) #. Layer 121 so that the pressure-resistant layer 12 covered by the unobstructed layer 19 0 has its insulating layer 12 exposed. As shown in Fig. 1M ', finally, the resist layer 190 is removed to form a conductive layer.

17556 Quan 懋 .ptd Page 14 200524490 V. Description of the Invention (9) The electric circuit layer 18 completes the manufacturing process of the conductive blind hole of the present invention. Compared with the traditional laser drilling technology, due to the insufficient penetrating power of carbon dioxide laser, various problems caused by the patterning of the conductive metal layer before drilling are required. The present invention abandons the patterning process and uses an oxidation method instead. A rough oxide layer is formed on the conductive metal layer (for example, a copper layer) to make the surface color of the metal darker after the browning process, resulting in a decrease in laser light reflectivity and an increase in light absorption, resulting in a weak penetrating carbon dioxide. Laser light can also directly melt the conductive metal layer without patterning before the laser light, so it can simplify the process and reduce costs. Second Embodiment: The 2A to 2J 'diagrams show another embodiment of the method for manufacturing a conductive blind hole of the present invention. This embodiment is substantially the same as the previous embodiment, except that the blind hole is UV laser. Instead of the carbon dioxide laser, it is only described in this embodiment that is different from the previous embodiment, and it is shown in Figures 2A to 2J '. As shown in FIG. 2A, an inner circuit board 20 (Inner Circuits Bo ajd) is first prepared. At least one inner circuit layer 21 is formed on the upper surface and / or the lower surface of the inner circuit board 20. (Inner Circuit Layer). In addition, the surface of a circuit board 20 on the inner layer includes at least a pair of bit 210. As shown in FIG. 2B, a build-up process is then performed on the inner circuit layer 21, and a technique such as lamination or coating is used to form a build-up process on the inner circuit layer 21. Compression layer 22 composed of an electrically conductive metal layer 2 2 1 and an insulating layer 22 0. The pressure-bonding layer 22 having the conductive metal layer 221 may be, for example, a glass fiber (G 1 a s s F i b e r), a polyester

17556 Quan®.Ptd Page 15 200524490 V. Description of the invention (10) (Phenolic Polyester) or a copper layer deposited on the epoxy resin layer, or made with Resin Coated Copper (RCC), but it can also be made. The insulating layer 2 2 0 is first laminated directly on the inner circuit layer 21, and then, a conductive metal layer 2 2 1 such as copper is laminated on the § 19 and the lamella edge layer 2 2 0. However, in order to facilitate the attachment of subsequent plating lines, this embodiment is described by using adhesive-backed copper foil (RCC). (Such as the first surface micro surname), so that φ slightly etched the overlying metal layer as the first stage 2 3 performs next to the fixed laser excavation 2 2, the pressure error (one point (here the machine (not shown in Figure 2C)) Shown, and then, performing a step on the conductive metal layer 2 2 1

(Surface Uniform Etching Process, SUEP thinner conductive metal layer; In addition, the conductive metal layer 221 has a better bonding property with the bonding layer on the surface, and the flatness of the conductive 221 is more uniform. 2 No, then , The semi-finished circuit board product is moved into a rough position of a positioning machine, so that a compression layer 2 2 2 of the alignment pad 2 丨 is provided on the outer edge of the clamping table 2 3 fixed pin 2 3 〇 (pin) (Recommended target technology) to remove the area of the compressed shoreline layer 22 covering the surface of the alignment pad 2 10 is at least larger than the alignment position (approximately J 0 0 μm produced by coarse positioning) so that The target point hidden under the insulating layer 2 2 〇 means that the alignment pad 2 1 is exposed, and then scanned by the CCD automatically _ scan and search for the correct position of the alignment pad 2 丨 0, that is, Wantian as the 2E As shown in the figure, the opening distance is calculated based on the position of the CCD automatic scanner (not shown in the figure), and the position of the formation layer is determined. Then, a carbon dioxide laser 25 is used to drill a plurality of blind lines connecting the layers 21 Hole 2 4.

200524490 V. Description of the invention (11) As shown in FIG. 2F, a seed layer 26 (Seed Layer) is deposited on the surface of each of the blind holes 24 and the conductive metal layer 221 by electroless plating technology. Layer 2 6 is mainly used as the current conduction path required for subsequent plating circuit layers. The type can be composed of metal, alloy, or several metal layers deposited. Its material can be selected from copper, tin, nickel, chromium, titanium and copper-chromium alloy. Formed by one of the groups. The seed layer 26 can also be formed by physical vapor deposition (PVD), chemical vapor deposition (C V D), sputtering (S p u 11 e r i n g), evaporation (evaporation), electricity? Melons are formed by Arc Vapor Deposition, Ion Bean Sputtering, Laser Ablation Deposition, or plasma-assisted chemical vapor deposition. Then, the patterned circuit layer-adding process is performed. The patterned layered circuit layer of the layered circuit board of the present invention is preferably the additive method shown in Figures 2G to 2I and the subtractive method shown in Figures 2G 'to 2J'. (Subtractive), therefore, the following process steps will be described separately with Figures 2G to 21 and 2G 'to 2J'. As shown in Fig. 2G, "the seed layer 26 is covered with a patterned plating resist layer 27, and the _plating resist layer 27 can be both a dry film and a liquid photoresist". The known-lithography process (Photolithography) transfers a pre-designed thin circuit pattern onto the plating resist layer 27 so that the plating resist layer 27 has an opening 2 7 0 and a part of the seed layer 26 is exposed. As shown in FIG. 2H, a plating process is performed to expose the plating resist layer 2 7 openings 2 7 0 to the seed layer 26. A conductive circuit layer 28 such as copper is deposited on the seed layer 26. It is also not necessary to plate full metal in the opening of the plating resist layer 2 7

17556 全懋 .ptd Page 17 200524490 V. Description of the Invention (12) 2 7 0 ° As shown in Figure 21, finally, remove the plating resist (as shown in Figure 27 above) and ~ the crystals covered by the plating resist The seed layer 26 and the conductive metal layer 2 2 1-underneath, that is, the conductive blind hole of the build-up circuit board is completed, so that the inner circuit layer 21 under the blind hole can be made conductive by the method of the present invention. The blind hole is electrically connected to the conductive circuit layer 28 above the blind hole. Another patterned circuit layer increasing technology disclosed in this embodiment uses a subtractive method to form a conductive circuit layer. As shown in FIG. 2F and FIG. 2G ', an electrical process is performed on the surface of the seed layer 26, so that the surface of the seed layer 26 has an electroplated gold-metal layer 29 with a sufficient thickness. The electroplated metal layer 29 is preferably a metallic copper layer. A second resist layer 290 is disposed on the electroplated metal layer 29. As shown in FIG. 2 (a), the electroplated metal layer 29 above the seed layer 26 is covered with a patterned resist layer 290 (similar to the above-mentioned plating resist layer), and the resist layer 2 9 0 It is to transfer a pre-designed thin circuit pattern onto the resist layer 2 90 using conventional exposure, development and baking techniques, so that a plurality of openings are formed in the resist layer 2 90 to expose part of the electroplated metal layer 2 9. _ As shown in Figure 2 Γ, the conventional etching technique (Etching) is used to etch away the electroplated metal layer 29 and the seed layer exposed to the openings of each of the resist layers 2 9 0. 2 6 _ The conductive metal below Layer 221, so that the non-resistive layer 29 0 covers the laminated layer 22 and the insulating layer 2 2 0 is exposed. As shown in FIG. 2 J ′, finally, the resist layer 290 is removed to form a conductive circuit layer 28 to complete the manufacturing process of the conductive blind hole of the present invention. The previous disclosure steps of the present invention are not limited to the method described in the embodiments, other

17556 全懋 .ptd Page 18 200524490 V. Description of the invention (13) Equivalent substitution steps of the circuit board process, equipment or materials, such as changing the number of layers of the multilayer package circuit board, etc. are also included in the scope of the present invention. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.

17556 Quan 懋 .ptd Page 19 200524490 Brief description of the drawings [Simplified description of the drawings]: Figures 1A to 1L are the manufacturing method of the conductive blind hole of the build-up circuit board of the first embodiment of the present invention to add 1A to 1I and 1J 'to 1M' diagrams of the method for forming a patterned build-up circuit by the method, which are manufacturing methods of conductive blind holes of the build-up circuit board according to the first embodiment of the present invention Flow chart for forming patterned build-up circuit by subtractive method; FIGS. 2A to 2I are the manufacturing method of the conductive blind hole of the build-up circuit board according to the second embodiment of the present invention. 2A to 2F and 2G 'to 2J' diagrams of the flow of the layer circuit, which are formed by subtracting the conductive blind hole manufacturing method of the layer-added circuit board according to the second embodiment of the present invention. A flowchart of patterning the layer-increasing circuit; and FIGS. 3A to 3H are flowcharts of a conventional method for manufacturing blind holes. 10,20,30 Inner circuit board 11, 21, 31 妁 layer circuit layer 110,210 Alignment pad 1 2, 2 2, 3 2-Lamination layer • 0, 2 2 0, 3 2 0 Insulating layer 121, 221 Conductive metal layer 122 Rough surface oxide layer 13,23 Positioning machine 1 3 0,2 3 0 Positioning pin

17556All®.ptd Page 20 200524490

Brief description of the drawings 14,24,34 Blind L 15,25 Carbon dioxide lightning 16, 26, 36 Seed layer 17, 27 Plating resist 1 7 0, 2 7 0 Opening 18, 28, 38 Conductive circuit layer 19, 29 Electroplated metal layer 1 9 0, 2 9 0 Resistive layer 321 Copper foil layer 33 Photoresistive layer 330 Photoresistive layer opening 17556 懋 .ptd page 21

Claims (1)

200524490 VI. Scope of patent application 1. A method for manufacturing electrically conductive blind vias of a build-up circuit board includes the following steps: • Preparing an inner-layer circuit board with an inner-layer circuit layer. A pressing layer is formed on at least one surface, and the pressing layer includes at least one conductive metal layer; the conductive metal layer is oxidized to form a rough oxide layer on the conductive metal layer; Surface oxide layer and the pressing layer to form a plurality of blind holes penetrating through the pressing layer; and φ forming a patterned conductive circuit layer on each of the blind holes and the conductive metal layer to make a plurality of electrical connections to the Conductive blind holes between layers of a build-up circuit board. 2. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 1 of the scope of patent application, which includes implementing a Surface Uni form Etching Process (SUEP) process on the conductive metal layer. 3. If applying The manufacturing method of the conductive blind hole of the layered circuit board of the first item of the patent scope includes removing the rough oxygen layer before the patterned circuit is formed. 4. The method for manufacturing a conductive blind hole of a build-up circuit board according to the first aspect of the patent application, wherein the conductive metal layer is a copper foil. 5. For example, the method for manufacturing a conductive blind hole of a build-up circuit board according to item 1 of the scope of patent application, wherein the oxidation treatment is performed by a browning process (Brown Oxidation). Manufacturing method of conductive blind hole of board 17556 全懋 .ptd Page 22 200524490 6. Application for Patent Scope Method, in which the oxidation treatment is carried out by a blackening process (B 1 ack Oxidation). 7. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 1 of the application, wherein the reflectivity of the laser light to the rough oxide layer is less than the reflectivity of the laser light to the conductive metal layer. 8. The method for manufacturing a conductive blind hole of a layer-added circuit board according to item 1 of the patent application scope, wherein the laser is a carbon dioxide laser. 9. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 1 of the scope of patent application, wherein the conductive blind hole penetrates the bonding layer and is electrically connected to the inner circuit layer covering the bonding layer. 10. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 1 of the scope of patent application, wherein the patterned conductive circuit layer is made by an additive method (A d d i t i v e). 1 1. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 1 of the scope of patent application, wherein the patterned conductive circuit layer is made by a subtract method. 1 2 · —A method for manufacturing conductive blind holes (E 1 ectrica 1 1 y _ Conductive Via) of a build-up circuit board includes the following steps: preparing an inner circuit board with an inner circuit layer, and the inner layer circuit. A compression layer is formed on at least one surface of the board, and the compression layer includes at least one conductive metal layer; the laser is used to ablate the compression layer to form a plurality of blind holes penetrating the compression layer; A patterned conductive line is formed on the hole and the conductive metal layer 17556 Quan 懋 .ptd Page 23 200524490 I. Scope of patent application Road layer to form a plurality of conductive blind holes electrically connected to the layers of the build-up circuit board. 1′3. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the scope of patent application, further comprising performing a Surface Uniform Etching Process (S UEP) process on the conductive metal layer. 14. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the scope of patent application, wherein the conductive metal layer is a copper foil. 15. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the scope of patent application, wherein the laser light is less reflective to the rough oxide layer _ than the laser light is reflective to the conductive metal layer Sex. -1 6. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the scope of patent application, wherein the conductive blind hole penetrates the bonding layer, and is electrically connected to the inner layer circuit layer covering the bonding layer. Sexual connection. 1 7. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the scope of patent application, wherein the patterned conductive circuit layer is made by an additive method. 18. If you apply for the conductive blind hole manufacturing method for layer-added circuit boards in item 12 of the application, where "the patterned conductive circuit layer is made by Subtractive". The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the patent application scope, wherein the conductive metal layer is a copper foil. 20. The method for manufacturing a conductive blind hole of a build-up circuit board according to item 12 of the patent application scope, wherein the laser is a UV laser. 17556 懋 .ptd Page 24