TW200507951A - Unitary dual damascene process using imprint lithography - Google Patents

Unitary dual damascene process using imprint lithography

Info

Publication number
TW200507951A
TW200507951A TW093113020A TW93113020A TW200507951A TW 200507951 A TW200507951 A TW 200507951A TW 093113020 A TW093113020 A TW 093113020A TW 93113020 A TW93113020 A TW 93113020A TW 200507951 A TW200507951 A TW 200507951A
Authority
TW
Taiwan
Prior art keywords
resist layer
template
dual damascene
patterned resist
tiered
Prior art date
Application number
TW093113020A
Other languages
English (en)
Inventor
Douglas J Resnick
Scott D Hector
Richard D Peters
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200507951A publication Critical patent/TW200507951A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1021—Pre-forming the dual damascene structure in a resist layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW093113020A 2003-05-08 2004-05-07 Unitary dual damascene process using imprint lithography TW200507951A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/434,614 US20040224261A1 (en) 2003-05-08 2003-05-08 Unitary dual damascene process using imprint lithography

Publications (1)

Publication Number Publication Date
TW200507951A true TW200507951A (en) 2005-03-01

Family

ID=33416733

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093113020A TW200507951A (en) 2003-05-08 2004-05-07 Unitary dual damascene process using imprint lithography

Country Status (4)

Country Link
US (1) US20040224261A1 (zh)
JP (1) JP2007521645A (zh)
TW (1) TW200507951A (zh)
WO (1) WO2004102624A2 (zh)

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JP3821069B2 (ja) * 2002-08-01 2006-09-13 株式会社日立製作所 転写パターンによる構造体の形成方法
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US7323417B2 (en) * 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
TW200503167A (en) * 2003-06-20 2005-01-16 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
US20050123860A1 (en) * 2003-12-03 2005-06-09 Paul Koning Dielectric with fluorescent material
US7435074B2 (en) * 2004-03-13 2008-10-14 International Business Machines Corporation Method for fabricating dual damascence structures using photo-imprint lithography, methods for fabricating imprint lithography molds for dual damascene structures, materials for imprintable dielectrics and equipment for photo-imprint lithography used in dual damascence patterning
US7163888B2 (en) * 2004-11-22 2007-01-16 Motorola, Inc. Direct imprinting of etch barriers using step and flash imprint lithography
US7691275B2 (en) * 2005-02-28 2010-04-06 Board Of Regents, The University Of Texas System Use of step and flash imprint lithography for direct imprinting of dielectric materials for dual damascene processing
US7767129B2 (en) * 2005-05-11 2010-08-03 Micron Technology, Inc. Imprint templates for imprint lithography, and methods of patterning a plurality of substrates
US7419611B2 (en) * 2005-09-02 2008-09-02 International Business Machines Corporation Processes and materials for step and flash imprint lithography
WO2007030527A2 (en) * 2005-09-07 2007-03-15 Toppan Photomasks, Inc. Photomask for the fabrication of a dual damascene structure and method for forming the same
US7259102B2 (en) * 2005-09-30 2007-08-21 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
FR2893018B1 (fr) * 2005-11-09 2008-03-14 Commissariat Energie Atomique Procede de formation de supports presentant des motifs, tels que des masques de lithographie.
US7422981B2 (en) * 2005-12-07 2008-09-09 Canon Kabushiki Kaisha Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
JP4827513B2 (ja) * 2005-12-09 2011-11-30 キヤノン株式会社 加工方法
WO2008005087A2 (en) * 2006-06-30 2008-01-10 Advanced Micro Devices, Inc. A nano imprint technique with increased flexibility with respect to alignment and feature shaping
DE102006030267B4 (de) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
JP5329522B2 (ja) 2007-03-23 2013-10-30 アレジアンス、コーポレイション 流体収集システム
US9889239B2 (en) 2007-03-23 2018-02-13 Allegiance Corporation Fluid collection and disposal system and related methods
US8460256B2 (en) 2009-07-15 2013-06-11 Allegiance Corporation Collapsible fluid collection and disposal system and related methods
JP2009034926A (ja) * 2007-08-02 2009-02-19 Sumitomo Electric Ind Ltd 樹脂パターン形成方法
US8026170B2 (en) * 2007-09-26 2011-09-27 Sandisk Technologies Inc. Method of forming a single-layer metal conductors with multiple thicknesses
JP5349404B2 (ja) * 2010-05-28 2013-11-20 株式会社東芝 パターン形成方法
KR102449800B1 (ko) 2015-06-15 2022-09-29 매직 립, 인코포레이티드 가상 및 증강 현실 시스템들 및 방법들
JP2017017093A (ja) * 2015-06-29 2017-01-19 株式会社東芝 半導体装置の製造方法
AU2017376453B2 (en) 2016-12-14 2022-09-29 Magic Leap, Inc. Patterning of liquid crystals using soft-imprint replication of surface alignment patterns
US10606170B2 (en) 2017-09-14 2020-03-31 Canon Kabushiki Kaisha Template for imprint lithography and methods of making and using the same
CN107719851A (zh) * 2017-09-27 2018-02-23 中国科学院光电技术研究所 一种变图案防伪浮雕型防伪器件
CN110078018A (zh) * 2018-01-26 2019-08-02 苏州锐材半导体有限公司 用于微流控芯片制备的台阶模板加工方法
JP7414597B2 (ja) 2020-03-12 2024-01-16 キオクシア株式会社 配線形成方法
JP2021145076A (ja) 2020-03-13 2021-09-24 キオクシア株式会社 原版および半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387787B1 (en) * 2001-03-02 2002-05-14 Motorola, Inc. Lithographic template and method of formation and use
US20030027419A1 (en) * 2001-08-02 2003-02-06 International Business Machines Corporation Tri-tone photomask to form dual damascene structures
US6753130B1 (en) * 2001-09-18 2004-06-22 Seagate Technology Llc Resist removal from patterned recording media
US6890688B2 (en) * 2001-12-18 2005-05-10 Freescale Semiconductor, Inc. Lithographic template and method of formation and use
US6716754B2 (en) * 2002-03-12 2004-04-06 Micron Technology, Inc. Methods of forming patterns and molds for semiconductor constructions
US6730617B2 (en) * 2002-04-24 2004-05-04 Ibm Method of fabricating one or more tiers of an integrated circuit
US6852454B2 (en) * 2002-06-18 2005-02-08 Freescale Semiconductor, Inc. Multi-tiered lithographic template and method of formation and use
US7013562B2 (en) * 2003-03-31 2006-03-21 Intel Corporation Method of using micro-contact imprinted features for formation of electrical interconnects for substrates

Also Published As

Publication number Publication date
US20040224261A1 (en) 2004-11-11
JP2007521645A (ja) 2007-08-02
WO2004102624A3 (en) 2005-03-03
WO2004102624A2 (en) 2004-11-25

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