TW200426958A - Semiconductor module and method for making same - Google Patents

Semiconductor module and method for making same Download PDF

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Publication number
TW200426958A
TW200426958A TW093108590A TW93108590A TW200426958A TW 200426958 A TW200426958 A TW 200426958A TW 093108590 A TW093108590 A TW 093108590A TW 93108590 A TW93108590 A TW 93108590A TW 200426958 A TW200426958 A TW 200426958A
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Taiwan
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insulator
semiconductor
substrate
insulating substrate
base material
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TW093108590A
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Chinese (zh)
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TWI305018B (en
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Ryosuke Usui
Hideki Mizuhara
Takeshi Nakamura
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Sanyo Electric Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

This invention provides a semiconductor module to enhance the adhesion between an insulation substrate and an insulation body formed on the insulation substrate, the insulation body being an encapsulating resin or an adhesive member of the semiconductor element. A solder resist layer (408) is formed on the uppermost layer of a laminate of a plurality of layers including wiring layers of interlayer insulation film (405) and a wiring (407) of copper. Elements (410a) and (410b) are formed on a surface of the solder resist layer (408). The elements (410a) and (410b) are molded with a molding resin. The surface of the solder resist layer (408) is modified by a plasma treatment with selected specific condition, and a group of fine projections is formed, so that the surface of the solder resist layer (408) has such characteristics that, when a detected strength of an X-ray photoelectron spectrograph with a binding energy of 284.5eV is designated by x, and a binding energy of 286eV is designated by y, the value of y/x is higher than 0.4.

Description

200426958 九、發明說明： 【發明所屬之技術領域】 本發明係有關搭載半導體元件等並接合於配線基板等 之半導體模組及其製造方法。 【先前技術】 當行動電話、個人數位助理（personal digital assistant, PDA)、數位攝影機（digital video camera，DVC)、數位相機 (digital still camera，DSC)等之攜帶式電子機器加速進行高 機能化時，為了使這樣的產品在市場上可被接受，還必須 進行小型·輕量化。而為了實現這樣的需求而必須尋求高 積月豆化的系統大型積體（large scale integrati〇n，Lsi)技術。 另一方面’對這些電子機器而言，也需要有更加好用而便 利的性能，而必須對在機器上使用的LSI要求高機能化、 间性月b化°為此’伴隨著LSI晶片之高積體化之輸入/輸出 點婁:：^曰力口 ’使封骏本身之小型化的要求也增強，為了使 而求可並存’而鉍烈地要求對適合於高密度半導體零 件之基板組裝的半導體封裝技術進行開發。為了配合這樣 白勺要求，而逸夕-於 疋订稱為晶片級封裝（Chip Size Package, CSP) 之封裝=術的各種開發。 目Μ已知有球開陣列封裝（Ball Grid Array, BGA)可作 為如此的封LBGA係在封裝 用基板上上安裝半導體元 ^將其以树脂模製之後，在對向側之表面形成作為外部 接點之區域狀錄姐 、干踢球。在BGA中，因為以面狀形成組裝區 域，使封裝能卜^ ^ 較各易小型化。此外，因為在電路基板侧 6 315641 200426958 上也沒有配合狭小間距的必要’而不需要高精確度的組衰 技術，所以使用BGA的話，即使封裝成本在多少較高的情 況下，總組裝成本仍可能降低。 第1圖係表示一般之BGA的概要結構圖。BGA1〇〇具有 在玻璃環氧（Glass-Epoxy)基板106上，透過接著層1〇8搭載 LSI晶片102的構造。其中，藉由封裝樹脂11〇對][^1晶片1〇2 進行模製（molding)。而將LSI晶片1〇2以及玻璃環氧基板-106間以金屬線1〇4電性連接。在玻璃環氧基板1〇6的背， 面，銲錫球112以陣列狀排列。再透過該銲錫球〗12，將# BGA100安裝於印刷線路基板。 在專利文獻1中記載有其他CSP的例子。在該公報記載 中，並揭露搭載高頻用LSI的系統級封裝件（System比200426958 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor module mounted on a semiconductor substrate or the like and bonded to a wiring substrate or the like, and a manufacturing method thereof. [Previous technology] When mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital video cameras (DVCs), and digital still cameras (DSCs) accelerate the high-performance In order for such products to be accepted in the market, they must also be reduced in size and weight. In order to realize such a demand, it is necessary to seek a large scale integrative system (Lsi) technology. On the other hand, for these electronic devices, more convenient and convenient performance is also required, and LSIs used in the devices must be highly functional and intermittent. To this end, accompany the LSI chip. The input / output point of the high-volume integration Lou :: ^ Likou 'enhances the miniaturization of Feng Jun itself, in order to make it coexist', and bismuth strongly requires a substrate suitable for high density semiconductor parts Development of assembled semiconductor packaging technology. In order to meet such requirements, Yi Xi-Yu has developed various packages called Chip Size Package (CSP). It is known that Ball Grid Array (BGA) can be used as such a package. LBGA is a semiconductor element mounted on a packaging substrate. ^ After molding with resin, it is formed on the opposite surface as an exterior. The area of the contact record sister, dry kick. In the BGA, since the assembly area is formed in a planar shape, the package can be easily miniaturized. In addition, because there is no need to cooperate with a narrow pitch on the circuit board side 6 315641 200426958, and no high-accuracy group attenuation technology is required, using BGA, even if the packaging cost is somewhat high, the total assembly cost is still May be reduced. FIG. 1 is a schematic configuration diagram showing a general BGA. BGA100 has a structure in which an LSI chip 102 is mounted on a glass-Epoxy substrate 106 through a bonding layer 108. Among them, the [[1] wafer 102 is molded by the encapsulating resin 110. The LSI wafer 102 and the glass epoxy substrate -106 are electrically connected by a metal wire 104. On the back and front of the glass epoxy substrate 106, solder balls 112 are arranged in an array. Then, through the solder ball 12, # BGA100 is mounted on the printed circuit board. Examples of other CSPs are described in Patent Document 1. In this publication, a system-level package (System ratio) equipped with a high-frequency LSI is disclosed.

Package)。該封裝件係於基底（base)基板上形成多層線路構 造，而在該基板上首先形成高頻用LSI之半導體元件。多 層線路構造係為核心（core)*板以及附加樹脂之銅箔等之 疊層構造。 但是，由這些習知的CSP卻難以在攜帶式電子機器等 方面只現如目前希望之水準的小型化、薄型化、輕量化。 其係因為習知的CSP具有支撐元件之基板的關係。由於支 撐基板的存在，使封裝全體變厚，而使小型化、薄型化、 輕里化有其界限。此外，散熱性的改善也有一定的界限。 曰本國專利2002-94247號公報 日本國專利2002-110717號公報 【發明内容】 7 315641 200426958Package). This package is a multilayer circuit structure formed on a base substrate, and a semiconductor element for a high-frequency LSI is first formed on the substrate. The multi-layer circuit structure is a laminated structure of a core * board and copper foil with resin. However, it is difficult for these conventional CSPs to achieve miniaturization, thinness, and weight reduction in portable electronic devices, etc., as currently desired. This is because the conventional CSP has the relationship of supporting the substrate of the element. The existence of the supporting substrate makes the entire package thicker, and there are limits to miniaturization, thinning, and lightness. In addition, there is a certain limit to the improvement of heat dissipation. Japanese Patent No. 2002-94247 Japanese Patent No. 2002-110717 [Summary of the Invention] 7 315641 200426958

a在以上所述之BGA等封裝件中，封裝件之 在、封7L件之封裝樹脂間之充分緊牙土 兄刀系山、、，口σ性十分重要，特別 半導體模組因為沒有支樓基板，因此 、斗面緊孩、結合性的要求十分嚴格。 本發明係有鑑於上述問題所開發者，其目的為，在半 ¥肢輪組等模組件中，將料基材和形成於絕緣基材上的 如半導體元件之封裝樹脂或接著材料間的緊密 本發明之半導體模組所具有的特徵為：包含設置導體 電路的絕緣基材，形成於該絕緣基材上的半導體元件，^ 及連接該絕緣基材以及該半導體元件而設立的絕緣體丨以 及在該絕緣基材之連接該絕緣體的表面上，形成微:突起 在本發明中，半導體元件係包含半導體晶片、晶片電 阻、晶片電容、晶片電導（Chip c〇n(JUct〇r)等。 該半導體模組因為在絕緣基材之連接絕緣體的表面上 形成微小突起群，使得於絕緣基材和絕緣體之界面的緊密 結合性變得良好。 此外，絕緣體可以是密封半導體元件的封裝樹脂，也 可以是設置於半導體元件和絕緣基材之間的接著材料。 此外’在絕緣基材之連接絕緣體的表面上，也可形成 複數之火山口（crater)狀凹部，而火山口狀凹部之直徑也可 在0·1 um以上、1 um以下。 3】5641 8 200426958 該半導體模組，因為除了在絕緣基材之連接絕緣體的 表面上形成微小突起群外，並形成直徑〇·! μπι以上、i μηι 以下之複數之火山口狀凹部，使絕緣基材和絕緣體之界面 的緊密結合性變得良好。 认小大起群宜含有平均直徑1 nm至20 nm的複數之突 起而且’其數虿後度宜為〇·5χ1〇3 以上，更宜為〇·8 X ίο3 μιη-2 至 2.0x ΙΟ3 μητ2。特別是，最宜為】6χ 1〇3 μιη_2 至2.〇x 103 μιη-2。藉此，可明顯改善於絕緣基材和絕緣體 之界面的緊密結合性。 有關本發明之另一半導體模組之特徵為：包含設置有 導體電路的絕緣基材，形成於該絕緣基材上的半導體元 件，=及連接該絕緣基材以及該半導體元件的絕緣體；以 及，u緣基材之連接該絕緣體的表面中，該絕緣基材係 由環氧樹脂材料構成’而於該表面之附近的乂線光電子分 光譜（spectrum)中，當將束缚能_284 5 6乂的檢測強度 X ’將束缚強度-286 eV的檢測強度當作丫的時候 值為0.4以上。 於此，束縛能-286 eV屬於結構C=〇結合的as電子。 另一方面，束缚能-284.5 eV屬於結構C—〇結合或C_N結 子’這些比值在滿足上述條件時，可明顯改善於 緣基材和絕緣體之界面的緊密結合性。還有，將y/x之 數值的上限設為例如3以下。 有關本發明之再一半導體模組之特徵為：包含設 體電路的絕緣基材，形成於該絕緣基材上的半導體元件， 315641 9 200426958 70件的絕緣體；以及該 露出時，其對純水之接 以及連接該絕緣基材以及該半導體 絕緣基材之連接該絕緣體的區域在 觸角為30度至120度。 p用’、有此接觸角的樹脂材料，可明顯地改善對 絶緣基材和絕緣體之界面的緊密結合性。 上述之半導體模組，例如，可藉由在沒有 的預定條件下進行電漿(plasma)處㈣得到。“（as)a In the above-mentioned BGA and other packages, the tightness of the package between the sealing resin and the sealing resin of 7L pieces is very important, especially because the semiconductor module has no branches. The substrate, therefore, the bucket surface is tight and the requirements for bonding are very strict. The present invention has been developed in view of the above-mentioned problems, and its purpose is to separate a base material and an encapsulating resin such as a semiconductor element or an adhesive material formed on an insulating base material in a mold assembly such as a half-limb wheel set. The semiconductor module of the present invention has the following characteristics: an insulating substrate provided with a conductor circuit, a semiconductor element formed on the insulating substrate, and an insulator established by connecting the insulating substrate and the semiconductor element, and On the surface of the insulating base material connected to the insulator, micro: protrusions are formed. In the present invention, a semiconductor element includes a semiconductor wafer, a chip resistor, a chip capacitor, and a chip conductance (Chip tron (JUctor)). Because the semiconductor module forms a small protrusion group on the surface of the insulating substrate to which the insulator is connected, the adhesion between the insulating substrate and the insulator becomes good. In addition, the insulator may be a sealing resin that seals a semiconductor element, or It is a bonding material provided between the semiconductor element and the insulating substrate. In addition, 'on the surface of the insulating substrate to which the insulator is connected, A plurality of crater-like recesses can also be formed, and the diameter of the crater-like recesses can also be greater than or equal to 0.1 um and less than 1 um. 3] 5641 8 200426958 This semiconductor module, because Outside the surface of the connected insulator, a group of micro-protrusions is formed, and a plurality of crater-shaped recesses having a diameter of 0 μm or more and i μm or less are formed, so that the tight bonding of the interface between the insulating base material and the insulator becomes good. The cluster should preferably include a plurality of protrusions with an average diameter of 1 nm to 20 nm and the number of degrees should be 0.5 × 10 ° or more, more preferably 0.8 × 3 μιη-2 to 2.0x ΙΟΟ 3 μητ2. Especially , Most preferably] 6χ 103 μιη_2 to 2.00 103 μιη-2. This can significantly improve the tight bonding at the interface between the insulating substrate and the insulator. Features of another semiconductor module related to the present invention Is: an insulating substrate provided with a conductor circuit, a semiconductor element formed on the insulating substrate, and an insulator connecting the insulating substrate and the semiconductor element; and a surface of the u-edge substrate connected to the insulator The insulating base material is made of epoxy resin. In the photoelectron spectrum of the ray line near the surface, when the binding energy is _284 5 6 乂, the detection intensity X is the binding intensity -286 eV. When the detection intensity is taken as y, the value is above 0.4. Here, the binding energy -286 eV belongs to the as electrons of the structure C = 0. On the other hand, the binding energy -284.5 eV belongs to the structure C-0 binding or C_N junction ' When these ratios satisfy the above conditions, the close bonding between the edge substrate and the insulator can be significantly improved. In addition, the upper limit of the value of y / x is set to, for example, 3 or less. Another semiconductor module related to the present invention The characteristics are: an insulating substrate including a body circuit, a semiconductor element formed on the insulating substrate, 315641 9 200426958 70 pieces of insulator; and when exposed, its connection to pure water and connection to the insulating substrate and The region of the semiconductor insulating substrate connected to the insulator has an antenna angle of 30 degrees to 120 degrees. For p ', a resin material with such a contact angle can significantly improve the tight bonding to the interface between the insulating substrate and the insulator. The above-mentioned semiconductor module can be obtained, for example, by performing plasma treatment under predetermined conditions that are not available. "(As)

有關本發明之又-半導體模組之特徵為 導體電路的的絕緣歸，形成於㈣緣基材上的半導^ :材絕緣基材和半導體元件的絕緣體；以及絕緣 官能氧環丁烧(―)化合物或環氧樹脂 化口物的先硬化性·熱硬化性樹脂。 該半導體模組的絕緣基材，因為具有含有多官 丁烷化合物或環氧樹脂化合物的光硬化性.熱硬In another aspect of the present invention, the semiconductor module is characterized by the insulation of the conductor circuit, and the semiconductor formed on the edge substrate: the insulator of the insulating substrate and the semiconductor element; ) A pre-curing and thermosetting resin of a compound or epoxy resin. The insulating substrate of this semiconductor module has a photo-hardening property containing a polybutane compound or an epoxy resin compound.

脂’而可進行型樣化(patterning)，同時，可明顯地改善J 絕緣基材和絕緣體的界面的緊密結合性。 有關本發明之又一半導體模組的特徵為··包含有基 材，形成於基材上的元件，以及連接美一 體；以及在基材之連接絕緣二Λ Γ及，絕緣 、， π丞w <連接絕緣體的表面上，形成微小突起 群。 該模組因為在基材之連接絕緣體的表面上形成微小突 起群’使得於基材和絕緣體的界面之緊密結合性變得= 315641 10 200426958 此外，在基材之連結絕緣體的表面上，也可以形成複 數的火山口狀凹部，而該微小突起群也可以含有平均直徑 1 nm至20 nm之複數個突起。 再者，本發明之半導體模組的製造方法係為製作上述 之半導體模組的方法，其特徵為··包含對設立有導體電路 的絕緣基材的表面進行電漿處理的步驟，以及在該絕緣基 材上，形成半導體元件以及連接該半導體元件之絕緣體的 步驟；以及在不對該基板施加偏壓（bias)下，用含有惰性 氣體（惰性氣體）之電漿氣體進行該電漿處理。 藉由進行如上述之電漿處理，而能安定地得到對絕緣 基材和絕緣體之界面具有卓越的緊密結合性之半導體模 組。還有，所謂「偏壓」係不包括基板本身的偏壓。' 再者，本發明之模組的製造方法係為製作上述之模組 的方法’其特徵為：包含對基材之表面進行電浆處理的步 驟以及在基材上形成疋件和連接元件之絕緣體的步驟； =在不對該基板施加偏壓下，用含有惰性氣 體進行該電漿處理。 ^ 矛絕二:：如上述之電漿處理，而能安定地得到對基材 界面具有卓越的緊密結合性之半導體模 有’戶“胃「偏壓」係不包括基板本身的偏麼。 緣4=中’在半導體元件為裸晶片(一)，而絕 在二相二晶片之封裝樹脂構成時，特別具有效果。 ι構的情況下，以薄型化而能實現輕量之封裝 315641 2同時，錄㈣絲材和料之財❹社 良問題’然而如果根據本發明，即可有效解決這樣的^不 t發明中之所料體電路，係為形成於基材内 i::導：由7_成的電路。所謂絕緣基材，係： 牙+V肢兀件以及與其連接之導體電路的絕緣性基 而所謂絕緣體係為，例如，對設立於絕緣基材上之$ 元件進行密封之封裝樹脂或 ^ γ m配置於絕緣基材和半導體元 1千之間的絕緣層或接著部材等。 6如果根據本發明’在半導體模組等模組方面，可將絕 緣基材、形成於絕緣基材上的絕緣體、以及例如半導體元 件之封裝樹脂間的緊密結合性提高。 【實施方式】 二以下將說明有關本發明之實施形態，然而在進入說明 之別，先對在實施形態中採用的ISB構造相關進行說明。Fat 'can be patterned, and at the same time, the adhesion between the J insulating substrate and the interface of the insulator can be significantly improved. Another feature of the semiconductor module of the present invention is that it includes a substrate, elements formed on the substrate, and a connection with the United States; and the connection between the substrate and the insulating layer Λ Γ and π 丞 w < A small protrusion group is formed on the surface of the connection insulator. The module forms micro-protrusions on the surface of the substrate to which the insulator is connected, so that the tight bonding at the interface between the substrate and the insulator becomes 315641 10 200426958. In addition, it can also be used on the surface of the substrate to which the insulator is connected. A plurality of crater-like recesses are formed, and the small protrusion group may also include a plurality of protrusions having an average diameter of 1 nm to 20 nm. Furthermore, the method for manufacturing a semiconductor module according to the present invention is a method for manufacturing the above-mentioned semiconductor module, and is characterized by including a step of performing a plasma treatment on a surface of an insulating substrate on which a conductive circuit is established, and A step of forming a semiconductor element and an insulator connected to the semiconductor element on an insulating substrate; and performing the plasma treatment with a plasma gas containing an inert gas (inert gas) without applying a bias to the substrate. By performing the plasma treatment as described above, a semiconductor module having excellent close bonding to the interface between the insulating substrate and the insulator can be obtained stably. The "bias" does not include the bias of the substrate itself. 'Further, the manufacturing method of the module of the present invention is a method of manufacturing the above-mentioned module', which is characterized in that it includes a step of plasma-treating the surface of the substrate and a method of forming a member and a connecting element on the substrate. Step of insulator; = The plasma treatment is performed with an inert gas without applying a bias voltage to the substrate. ^ Spear 2: The plasma processing as described above can stably obtain a semiconductor mold with excellent tight bonding to the substrate interface. Does the "stomach bias" not include the substrate bias? Edge 4 = medium 'is particularly effective when the semiconductor device is a bare wafer (1), but is formed of a two-phase two-wafer packaging resin. In the case of a thin structure, it is possible to realize a light-weight package 315641 2 with a thin profile. At the same time, it is possible to record the problems of the wire and materials. The expected body circuit is a circuit formed in the substrate i :: guide: 7_. The so-called insulating substrate is: the insulating base of the teeth + V limbs and the conductor circuit connected to it. The so-called insulating system is, for example, an encapsulating resin or ^ γ m that seals the $ element established on the insulating substrate. An insulating layer or an adhesive member disposed between an insulating base material and 1,000 semiconductor elements. 6 According to the present invention, in a module such as a semiconductor module, it is possible to improve the tight bonding between an insulating substrate, an insulator formed on an insulating substrate, and a sealing resin such as a semiconductor element. [Embodiment] The following will describe the embodiment of the present invention. However, before entering the description, the ISB structure used in the embodiment will be described first.

IjB(Integrated System in B〇ard ;註冊商標），是根據本申 。月案所開發之原創封裝件。ISB係以半導體裸晶片為中心 、電子電路封裝件’而不使用到含有以銅製作之線路型樣 f用來支撐電路零件的核心（基材）的原創無核心系統級封 裝件（c〇reless system in package)。 ， 第2圖係表示ISB之一範例的概要結構圖。於此，為了 谷易知這ISB的全體構造，而僅顯示單一線路層，然而實 際上係由複數之線路層形成層疊構造。在該ISB中，LSI 裸晶片201、Tr裸晶片202以及晶片cr 203形成藉由以銅型 12 315641 200426958 樣205構成之線路進行接線的構造。在LSI裸晶片2〇ι中， 藉由銲接（bonding)金線204而導通引出電極和線路。在乙幻 裸晶片201的正下方，設置有導電膏2〇6，並透過該導電膏 將安裝於印刷線路基板上。而ISB全體則藉由以環氧ς 脂等構成的樹脂封裝體207進行密封。 " 若藉由此封裝，則能得到以下的優點。 ⑴因為能以無核心進行組裝，而可實現電晶體、ic、lSi 的小型·薄型化。 (η)因為可形成及封裝由電晶體到系統Lsi，還有晶片形式 的電容器以及電阻，而能實現高度化系統級封裝件 (SIP，System in Package)。 (iii)因為可組合現有的半導體元件，使系統LSI在短期間 即可開發出。 (iv) 由於將半導體裸晶片直接裝在正下方的銅材上，而能 得到良好的散熱性。 (v) 因為沒有電路線路係銅材之核心材，而具有低介電係 數率的電路線路，在快速資料傳送以及高頻電路上可 發揮優越的特性。 (VI) 因為電極係為在封裝件内部的埋入構造，故可抑制電 極材料之微粒污染（particle contamination)的發生。 (VII) 封裝尺寸沒有限制（free)，而因為將相當於1個封裝件 之廢料與64腳（pin)之SQFP封裝件比較，僅有約1/10的 置’因此能降低環境的負擔。 13 315641 200426958 (vui)從搭載零件的印刷電路基板，到置入機能的電路基板 中，都能實現新的概念的系統結構。 (ix) ISB的型樣設計如同印刷電路基板之型樣設計般容 易，製造商的工程師也可以自行設計。 其次對關於ISB之製造流程上的優點進行說明。第3圖 係為習知之CSP以及有關本發明之isb製造流程的對照 圖。第3(B)圖係表示習知之CSP的製造流程。首先在基底 基板上形成框架（frame)，在由各框架所劃分之元件形成區 域上安裝晶片。之後，在各元件上藉由熱硬化性樹脂設置 封裝體。之後，在每個元件上利用模具進行衝壓。在最後 步驟的衝壓中，因為模製樹脂以及基底基板同時被切斷， 而產生切斷面之表面龜裂等問題。此外因為衝壓結束之後 大置產生廢料，而有環境負擔的問題。 另一方面，第3(A)圖係表示isb的製造流程圖。首先， 在金屬箔上設置框架，在各模組形成區域上，形成線路型 樣並灰其上格載LSI等電路元件。其次在每個模組上施 仃封裝，沿著刮割（scribe)區域進行切塊（dicing)工程，以 得到產品。封裝結束後，在刮割步驟前，因為先除去做為 基底的金屬箔，所以在刮割步驟的切塊工程中，只有對樹 脂層進行切斷。因此，得以抑制切斷面的龜裂，並使切塊 的正確性提高。 ▲ 形熊 以下，有關本發明的較佳實施形態，將以具有前述 構造的半導體模組當作例子進行說明。第4圖係有關本者 315641 14 200426958 施形態的半導體模組的斷面構造的表示圖。該半導體模組 係由，將由線路407所構成的線路層以複數層層疊後於最 上層形成抗銲層（s〇lderresist)408之多層線路構造體，以及 在其表面所形成之元件41〇a以及41〇b所構成。其中，該線 路層係由層間絕緣膜405以及銅所構成。在多層線路構造 體的背面，設置有銲錫球420。元件410a以及410b係為以 模製樹脂415所封模的構造體。在第4(b)圖中，相對於第4(&) 圖的構造，更進一步設置了由金屬材料構成的假（dummy) 線路435。由此，可提高多層線路構造體和模製樹脂415之 間的緊密結合性。 有關元件410a的組裝方法中，雖然在第4圖中採用了銲 線銲接方式（wire bonding)，然而也可如第1 〇圖所示把元件 41〇&以面朝下（&“（1(^11)配置之方式進行覆晶式卬 組裝。 ^在如第1圖所示之習知半導體模組中，LSI晶片102具有 糟由封裝樹脂密封裸晶片之晶片構造。相對於此，在第4 ，的半導體模組中，元件物係具有沒有藉由封裝樹脂封 裝的裸^。為此’必須更加確實地實行吸㈣策。在模 製樹脂415和多層線路構造之間的界面若產生剝離，則例 如在銲錫步驟中，水分會由該處浸人，使裸晶片直接受到 水分的影響。在此情況’會造成晶片之性能大幅度損害的 結果。由A ’在如第4圖所示之ISB構造的半導體模組中， ::改善該界面的緊密結合性而充分抑制水分的透過係 已成為重要的技術課題。 315641 15 200426958 為了解決這樣的課題，在本實施形態中，藉由 f條件之電聚處理，對抗銲層彻的表面進行改質。具體而 吕」係在抗銲層408之與模製樹脂4〗5連接側的表面上，形 成，小突起群。此外，在抗輝層侧的上述表面上，當將束 缚月匕-284.5 eV的檢測強度當作X，將束缚能_286 ^的檢測 強度當作3^，使X線光電子分光分析光譜之y/χ之值於04 以上。 、 還有，使抗銲層408之連接模製樹脂415的區域在露出 時，對純水的接觸角係於30至120度範圍内。 可各自獨立選擇樹脂材料作為構成抗銲層4〇8、層間絕 緣膜405以及模製樹脂415的材料，例如，可列出樹脂 (Resm)等之三聚氰胺（meiamine)衍生物、液晶聚合物 (=〇ly=)、環氧樹脂、ppE樹脂、聚醯亞胺㈣咖此)樹 脂、氟樹脂、酚（phen〇l)樹脂、聚醯胺雙馬來醯亞胺 (polyarmde bismaleimide)等之熱硬化性樹脂。其中，較宜 使用在高頻特性方面較卓越的液晶聚合物、環氧樹脂、訂 樹脂等之三聚氰胺誘導體。除了這些樹脂，也可適宜地添 加填充物（filler)或添加劑。 另外，宜使用環氧樹脂、BT樹脂、液晶聚合物等作為 ，成本發明之絕緣基材的材料。藉由使用這樣的樹脂，可 得到具有卓越之高頻特性以及產品可靠性的半導體模 組。 、 其次，關於如第4(a)圖所示之半導體模組的製造方法， 將蒼照第5至7圖進行說明。首先，如第5(A)圖，在金屬箔 315641 16 200426958 400之預定表面上選擇形成導電被覆膜402。具體而言，以 光阻（photo resist)401覆蓋金屬箔400之後，藉由電場電鑛 法，在金屬箔400的露出面上形成導電被覆膜402。將導電 被覆膜402的膜厚形成為例如1至10 μηι的程度。由於該導 電被覆膜402最終成為半導體模組的背面電極，所以較宜使 用與銲錫等銲料之接著性良好的金或銀形成。 其次，如第5(B)圖所示，在金屬箔400上，形成第一層 的線路型樣（pattern)。首先對金屬箔400進行化學研磨以進 行表面清潔和表面粗化。其次，在金屬箔400上以熱硬化性 ® 樹脂覆蓋導電被覆膜4 0 2之全面，對其加熱硬化使其成為具 有平坦表面的膜體。其次，在該膜中，形成到達導電被覆 膜402之直徑100左右的通孔（via hole)404。有關設置通孔 404的方法，在本實施形態中係以雷射加工進行，然而除此 之外，也可使用機械加工、藉由藥液之化學餘刻加工、使 用電漿的乾蝕刻法等。之後，以雷射照射除去蝕刻殘渣之 後，以填埋通孔404之方式在全面上形成銅電鍍層。之後，_ 將光阻作為遮罩（mask)以蝕刻銅電鍍層，而形成由銅構成 的線路407。例如，可在從光阻露出的部位上，喷灑化學蝕 刻液，將不需要的銅箔蝕刻除去，而形成線路型樣。 如以上所述，藉由反覆進行層間絕緣膜405的形成、通 孔形成、銅電鍍層的形成以及銅電鍍層之型樣化之步驟， 而可如第5(C)圖所示，由線路407以及層間絕緣膜405構成 之線路層層疊而形成多層線路構造。 17 315641 200426958 其次，如第6(A)圖所示，在形成抗銲層408之後，藉由 雷射加工在抗銲層408中形成接觸孔（contact hole)421。其 中’可使用含有填充物之環氧樹脂系絕緣膜作為抗銲層408 的構成材料。在本實施形態中係藉由雷射加工進行，然而 除此之外，也可使用機械加工、藉由藥液之化學蝕刻加工、 乾姓刻法等。之後，藉由電漿照射除去做蝕刻殘渣。在本 貝加形態中’係使用由氬以及氧構成的電漿氣體進行該電 漿處理。 為形成具有前述形態（morphology)以及樹脂特性的表 面層，而按照所使用的樹脂材料適宜地設定電漿照射條 件。還有，較宜不對基板施加偏壓。例如可用如以下的條 件進行。 偏壓·無施加 電漿氣體：氬10至20sccm，氧〇至i〇sccm 藉由該電衆照射，除了除去線路407表面的蝕刻殘渣 外，也對抗録層4G8的表面進行改質，而形成具有前述形 態以及樹脂特性之表面層。 其次如第6(B)圖所示，在抗輝層彻上搭載元件她、 41〇b。有關元件410，可採用電晶體、二極體、ic晶片 導體元件，或晶片電容、晶片電阻等被動元件。還 :t:CSP、BGA等面朝下的半導體元件。在第6(B)圖的 構造中，元件偷是未封著之料導體 )牛疋曰曰片電容器。將這些元件固定於抗銲層 彻上。以此狀態再度進行電漿處理。為形成具有前述形； 315641 200426958 以及樹脂特性的表面層，而按照所使用的樹脂材料適宜地 叹疋電漿照射條件。還有，較宜不對基板施加偏壓。例如 可用如以下的條件進行。 偏壓：無施加 笔水氣肢·氬10至20 seem ，氧〇至10 seem 藉由該電漿照射，除了可除去線路407表面的蝕刻殘渣 外，也可對抗銲層408的表面進行改質，而形成具有前述 形怨以及樹脂特性的表面層。 之後’透過經形成之通孔，藉由線路4〇7以及金線412 連接元件41〇a之後，以模製樹脂（㈤“⑴叩resin)4i5對這些 〜構進行封裝。第7(A)圖表示被封裝後的情況。半導體元 件1封裝係對設置於金屬領4〇〇上之複數個模組，用模具 5寸進行4步驟可藉由轉移成模（transfer mold)、射出 成，（injection m〇id)、膠埋法（p〇tting)或浸潰法⑷卯★) 而貝現。在樹脂材料中，環氧樹脂等熱硬化性樹脂可用在 轉移成模或膠埋法中實行，而聚酿亞胺樹脂等熱塑性樹脂 則可在射出成型中實行。 之後，如第7(B)圖所示，從多層線路構造除去金屬箔 並在月面上形成銲錫球42〇。其中，可藉由拋光、研 、雷射之金屬蒸發等進行金屬㈣㈣除去。在本 裝】用以下的方法。亦即，藉由拋光裝置或研磨 2 ，孟V自400削除5〇μΐΏ左右，而剩餘的金屬箔400則夢 ΪΓ入式,濕㈣料。财，切以藉由濕㈣除去金屬曰 / 卩。藉由透過這樣的步驟，在搭載半導體元件側之 315641 19 200426958 :::开的1?上’使第1層線路407的背面露出。據此，由 恐侍到之模組的背面可變得平坦，而可且有此制 力而水平移動，:=時，能藉由鲜錫等表面張 〜易進仃自對準（se】f-align)#。並次， 在路出之導電被覆膜402上被覆固 並 =〇;而完成半導體模組。之後，藉由二::: 曰曰®(wafer)，而可得到半導體模組晶片。直到上 箱400之除去步驟為止，係將金屬㈣ 、在 =〇7形成時的電解電鏟步驟中，也可利用金屬;二： =極。此外，當使模製樹脂化成模時，其也可使至模I 。模具之組裝操作性變得良好。進行如以上之作法， 而可得到如第4(A)圖所示之構造的半導體模組。' 術進亥半^體^且’在第6(B)圖之步驟中’因為對抗鮮層 和梅二^ ’而進行表面改質的關係’使抗銲層彻 ^衣樹脂415之間的界面緊密結合性明顯地改善。直社 果，可使半導體模組的可靠性明顯提高。 ° 火::狀=’因為除了微小突起’還可在表面形成複數 山口狀凹部，而可更加改善緊密結合性。 至於抗銲層408的表面是否存在凹凸狀，可斜切斷抗銲 使用掃描型電子顯微鏡觀察等分析其斷面而確 315641 20 200426958 部等部位沒有藉由模製 凹凸存在，也能使用掃 之分析而確認。 此外，例如，在如抗鐸層4〇8端 樹脂415封裝的部份之表面是否有 描型電子顯微鏡觀察等進行該表面 實施形熊 在第-實施形態中，具有在抗銲層彻上由銲 =、r牛侧的結構’然而若不利用銲錫，也能以接 者兀件。在該情況下，也可形成沒有設置抗辉層 第9®絲*沒有抗銲料，直接將元件接著於線路上 的、、、。構。多層線路構造係具有於第一實施形態中所說明者 ::同構造。在本實施形態中，係使用環氧樹 絕緣膜405。 ~曰间 ★該半導體模組可如以下所述般進行製造。首先進行到 弟5(C)圖為止的步驟。隨後，如第8圖般藉*接著劑而 =件4U)a、元件侧。在該狀態下對元件形成面進行電嘴 處理。電㈣理係以第-實施形態之同樣方式進行。藉由 該電漿照射’使線路4〇7的表面具有清潔的狀態，而使^件 41〇a、元件410b以及線路4〇7間可具有良好的接線。此外， 此$並藉由電漿處理而同時對層間絕緣膜4〇5的表面進行 改質，而形成具有前述之形態以及樹脂特性的表面層。 之後，藉由線路407和金線412對元件41〇a進行接線之 後，以模製樹脂415對這些結構進行封模。根據以上之步驟 而可得到如第9圖所示之構造的半導體模組。該半導體模组 在第8圖的步驟中，因為對層間絕緣磨4〇5進行氬電漿處 315641 21 200426958 理，而進行表面改質的_ ’使相絕緣㈣5和模製樹脂 415之間的界面緊密結合性明顯改善。該結果可使半導體模 組的可靠性明顯提高。 且、 於此’也可以用含有多官能氧環丁烷化合物或環氧樹 月旨化合物的光硬化性·熱硬化性樹脂，作為構成層間絕緣 磨層彻的材料。藉此，因為除了微小突起，還可在表面形 成複數火山π狀凹部，而可更加改善緊密結合性。 此外’可斜切斷層間絕緣膜層彻後，使用择描型電子 顯微鏡觀察等分析其斷面而進行在絕緣膜層彻的表面是 否有凹凸狀存在之確認。 此夕卜，例如 制 ，隹如絶緣膜層405端部等部位沒有藉由模 衣難415封農的部份之表面是否有凹凸狀存在，也能使用 ^描型電子顯微鏡觀察等進行該表面之分析而確認。 居^貝施形辑 透過接著材料5 1 〇 在本實施形態中，如第;15圖所示 將元件502接著於基板5〇6上。 上據此，在元件502和基板506間界面之緊密結合性不佳 :活’會有從該地方發生元件5〇2剝離的疑慮，而造成 肢模組之可靠性大幅度損害的結果。 守 ttl解決這樣的課題，在本實施形態中，藉由選擇和 灵鈿形怨以及第二實施型態相同的條件之電漿處理， 而對.連接接著材料51〇之基板5〇6的表面進行改質。其中， =接著材料510係連接元件5〇2的下表面。具體而言了係在 土板506具有線路層的表面上，形成微小突起群和，例如， 315641 22 200426958 直徑100 nm以上之複數火山口狀凹部。此外，在基板5〇2 之上述表面上，當將束缚能-284.5 eV的檢測強度當作X， 將束缚能-286 eV的檢測強度當作y時，係使χ線光電子分光 分析光譜之y/x之值於0.4以上。 還有，在露出基板506之與模製樹脂415連接的區域 時，其對純水的接觸角係在30至12〇度的範圍内。 在這裡，也可以用含有多官能氧環丁烷化合物或環氧 ， 化合物的光硬化性·熱硬化性樹脂作為構成基板5〇6的材、 料。藉此，因為除了微小突起外，還在表面形成複數之火籲 山口狀凹部，而可改善緊密結合性。 此外，可斜切斷基板506後，藉由使用掃描型電子顯微 鏡觀察等分析其斷面而進行在基板5〇6的表面是否有凹 狀存在之確認。 此外例如，在如基板5〇6端部等部位沒有藉由模製樹 脂415封裝的部份之表面是否有凹凸狀存在，也能藉由使用 掃描型電^顯微鏡觀料進行該表面之分析而確認。 以上說明了適合本發明之實施形態。但是，本發明非 僅限定於上述之實施形態，本業者在本發明的範圍二當铁 也可貫行上述之實施形態的變型。 例如 進行說明 有關上述之實施形態中， 然而本發明也可適用於 係對半導體模組相關 半導體模組以外的模 中，係對採用設置有線路 ，然而，也可以採用例如 此外，有關上述之實施形態 4〇7的抗銲層4〇8之形態進行說明 315641 23 200426958 之導電體的抗 "又置有導線架（lead frame)等之線路407以外 銲層。 此外’有關上述之實施形態中’係針對使用抗桿層楊 為、、、邑緣基材的形態進行說明，然而也可以使用絕緣基材以 外的基材。 實施例 實施例1 在銅镇表面貼上乾抗㈣（dry film resist)(商品名 PDF300,新日鐵化學社製）之後，冑該抗餘膜進行型樣化， 而露出銅絲面之-部份。在該狀態下，對含㈣露出面 ，及乾抗蝕膜面之全面進行氬電漿處理。其中，改變電漿 氣體裏面的氧濃度而製造出2種類的樣品。 偏壓電壓：無施加 电漿氣體·樣品1氬1 〇 seem，氧〇 sccm 樣品 2 氬 1〇 seem，氧 1〇 sccm RF功率（w) : 500 壓力（Pa) : 20 處理時間（sec) : 20 ^藉由掃描型電子顯微鏡，而對電漿照射前後的乾抗蝕 膜表面進行了觀察。結果如第丨丨圖、第12圖以及第〗3圖所 不。第Π圖表示樣品1、第12圖表示樣品2、第13圖表示未 電漿處理之外觀。可清楚地瞭解，藉由電漿照射可在樹脂 ，面形成複數之微小突起。使用藉由掃描型電子顯微鏡觀 祭所彳于到的晝像資料，對微小突起的平均直徑以及密度進 24 315641 200426958 行測定。密度係對長度1 μπι之直線上之微小突起數量（、線密 度）進行測定，並將該數量乘以2後而求得。將結果於以下 表不。 樣品1 平均直徑4 nm 數量密度1·2χ 103個/μπι2 樣品2 平均直徑4 nm 數量密度1·6χ 103個/μιη2 其次，對該樣品1、2相關進行X線光電子分光分析。 將結果表示於第14圖。在圖中，除了樣品〗、2外，也顯示 了氬電漿處理前的曲線以作為參照。可知道藉由電裝日、召 射，在有關286 eV的C=0結合而來的強度增加的同時，有 關284.5 eW-〇結合或c—縣合而來的強度反而減 少。把有關284.5 eV的C—〇結合或c —N結合而來的強度 當作X，把有關286 eV的〇〇結合而來的強度當作y時，^ 有關本實施例之模組之y/x的數值中，樣品】、2都大約為 0.44。 ^ 續之，對該樣品1、2測量接觸角。在抗蝕膜表面上滴 下純水後，以放大鏡觀察水滴形狀並測量其接觸角。該接 觸角之測定係於樣品製作2天後進行。所得到的接觸角數值 係如下所示。據此，可知在採用乾抗蝕膜（商品名p d f 3 〇 〇， 315641 25 200426958 新曰鐵化學社製）的樣品1、樣品2中，具有接觸角為30至70 度之令人滿意的表現。 樣品1 52.0度 樣品2 53.6度 於第一實施型態所陳述之製程中，應用與上記樣品1 以及樣品2同樣之成模、電漿處理製程以製造半導體模組。 該半導體模組將樣品1、2的乾抗蝕膜作為抗銲層，並於其 表面搭載有半導體元件。對該半導體模組進行評價後，除 了熱循環（heat cycle)性十分卓越外，於壓力锅（pressure cooker)試驗也有良好的結果。 實施例2 在銅箔表面上貼上乾抗蝕膜（商品名AUS402，太陽 INK社製）之後，對該抗蝕膜進行型樣化，而露出銅箔表面 之一部份。在該狀態下，對含銅箔露出面以及環氧樹脂系 抗蝕膜面之全面進行氬電漿處理。 此外，於此，上述之乾抗蝕膜（商品名AUS402，太陽 INK社製）因為係使用含有多官能氧環丁烷化合物或環氧 化合物的光硬化性·熱硬化性樹脂所製造出，而在表面存 在有火山口狀凹部。 偏壓：無施加 電漿氣體：氬1 〇 seem，氧0 seem RF功率（W) : 500 壓力（Pa) : 20 26 315641 200426958 處理時間··樣品3 : 20〇ec〇 樣品 4 : 60(see) 精由掃描型電子顯微鏡，對電漿照射前後的乾抗蝕膜 表面進行了觀察。結果如第16圖、第Π圖以及第18圖所 示第16圖係表示樣品3、第17圖係表示樣品4、第丨8圖係 表示未電漿處理之外觀。可清楚地瞭解，藉由電漿照射可 在树月曰表面升乂成複數之微小突起。使用藉由掃描型電子顯 微鏡觀察所得到的畫像資料，對微小突起的平均直徑以及 密度進行測定。密度係對長度1 μηι之直線上之微小突起數 量（線密度）進行測定，並將該數量乘以2後而求得。將結果 於以下表示。 ° 樣品3 平均直徑4 nm 數量密度2χ 1〇3個/μπι2 樣品4 平均直徑4 nm 數量密度2χ 1〇3個/μηι2 其次，對上述樣品進行χ線光電子分光分析。將結果表 不於第19圖。在圖中，係將氬電漿處理前的曲線作為參照 而顯示樣品4的曲線。可知道藉由電漿照射，在有關以^二 的〇〇結合而來的強度增加的同時，有關284·5 之c一 〇 315641 27 200426958 結合或C —N結合而來的強度反而減少。把有關284 5 eV的 C—〇結合或C —N結合而來的強度當作χ，把有關286以的 c=〇結合而來的強度當作㈣，有關本實施例的模組之y/x 的數值約為〇·4。 、、，之，對上述樣品進行接觸角的量測。在抗蝕膜表面 上滴下純水後’以放大鏡觀察水滴形狀並測量其接觸角。 該接觸角之測定係於樣品製作2天後進行。所得到的接 的數值係如下所示。 樣品3 8 0度 樣品4 10 5度 於第-實施型態所陳述之製程中，應用與上述樣 樣之成模、電漿處理製程，而製造半導體模組。該半導 模組將上述樣品的乾抗蝕膜作為抗銲層，並於其表面搭 有半導體元件。對該半導體模組進行評價後，除了熱猶戸 性十分卓越外，於壓力鍋試驗也具有良好的結果。 衣 【圖式簡單說明】 苐1圖係為BGA構造的說明圖。 昂2圖係為ISB(登錄商標）構造的說明圖。 第3(A)及3(B)圖係為BGA以及ISB(登錄商標）之製、生 流程的說明圖。 衣& 第4(a)及4(b)圖係為相關半導體模組之構造的說明 圖0 第5(A)至5(C)圖係為相關半導體模組之製造方法的 315641 28 200426958 說明圖。 第6(A)及6(B)圖係為相關半導體模組之製造方法的 說明圖。 第7(A)及7(B)圖係為相關半導體模組之製造方法的 說明圖。 第8圖係為相關半導體模組之製造方法的說明圖。 弟9(A)及9(B)圖係為相關半導體模組之製造方法的 說明圖。 / 第10(a)及10(b)圖係為相關半導體模組之構造的說 圖。 第11圖係藉由掃猫型電子顯微鏡觀察電聚處理後之 抗钱膜表面的結果的表示圖。 >第12圖係藉由掃瞄型電子顯微鏡觀察電漿處理後之 抗钮膜表面的結果的表示圖。 抗丄1二由掃猫型電子顯微鏡觀察電衆處理後之 抗姓Μ表面的結果的表示圖。 第14圖係為電襞處理後之抗钮膜表面之 分光分析結果的表示圖。 =圖係為相關半導體模組之構造的說明圖。 抗㈣表㈣料的表示/子七枝㈣電漿處理後之 第17圖係藉由掃瞄 抗㈣表㈣結果的表示圖。相鏡料錢處理後之 第18圖係藉由掃猫型電子顯微鏡觀察電漿處理後之 315641 29 200426958 抗姓膜表面的結果的表示圖。 第19圖係為電漿處理後之抗蝕膜表面之X線光電子 分光分析結果的表示圖。 【主要元件符號說明】 100 球閘陣列封裝（BGA) LSI 晶片 1〇4 金屬線 i〇6 環氧基板 108 接著層 Π〇 封裝樹脂 112 鲜錫球 2〇ι LSI裸晶片 202 Tr裸晶片 203 晶片CR 204 金線 2〇5 銅型樣 206 導電膏 2〇7 樹脂封裝體 208 鲜錫球 4〇〇 金屬镇 401 光阻 402 導電被覆膜 404 通孔 405 層間絕緣膜 407 線路 408 抗鲜層 410a， 4 1 0 b元件 412 金線 415 模製樹脂 420 録锡球 421 接觸孔 435 假線路 502 元件 5〇6 基板 510 接著材料 315641 30IjB (Integrated System in B〇ard; registered trademark) is based on this application. Original package developed by the monthly case. The ISB is an electronic circuit package centered on a semiconductor bare chip. It does not use an original coreless system-level package (coreless) that contains a copper-made circuit pattern f to support the core (substrate) of a circuit part. system in package). FIG. 2 is a schematic configuration diagram showing an example of an ISB. Here, in order to know the overall structure of this ISB, only a single wiring layer is shown, but in reality, a stacked structure is formed by a plurality of wiring layers. In this ISB, the LSI bare wafer 201, the Tr bare wafer 202, and the wafer cr 203 have a structure in which wiring is formed by a line made of copper type 12 315641 200426958 sample 205. In the LSI bare chip 200m, the lead-out electrode and the wiring are conducted by bonding a gold wire 204. A conductive paste 206 is provided directly below the B-die bare wafer 201, and will be mounted on the printed circuit board through the conductive paste. The entire ISB is sealed with a resin package 207 made of epoxy resin or the like. " By this packaging, the following advantages can be obtained. ⑴ Because it can be assembled without a core, it is possible to reduce the size and thickness of transistors, ICs, and lSi. (η) Since a transistor to the system Lsi can be formed and packaged, and a capacitor and a resistor in the form of a wafer can be formed and packaged, a highly advanced system in package (SIP) can be realized. (iii) Because existing semiconductor elements can be combined, system LSIs can be developed in a short period of time. (iv) Since the bare semiconductor chip is directly mounted on the copper material directly below, good heat dissipation can be obtained. (v) Because there is no core material of copper wire, the circuit wire with low dielectric coefficient rate can exert excellent characteristics in fast data transmission and high-frequency circuit. (VI) Since the electrode system is embedded in the package, particle contamination of the electrode material can be suppressed. (VII) There is no restriction on the package size, and because the waste equivalent to one package is compared with the SQFP package with 64 pins, there is only about one-tenth the position ', which can reduce the burden on the environment. 13 315641 200426958 (vui) From the printed circuit board on which the components are mounted to the functional circuit board, a new concept system structure can be realized. (ix) The design of the ISB pattern is as easy as that of the printed circuit board, and the engineer of the manufacturer can also design it by himself. Next, the advantages of the manufacturing process of the ISB will be described. Fig. 3 is a comparison diagram of the conventional CSP and the isb manufacturing process related to the present invention. Fig. 3 (B) shows a manufacturing process of a conventional CSP. First, a frame is formed on a base substrate, and a wafer is mounted on an element formation area divided by each frame. Thereafter, a package is provided on each element with a thermosetting resin. Thereafter, a die is used for punching on each component. In the pressing of the last step, the molding resin and the base substrate are cut at the same time, which causes problems such as surface cracks on the cut surface. In addition, there is a problem of environmental burden because waste material is generated after the completion of stamping. On the other hand, FIG. 3 (A) shows a manufacturing flow chart of the isb. First, a frame is provided on a metal foil, and a circuit pattern is formed on each module formation area, and circuit elements such as LSI are mounted thereon. Secondly, encapsulation is performed on each module, and a dicing process is performed along the scribe area to obtain a product. After the encapsulation is completed, before the scraping step, the metal foil used as the substrate is removed. Therefore, in the cutting process of the scraping step, only the resin layer is cut. Therefore, cracks in the cut surface can be suppressed, and the accuracy of dicing can be improved. ▲ Shaped Bear In the following, a preferred embodiment of the present invention will be described using a semiconductor module having the aforementioned structure as an example. FIG. 4 is a diagram showing a cross-sectional structure of a semiconductor module in a form of 315641 14 200426958. This semiconductor module consists of a multilayer circuit structure in which a circuit layer composed of a circuit 407 is laminated in a plurality of layers to form a solder resist 408 on the uppermost layer, and an element 41a formed on its surface. And 41〇b. The line layer is composed of an interlayer insulating film 405 and copper. A solder ball 420 is provided on the back surface of the multilayer wiring structure. The elements 410a and 410b are structural bodies sealed with a molding resin 415. In Fig. 4 (b), a dummy line 435 made of a metal material is further provided in comparison with the structure of Fig. 4 (&). Thereby, the close bonding property between the multilayer wiring structure and the molding resin 415 can be improved. In the assembly method of the element 410a, although the wire bonding method is used in FIG. 4, the element 41〇 & can be face down (& "( 1 (^ 11) configuration for flip chip assembly. ^ In the conventional semiconductor module shown in Fig. 1, the LSI wafer 102 has a wafer structure in which a bare wafer is sealed with a sealing resin. In contrast, In the fourth semiconductor module, the component system has a bare body that is not encapsulated with a sealing resin. For this reason, it is necessary to implement a suction strategy more surely. If the interface between the molding resin 415 and the multilayer wiring structure is When peeling occurs, for example, in the soldering step, moisture will be immersed there, and the bare wafer will be directly affected by moisture. In this case, the result of the wafer's performance will be greatly impaired. From A 'in Figure 4 In the semiconductor module of the ISB structure shown, :: Improving the tight bonding of the interface and sufficiently suppressing the transmission of moisture has become an important technical issue. 315641 15 200426958 In order to solve such problems, in this embodiment, By f The surface of the anti-welding layer is modified by the electro-polymerization treatment of the pieces. Specifically, Lv "is formed on the surface of the anti-solder layer 408 on the side of the connection with the molding resin 4 and small protrusions. In addition, On the above surface of the bright layer side, when the detection intensity of the bound moon -284.5 eV is taken as X, and the detection intensity of the bound energy _286 ^ is taken as 3 ^, the value of y / χ of the X-ray photoelectron spectroscopic analysis spectrum is made. Above 04. Also, when the area where the mold resin 415 is connected to the solder resist layer 408 is exposed, the contact angle with pure water is in the range of 30 to 120 degrees. Resin materials can be independently selected to form the solder resist. The material of the layer 408, the interlayer insulating film 405, and the molding resin 415 can be listed, for example, melamine derivatives such as resin (Resm), liquid crystal polymer (= 〇ly =), epoxy resin, ppE Resins, polyimide resins), thermosetting resins such as fluororesin, phenol resin, phenol resin, polyarmde bismaleimide, etc. Among them, it is more suitable to be used in high Trimerization of liquid crystal polymers, epoxy resins, and custom resins with excellent frequency characteristics Cyanamine inducer. In addition to these resins, fillers or additives may be added as appropriate. In addition, epoxy resin, BT resin, liquid crystal polymer, etc. are preferably used as materials for the insulating base material of the invention. By using such a resin, a semiconductor module having excellent high-frequency characteristics and product reliability can be obtained. Second, regarding the method for manufacturing a semiconductor module as shown in FIG. 4 (a), Cang according to FIGS. 5 to 7 First, as shown in FIG. 5 (A), a conductive coating film 402 is selectively formed on a predetermined surface of a metal foil 315641 16 200426958 400. Specifically, after the metal foil 400 is covered with a photo resist 401, a conductive coating film 402 is formed on the exposed surface of the metal foil 400 by an electric field electrospinning method. The film thickness of the conductive coating film 402 is, for example, about 1 to 10 μm. Since the conductive coating film 402 eventually becomes the back electrode of the semiconductor module, it is more preferable to form the conductive coating film 402 with gold or silver having good adhesion to solder such as solder. Next, as shown in FIG. 5 (B), a first layer circuit pattern is formed on the metal foil 400. First, the metal foil 400 is chemically ground for surface cleaning and surface roughening. Next, the entire surface of the conductive coating film 402 is covered with a thermosetting resin on the metal foil 400, and then heat-hardened to form a film having a flat surface. Next, a via hole 404 having a diameter of about 100 and reaching the conductive coating film 402 is formed in the film. The method of providing the through-holes 404 is performed by laser processing in this embodiment. However, in addition to this, mechanical processing, chemical post-processing using a chemical solution, and dry etching using a plasma may be used. . After that, after the etching residue is removed by laser irradiation, a copper plating layer is formed on the entire surface by filling the via hole 404. After that, the photoresist is used as a mask to etch the copper plating layer to form a wiring 407 made of copper. For example, a chemical etching solution may be sprayed on a part exposed from the photoresist, and an unnecessary copper foil may be etched and removed to form a circuit pattern. As described above, the steps of forming the interlayer insulating film 405, forming a via hole, forming a copper plating layer, and patterning the copper plating layer are performed repeatedly, as shown in FIG. 5 (C). The wiring composed of 407 and the interlayer insulating film 405 is laminated to form a multilayer wiring structure. 17 315641 200426958 Next, as shown in FIG. 6 (A), after the solder resist 408 is formed, a contact hole 421 is formed in the solder resist 408 by laser processing. Among them, an epoxy-based insulating film containing a filler can be used as a constituent material of the solder resist layer 408. In this embodiment, it is performed by laser processing. However, in addition to this, mechanical processing, chemical etching processing by a chemical solution, dry name engraving, etc. may be used. After that, the etching residue is removed by plasma irradiation. In this Bekaa form, the plasma treatment is performed using a plasma gas composed of argon and oxygen. In order to form a surface layer having the aforementioned morphology and resin characteristics, the plasma irradiation conditions are appropriately set according to the resin material used. It is also preferable not to apply a bias voltage to the substrate. For example, the following conditions can be used. Bias and non-applied plasma gas: 10 to 20 sccm of argon, and 0 to 10 sccm of argon. Irradiation with this electric mass not only removes the etching residue on the surface of the line 407, but also reforms the surface of the recording layer 4G8 to form A surface layer having the aforementioned form and resin characteristics. Next, as shown in FIG. 6 (B), a component 41b is mounted on the anti-glow layer. As for the element 410, a transistor, a diode, an IC chip conductive element, or a passive element such as a chip capacitor and a chip resistor can be used. Also: t: CSP, BGA and other face-down semiconductor components. In the structure of Fig. 6 (B), the component is an unsealed material conductor. These components are fixed on the solder resist. In this state, plasma treatment was performed again. In order to form a surface layer having the aforementioned shape; 315641 200426958 and resin characteristics, the plasma irradiation conditions are appropriately sighed according to the resin material used. It is also preferable not to apply a bias voltage to the substrate. For example, the following conditions can be used. Bias: No application of water, gas limbs, argon 10 to 20 seem, oxygen 0 to 10 seem. With this plasma irradiation, in addition to removing the etching residue on the surface of the line 407, it can also resist the surface modification of the solder layer 408. To form a surface layer having the aforementioned shape and resin characteristics. After that, the components 41oa are connected through the formed through holes and the wires 407 and gold wires 412, and then these structures are packaged with a molding resin (㈤ "㈤resin) 4i5. Section 7 (A) The figure shows the situation after being packaged. The package of semiconductor element 1 is a set of four modules placed on a metal collar 400, which can be performed in 4 steps by using a 5-inch mold. injection m〇id), embedding method (potting) or impregnation method (⑷ 卯 ★), and is now available. In resin materials, thermosetting resins such as epoxy resin can be used for transfer molding or embedding method. However, thermoplastic resins such as polyimide resins can be implemented in injection molding. After that, as shown in Figure 7 (B), the metal foil is removed from the multilayer wiring structure and solder balls 42 are formed on the moon. Among them, The metal can be removed by polishing, grinding, laser metal evaporation, etc. In this installation, the following method is used. That is, by using a polishing device or a grinding machine 2, Meng V is cut from 400 to about 50 μΐΏ, and the remaining The metal foil 400 is a dream type, wet material. Wealth, cut with wet Metal removal / 曰. By following this procedure, the back side of the first layer wiring 407 is exposed on the 315641 19 200426958 ::: open 1? On the side where the semiconductor device is mounted. According to this, the model will The back of the group can be flat, and it can move horizontally with this force. When ==, it can be stretched by the surface such as fresh tin. ~ Self-alignment (se) f-align) #. Also, The semiconductor module is completed by covering and fixing the conductive coating film 402 on the way out. After that, the semiconductor module wafer can be obtained by 2 ::: wafer. Until the upper case 400 Up to the removal step, the metal ㈣ can also be used in the electrolytic shovel step at the time of formation of 〇7; two: = pole. In addition, when the molding resin is formed into a mold, it can also reach the mold I The mold assembling operability becomes good. By performing the above-mentioned method, a semiconductor module having a structure as shown in FIG. 4 (A) can be obtained. In the step of the figure, the relationship between the surface modification due to the anti-fresh layer and plum ^ 'makes the interface between the solder resist layer and the resin 415 tightly bonded. Significant improvement in the bonding performance. The reliability of the semiconductor module can be significantly improved by the direct result. ° Fire :: shape = 'Besides small protrusions', multiple mountain-shaped recesses can be formed on the surface, which can further improve the tight bonding. As for whether the surface of the solder resist layer 408 has unevenness, the solder resist can be cut obliquely, and its cross section can be analyzed using a scanning electron microscope to confirm that 315641 20 200426958 and other parts do not exist by molding. In addition, for example, if the surface of the portion sealed with the 408 end resin 415 of the anti-corrosion layer has a tracing electron microscope observation, the surface is formed. The structure of the solder layer is completely formed by soldering. However, if soldering is not used, it is possible to connect the components. In this case, it is also possible to form the 9th wire without the anti-glow layer * without solder resistance, and directly attach the element to the circuit.结构。 Structure. The multilayer wiring structure has the same structure as described in the first embodiment. In this embodiment, an epoxy resin insulating film 405 is used. ~ Said ★ This semiconductor module can be manufactured as described below. First, proceed to the step 5 (C). Subsequently, as shown in FIG. 8, by using the * adhesive agent, the component 4U) a, the component side. Nozzle processing is performed on the element formation surface in this state. Electrical management is performed in the same manner as in the first embodiment. By the plasma irradiation ', the surface of the wiring 407 is kept in a clean state, so that good connections can be made between the components 41a, 410b, and the wiring 407. In addition, the surface of the interlayer insulating film 405 is modified by plasma treatment at the same time to form a surface layer having the aforementioned shape and resin characteristics. After that, the components 41a are connected by the wiring 407 and the gold wire 412, and then these structures are sealed with a molding resin 415. According to the above steps, a semiconductor module having a structure as shown in FIG. 9 can be obtained. In the step of FIG. 8, the surface modification of the interlayer insulation mill 405 was performed because of the argon plasma treatment 315641 21 200426958, and the surface modification of _ 'makes the phase insulation ㈣5 and the molding resin 415 The interface tightness was significantly improved. This result can significantly improve the reliability of the semiconductor module. In addition, a photo-curable and thermo-curable resin containing a polyfunctional oxycyclobutane compound or an epoxy resin compound may be used here as a material constituting the interlayer insulation and the abrasive layer. Thereby, in addition to the minute protrusions, a plurality of volcano pi-shaped depressions can be formed on the surface, and the tight adhesion can be further improved. In addition, after the interlayer insulating film layer can be cut obliquely, the cross section can be analyzed using a selective-scanning electron microscope to check whether the uneven surface exists on the surface of the insulating film layer. In addition, for example, if there is no unevenness on the surface of the portion such as the end of the insulating film layer 405 that is difficult to seal by 415, it can also be observed using a tracing electron microscope. Analysis. In this embodiment, as shown in FIG. 15, the element 502 is bonded to the substrate 506 as shown in FIG. 15. According to the above, the close bonding of the interface between the element 502 and the substrate 506 is not good: there may be a concern that the component 502 peels from the place, and the reliability of the limb module is greatly damaged. Shou ttl solves such a problem. In this embodiment, the surface of the substrate 506 which is bonded to the material 51 is connected to the surface of the substrate 506 by selecting a plasma treatment under the same conditions as the resentment and the second embodiment. Make improvements. Among them, the bonding material 510 is the lower surface of the connecting element 502. Specifically, it is formed on the surface of the soil plate 506 having a wiring layer, and forms a group of microprotrusions, for example, 315641 22 200426958 a plurality of crater-like recesses having a diameter of 100 nm or more. In addition, on the above surface of the substrate 50, when the detection intensity of the binding energy -284.5 eV is taken as X, and the detection intensity of the binding energy -286 eV is taken as y, the y of the x-ray photoelectron spectroscopic analysis spectrum is used. The value of / x is 0.4 or more. When the area of the substrate 506 connected to the molding resin 415 is exposed, the contact angle with pure water is in the range of 30 to 120 degrees. Here, a photo-curable and thermo-curable resin containing a polyfunctional oxycyclobutane compound or an epoxy compound may be used as the material or material constituting the substrate 506. Thereby, in addition to the minute protrusions, a plurality of fire-pitched recesses are formed on the surface, so that the close bonding property can be improved. In addition, after the substrate 506 can be cut diagonally, the cross section can be analyzed with a scanning electron microscope to confirm whether there is a concave shape on the surface of the substrate 506. In addition, for example, whether there is unevenness on the surface of a portion such as the substrate 506 end which is not encapsulated by the molding resin 415, can also be analyzed by using a scanning electron microscope to analyze the surface. confirm. The embodiment suitable for the present invention has been described above. However, the present invention is not limited to the above-mentioned embodiments, and those skilled in the art can also carry out variations of the above-mentioned embodiments within the scope of the present invention. For example, the above-mentioned embodiment will be described. However, the present invention can also be applied to a mold other than a semiconductor module related to a semiconductor module, and a circuit is provided for the pair. However, for example, in addition to the above-mentioned implementation The form of the solder resist layer 408 of the form 407 will be described 315641 23 200426958. The resistance of the conductor " lead frame and other lines 407 are placed on the solder layer. In addition, in the above-mentioned embodiment, the description will be made with respect to a form in which the anti-rod layer is used as a base material, but a base material other than an insulating base material may be used. EXAMPLES Example 1 After a dry film resist (trade name PDF300, manufactured by Nippon Steel Chemical Co., Ltd.) was pasted on the surface of a copper town, the anti-residue film was patterned to expose the copper wire surface- Part. In this state, argon plasma treatment was performed on the entire surface including the thorium exposed surface and the dry resist film surface. Among them, two types of samples were produced by changing the oxygen concentration in the plasma gas. Bias voltage: Plasma gas is not applied. Sample 1 Argon 1 〇seem, oxygen 〇sccm Sample 2 Argon 10 seem, oxygen 10 Sccm RF Power (w): 500 Pressure (Pa): 20 Processing time (sec): 20 ^ The surface of the dry resist film before and after plasma irradiation was observed with a scanning electron microscope. The results are shown in Figure 丨 丨, Figure 12, and Figure 3. Figure Π shows Sample 1, Figure 12 shows Sample 2, and Figure 13 shows the appearance without plasma treatment. It can be clearly understood that a plurality of minute protrusions can be formed on the resin surface by plasma irradiation. The average diameter and density of the microprotrusions were measured using daylight image data obtained by observing the festival with a scanning electron microscope. The density is determined by measuring the number of microprotrusions (, line density) on a straight line with a length of 1 μm, and multiplying the number by two. The results are shown in the following table. Sample 1 has an average diameter of 4 nm and a number density of 1.2 × 103 samples / μm 2 Sample 2 has an average diameter of 4 nm and a number density of 1.6 × 103 samples / μm 2 Next, X-ray photoelectron spectroscopy analysis is performed on the samples 1 and 2. The results are shown in FIG. 14. In the figure, in addition to Samples 2 and 2, the curve before argon plasma treatment is also shown as a reference. It can be known that through Denso Japan and radio, while the intensity of the C = 0 combination of 286 eV increases, the intensity of the 284.5 eW-0 combination or the combination of c-county decreases. When the intensity of the C—0 or c—N combination of 284.5 eV is taken as X, and the intensity of the 〇 e combination of 286 eV is taken as y, y / about the module of this embodiment In the numerical value of x, the sample] and 2 are both about 0.44. ^ Continued, measuring contact angles for the samples 1 and 2. After pure water was dropped on the surface of the resist film, the shape of the water droplet was observed with a magnifying glass and the contact angle thereof was measured. The contact angle was measured 2 days after the sample was made. The obtained contact angle values are shown below. From this, it can be seen that Samples 1 and 2 using a dry resist film (trade name pdf 300, 315641 25 200426958 manufactured by Shinsei Iron Chemical Co., Ltd.) exhibited satisfactory performance at a contact angle of 30 to 70 degrees. . Sample 1 52.0 degrees Sample 2 53.6 degrees In the manufacturing process stated in the first embodiment, the same molding and plasma processing processes as in the above-mentioned samples 1 and 2 were applied to manufacture semiconductor modules. This semiconductor module uses dry resist films of samples 1 and 2 as a solder resist, and a semiconductor element is mounted on the surface. After the evaluation of the semiconductor module, in addition to the excellent heat cycle performance, the pressure cooker test also has good results. Example 2 After a dry resist film (trade name AUS402, manufactured by Taiyo Ink Co., Ltd.) was attached to the surface of a copper foil, the resist film was patterned to expose a part of the surface of the copper foil. In this state, the entire surface of the copper-containing foil exposed surface and the epoxy-resist-based resist film surface was subjected to argon plasma treatment. In addition, here, the above-mentioned dry resist film (trade name: AUS402, manufactured by Taiyo Ink Co., Ltd.) is manufactured by using a photo-curing and thermosetting resin containing a polyfunctional oxycyclobutane compound or an epoxy compound, and There are crater-like recesses on the surface. Bias voltage: no applied plasma gas: argon 1 〇seem, oxygen 0 seem RF power (W): 500 pressure (Pa): 20 26 315641 200426958 processing time ·· Sample 3: 20〇ec〇 Sample 4: 60 (see The surface of the dry resist film before and after the plasma irradiation was observed with a scanning electron microscope. The results are shown in Figure 16, Figure Π, and Figure 18. Figure 16 shows Sample 3, Figure 17 shows Sample 4, and Figure 8 shows the appearance without plasma treatment. It can be clearly understood that a plurality of tiny protrusions can rise on the surface of the tree moon by plasma irradiation. The image data obtained by observation with a scanning electron microscope was used to measure the average diameter and density of the microprojections. The density is determined by measuring the number of microprotrusions (linear density) on a straight line with a length of 1 μm, and multiplying the number by two. The results are shown below. ° Sample 3 with an average diameter of 4 nm and a number density of 2 × 103 cells / μm 2 Sample 4 with an average diameter of 4 nm and a number density of 2 × 103 cells / μm 2 Next, the above samples were analyzed by χ-ray photoelectron spectroscopy. The results are shown in Figure 19. In the figure, the curve of Sample 4 is shown using the curve before argon plasma treatment as a reference. It can be known that by plasma irradiation, while the intensity associated with the 〇2 bond increases, the intensity associated with the 284.5-c 315641 27 200426958 bond or C—N bond decreases. Let the intensity of the C-0 combination or C-N combination of 284 5 eV be regarded as χ, and the intensity of the combination of c = 0 of 286 be regarded as ㈣. The y / The value of x is approximately 0.4. The contact angle of the above samples was measured. After pure water was dropped on the surface of the resist film, the shape of the water droplet was observed with a magnifying glass and its contact angle was measured. The measurement of the contact angle was performed 2 days after the sample was made. The obtained values are shown below. Sample 380 degrees Sample 4 105 degrees In the process stated in the first embodiment, a mold and plasma processing process similar to the above is applied to manufacture a semiconductor module. The semiconductor module uses the dry resist film of the sample as a solder resist, and a semiconductor element is laminated on the surface. After the evaluation of this semiconductor module, in addition to the excellent thermal stability, it also has good results in the pressure cooker test. [Simplified illustration of the figure] Figure 1 is an explanatory diagram of the BGA structure. Ang 2 is an explanatory diagram of the ISB (registered trademark) structure. Figures 3 (A) and 3 (B) are explanatory diagrams of the manufacturing and production processes of BGA and ISB (registered trademark). Clothing & Figures 4 (a) and 4 (b) are illustrations of the structure of the related semiconductor module. Figures 0 (A) to 5 (C) are the manufacturing methods of related semiconductor modules. 315641 28 200426958 Illustrating. Figures 6 (A) and 6 (B) are explanatory diagrams of a manufacturing method of a related semiconductor module. Figures 7 (A) and 7 (B) are explanatory diagrams of a manufacturing method of a related semiconductor module. FIG. 8 is an explanatory diagram of a manufacturing method of a related semiconductor module. Brother 9 (A) and 9 (B) are explanatory diagrams of a method for manufacturing a related semiconductor module. / Figures 10 (a) and 10 (b) are diagrams illustrating the structure of a related semiconductor module. Fig. 11 is a graph showing the results of observing the surface of the anti-money film after the electropolymerization treatment with a cat-type electron microscope. > FIG. 12 is a graph showing the results of observing the surface of the anti-button film after the plasma treatment with a scanning electron microscope. Anti-Member 1 2 A representation of the results of observing the anti-M surname M surface after treatment with a cat-type electron microscope. Fig. 14 is a graph showing the results of the spectroscopic analysis of the surface of the anti-button film after the electrolysis treatment. = The figure is an explanatory diagram of the structure of the related semiconductor module. Representation of anti-repellent surface materials / Figure 17 after plasma treatment of Chichichi-chan is a representation of the results of anti-repellent surface scanning. The 18th figure after the phase mirror material treatment is a result of observing the plasma treated surface with a cat-type electron microscope 315641 29 200426958. Fig. 19 is a graph showing the results of X-ray photoelectron spectroscopy analysis of the surface of the resist film after plasma treatment. [Description of Symbols of Main Components] 100 Ball Gate Array Package (BGA) LSI chip 104 metal wire epoxy substrate 108 next layer 010 packaging resin 112 fresh solder ball 〇2 LSI bare chip 202 Tr bare chip 203 chip CR 204 gold wire 205 copper pattern 206 conductive paste 207 resin package 208 fresh tin ball 400 metal town 401 photoresist 402 conductive coating film 404 through hole 405 interlayer insulation film 407 line 408 anti-frying layer 410a 4 1 0 b component 412 gold wire 415 molded resin 420 solder ball 421 contact hole 435 dummy line 502 component 506 substrate 510 then material 315641 30

Claims (1)

200426958 十、申請專利範圍： 1·:種半導體模組’包含設置有導體電路的絕緣基材、於 2緣基材上形成的半導體元件、連接該絕緣基材以及 忒半導體70件的絕緣體，其特徵為： 突起^該絕緣基材之連接該絕緣體的表面上，形成微小 2m專利範圍第1項的半導體模組，其中，該絕緣想 係為费封該半導體元件之封裝樹脂。 3·範圍第1項的半·導體模組，其中，該絕緣體 4 ΓίίΓ體元件以及該絕緣基材的接著材料。 .=1範圍第卜2或3項的半導體模組，其中， 基材之連接該絕緣體的表面上，形成 山口狀凹部。 5.如申請專·圍第4項的半導體模組， 狀凹部的直徑係為〇.1μηι以上、Um以下/ •::=i範圍第卜2或3項的半導體模組，其中， 起亥則、犬起群含有平均直Wnm^〇nm之複數個突 乾圍第1、2或3項的半導體模組，其中， 數個突起。 。叉為0.5X10 μιη·2以上之複 模組’包含設置有導雜電路的絕緣基材、於 形成的半導趙元件、連接該絕緣基材以及 牛¥肢疋件的絕緣體，其特徵為： 315641 31 200426958 在該絕緣基材之連接該絕緣體之表面附近的X線 光包刀子为光光瑨中，當將於束缚能284.5 eV之檢測強 度當作X，將於束縛能286 eV之檢測強度當作）^時，y/x 值為0.4以上。 9·種半‘ β豆杈組，包含設置有導體電路的絕緣基材、於 及絕緣基材上形成的半導體元件、連接該絕緣基材以及 該半導體元件的絕緣體，其特徵為·· 在露出該絕緣基材之連接該絕緣體之區域時之對 純水的接觸角係為3〇度至12〇度。 10·-種半導體模組，包含設置有導體電路的絕緣基材、於 該絕緣基材上形成的半導體元件、連接該絕緣基材以及 。亥半導體元件的絕緣體，其特徵為： —該絕緣基材係為含有多官能氧雜環丁烧化合物或 環氧化合物之光硬化性•光熱化性樹脂。 11. 如申請專利範圍第U 3、8至1G項中之任—項的半導 體模組，其中，該半導體S件係為裸晶片該絕緣體係 由密封該裸晶片之封裝樹脂形成。 12. -種模組，包含基材、於該基材上形成的元件、連接該 基材以及該元件的絕緣體，其特徵為： 在該基材之連接該絕緣體的表面上，形成微小突起 群。 A如申請專利範圍第12項的模組，其中，在該基材之連 接遠絕緣體的表面上，形成複數之火山口狀凹部。 14.如申請專利範圍第12項或第⑴員的模組，其中，該微 315641 32 小突起群含有平均直彳⑤ κ 一種半導體模組的製二;^，"之複數個突起。 第 1至 ΛΑ 、 1 3項中之任一項的半導辦;1¾ h 、方法，包含對設置有導體電 、、，， 電聚處理的步驟，在該㈣心、，、巴，·束基材的表面進行 連接該半導體元件之絕缘^上形成半導體元件以及 .^ 象肢的步驟，其特徵為： 基材而進nr 1體之㈣氣體，且*施加偏壓於該 巷材而進仃該電漿處理。 、攻 16·一種模組的製造方法，# η 係為製造如申請專利範圍第12 貝Α弟13項的模組的方法， 電f卢a /、匕含對基材的表面進行 之锅鰺胁^ , 柯上形成兀件以及連接該元件 、、、邑、、彖體的步驟，其特徵為·· 基材：二3 # <M生風體之電漿氣體，且不施加偏壓於該 丞材而進行該電漿處理。 315641 33200426958 10. Scope of patent application: 1. A semiconductor module including an insulating substrate provided with a conductor circuit, a semiconductor element formed on a two-edge substrate, and an insulator connecting the insulating substrate and 70 semiconductors. It is characterized in that: a protrusion is formed on the surface of the insulating base material connected to the insulator to form a semiconductor module of the minute 2m patent scope, wherein the insulation is intended to be a packaging resin that seals the semiconductor element. 3. The semi-conductor module according to the first item, wherein the insulator 4 is a body element and a bonding material of the insulating base material. . = 1 The semiconductor module according to item 2 or 3 of the range, wherein the surface of the base material connected to the insulator forms a mountain-like recess. 5. If applying for the semiconductor module of the fourth item, the diameter of the concave portion is greater than or equal to 0.1 μm and less than Um / • :: == i. The semiconductor module according to item 2 or 3, wherein, Then, the canine group includes a plurality of semiconductor modules with an average straight Wnm ^ 0nm of item No. 1, 2 or 3, among which there are several protrusions. . The complex module with a fork of 0.5X10 μιη · 2 or more includes an insulating substrate provided with a miscellaneous circuit, a semiconducting element formed thereon, and an insulator connecting the insulating substrate and a limb member, and is characterized by: 315641 31 200426958 In the case where the X-ray package knife near the surface of the insulating substrate connected to the insulator is a light beam, when the detection intensity of the binding energy of 284.5 eV is regarded as X, the detection intensity of the binding energy is 286 eV As) ^, the y / x value is 0.4 or more. 9 · Semi- 'β bean branch group, which includes an insulating substrate provided with a conductor circuit, a semiconductor element formed on the insulating substrate, and an insulator connecting the insulating substrate and the semiconductor element, and is characterized by being exposed The contact angle of the insulating substrate to the pure water when the region connecting the insulator is 30 ° to 120 °. A 10 · -semiconductor module comprising an insulating substrate provided with a conductor circuit, a semiconductor element formed on the insulating substrate, a connection to the insulating substrate, and. An insulator for a semiconductor device is characterized in that:-the insulating base material is a photo-curable / photothermable resin containing a polyfunctional oxetane compound or an epoxy compound. 11. For the semiconductor module of any one of items U 3, 8 to 1G in the scope of application for a patent, wherein the semiconductor S-piece is a bare wafer, the insulation system is formed by a sealing resin sealing the bare wafer. 12. A module comprising a base material, an element formed on the base material, and an insulator connected to the base material and the element, characterized in that a micro-protrusion group is formed on a surface of the base material connected to the insulator. . A The module according to item 12 of the patent application scope, wherein a plurality of crater-shaped recesses are formed on the surface of the remote insulator connected to the substrate. 14. If the module of the scope of patent application No. 12 or the first member, wherein the micro 315641 32 small protrusion group contains an average straight line ⑤ κ a semiconductor module system two; ^, " a plurality of protrusions. The semi-conductor of any one of items 1 to ΛΑ, 13; 1¾ h, the method, including the step of conducting the electric ,,, and electrocondensation processing on the conductor, in the center The step of forming a semiconductor element and an elephant limb on the surface of the substrate to connect the semiconductor element with insulation is characterized in that: the substrate enters the nr 1 body of radon gas, and * applies a bias to the lane material to enter仃 The plasma treatment. 16. A method for manufacturing a module, # η is a method for manufacturing a module such as the 13th item in the scope of the patent application, and the method includes a method for performing a process on the surface of a substrate. Threat ^, the step of forming an element on Ko and connecting the element ,,, yup, and corpuscle are characterized by a base material: two 3 # < M plasma source gas without applying a bias voltage The plasma treatment is performed on the base material. 315641 33
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