TW200832661A - Semiconductor module and method for making same - Google Patents

Semiconductor module and method for making same Download PDF

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Publication number
TW200832661A
TW200832661A TW097108613A TW97108613A TW200832661A TW 200832661 A TW200832661 A TW 200832661A TW 097108613 A TW097108613 A TW 097108613A TW 97108613 A TW97108613 A TW 97108613A TW 200832661 A TW200832661 A TW 200832661A
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substrate
resin
semiconductor module
semiconductor
layer
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TW097108613A
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Chinese (zh)
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TWI326910B (en
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Ryosuke Usui
Hideki Mizuhara
Takeshi Nakamura
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Sanyo Electric Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

This invention provides a semiconductor module to enhance the adhesion between an insulation substrate and an insulation body formed on the insulation substrate, the insulation body being an encapsulating resin or an adhesive member of the semiconductor element. A solder resist layer (408) is formed on the uppermost layer of a laminate of a plurality of layers including wiring layers of interlayer insulation film (405) and a wiring (407) of copper. Elements (410a) and (410b) are formed on a surface of the solder resist layer (408). The elements (410a) and (410b) are molded with a molding resin. The surface of the solder resist layer (408) is modified by a plasma treatment with selected specific condition, so that the surface of the solder resist layer (408) has such characteristics that, when a detected strength of an X-ray photoelectron spectrograph with a binding energy of 284.5eV is designated by x, and a binding energy of 286eV is designated by y, the value of y/x is higher than 0.4.

Description

200832661 u 九、發明說明： v【發明所屬之技術領域】 本發明係有關格载半導體7〇件等並接合於配線基板等 之半導體模組及其製造方法。 【先前技術】 當行動電話、個人數位助理（personal digital assistant, PDA)、數位攝影機(digital video camera，DVC)、數位相機 (digital still camera, DSC)等之攜帶式電子機器加速進行 w高機能化時，為了使這樣的產品在市場上可被接受，還必 須進行小型·輕量化。而為了實現這樣的需求而必須尋求 南積體化的系統大型積體（large scale integration，LSI)技 術。另一方面，對這些電子機器而言，也需要有更加好用 而便利的性能，而必須對在機器上使用的LSI要求高機能 化、高性能化。為此，伴隨著LSI晶片之高積體化之輸入/ 輸出點數的增加，使封裝本身之小型化的要求也增強，為 _ 了使這些需求可並存，而強烈地要求對適合於高密度半導 體零件之基板組裝的半導體封裝技術進行開發。為了配合 這樣的要求，而進行稱為晶片級封裝（Chip Size Package, CSP)之封裝技術的各種開發。 目前已知有球閘陣歹彳封裝（Ball Grid Array, BGA)可作 為如此的封裝例。BGA係在封裝用基板上上安裝半導體元 件，將其以樹脂模製之後，在對向侧之表面形成作為外部 接點之區域狀銲錫球。在BGA中，因為以面狀形成組裝區 域，使封裝能比較容易小型化。此外，因為在電路基板侧 5 315641D01 200832661 v上也沒有配合狭小間距的必要，而不需要高精確度的組裝 ，技術，所以使用BGA的話，即使封裝成本在多少較高的情 況下’總組裝成本仍可能降低。 _ 第1圖係表示一般之BGA的概要結構圖。bgai〇〇具有 在玻璃㈣（Glass-Epoxy)基板1〇6上，彡過接著層1〇8搭載 LSI晶片102的構造。其中，藉由封裝樹脂11〇對lsi晶片 進行模製（molding)。而將LSI晶片102以及 間以金屬㈣4電性連接。在玻璃環氧基板 面，銲錫球112以陣列狀排列。再透過該銲錫球ιΐ2，將 BGA100安裝於印刷線路基板。 在專利文獻1中記載有其他CSP的例子。在該公報記載 中，並揭露搭載高頻用LSI的系統級封裝件沁 PaCkage)。該封裝件係於基底（base)基板上形成多層線路構 造，而在該基板上首先形成高頻用LSI之半導體元件。多 層線路構造係為核心（core)基板以及附加樹脂之銅箔等之 春疊層構造。 但是，由這些習知的CSP卻難以在攜帶式電子機器等 方面實現如目前希望之水準的小型化、薄型化、輕量化。 f係因為習知的csp具有支樓元件之基板的關係。由於支 撐基板的存在，使封裝全體變厚，而使小型化、薄型化、 輕量化有其界限。此外，散熱性的改善也有一定的界限。 日本國專利2002-94247號公報 日本國專利2002-110717號公報 【發明内容】 315641D01 6 200832661 登明欲解決的 一在以上所述之BGA等封裝件中，封裝件之支撐基板和 ^封元件之封裝樹脂間之充分緊密結合性十分重要，特別 疋，，如後述之ISB之半導體模組因為沒有支樓基板，因此 針對界面緊密結合性的要求十分嚴格。 、曾本發明係有鐘於上述問題所開發者，其目的為，在半 T體模組等模組件中’將絕緣基材和形成於絕緣基材上的 、”巴緣體’例如半導體元件之封裝樹脂或接 罾結合性提高。 π Ί^^ 本毛月之+¥體杈組所具有的特徵為：包含 電路的絕緣基材，形成於η置 河办成m緣基材上的半導體元件" 連接〇絕緣基材以及該半導體元件而設立的p. 群 縣材之連接朗緣體的表面上，形成微小以 晶片1 在本發明中，半導體元件係包 #-^t^^^(chipconductor^;^ 开多成模組因為在絕緣基材之連接絕緣體的表面 形成則、大起群，使得於絕緣基 矛面- 結合性變得良好。 e緣體之界面的緊《 此外’絕緣體可以是密封半導體元件 可以是設置於半導體元件和 封衣枒如，4 LL Μ 緣基材之間的接著;fef袓 ’在絕緣基材之連接絕緣體的表上 複數之火山口㈣叫狀凹部，而火山口狀凹^可形或 在〇·1 um以上、1 um以下。 #之直徑也可 31564ID01 7 200832661 該半導體模組，因為除了在絕緣基材之連接絕緣體的 、表面上形成微小突起群外，並形成直徑〇1 _以上、i _ 以下之複數之火山口狀凹部，使絕緣基材和絕緣體之界面 的緊密結合性變得良好。 微小突起群宜含有平均直徑1腿至20 nm的複數之突 起。而且，其數量密度宜為0·5χ1〇3 μπΓ2以上，更宜為〇·8 ΧΙΟ μπι2至2·Οχ1〇3 特別是，最宜為16_3〆至 _ μτη藉此，可明顯改善於絕緣基材和絕緣體之界 面的緊密結合性。 有關本發明之另一半導體模組之特徵為：包含設置有 導體電路的絕緣基材，形a於該絕緣基材上的半導體元 件，以及連接該絕緣基材以及該半導體元件的絕緣體；以 及^絕緣基材之連接該絕緣體的表面中，該絕緣基材係 =衰氧树月曰材料構成’而於該表面之附近的X線光電子分 光譜（spectrum)中，當將束缚能_284 5…的檢測強度當作 • X ’將束縛強度·286 eV的檢測強度當作㈣時候，y/x的數 值為0·4以上。[Technical Field] The present invention relates to a semiconductor module in which a semiconductor semiconductor device or the like is bonded to a wiring substrate or the like and a method of manufacturing the same. [Prior Art] Accelerating the high-performance of mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital video cameras (DVCs), and digital still cameras (DSCs) In order to make such products acceptable in the market, it is also necessary to reduce the size and weight. In order to realize such a demand, it is necessary to seek a system of large scale integration (LSI) technology. On the other hand, for these electronic devices, it is also required to have better and more convenient performance, and it is necessary to have high performance and high performance for the LSI used in the machine. For this reason, with the increase in the number of input/output points of the high integration of LSI chips, the demand for miniaturization of the package itself is also enhanced, so that these demands can coexist, and it is strongly required to be suitable for high density. Semiconductor package technology for substrate assembly of semiconductor parts was developed. In order to meet such requirements, various developments of a package technology called Chip Size Package (CSP) have been carried out. A Ball Grid Array (BGA) is known as such a package. In the BGA, a semiconductor element is mounted on a substrate for packaging, and after molding with a resin, a region-shaped solder ball as an external contact is formed on the surface on the opposite side. In the BGA, since the assembly region is formed in a planar shape, the package can be easily miniaturized. In addition, since there is no need to fit a small pitch on the circuit substrate side 5 315641D01 200832661 v without high-precision assembly and technology, if the BGA is used, even if the package cost is high, the total assembly cost is high. It may still be lower. _ Figure 1 shows a schematic structure diagram of a general BGA. The bgai〇〇 has a structure in which the LSI wafer 102 is mounted on the glass-epoxy substrate 1〇6 and the subsequent layer 1〇8. Here, the lsi wafer was molded by encapsulating the resin 11?. The LSI wafer 102 and the metal (four) 4 are electrically connected to each other. On the surface of the glass epoxy substrate, the solder balls 112 are arranged in an array. The BGA 100 is mounted on the printed wiring board through the solder ball ι 2 . Patent Document 1 describes an example of another CSP. In the description of this publication, a system-in-package 搭载 PaCkage) equipped with a high-frequency LSI is disclosed. The package is formed on a base substrate to form a multilayer wiring structure, and a semiconductor element of a high frequency LSI is first formed on the substrate. The multi-layer line structure is a spring laminated structure of a core substrate and a copper foil to which a resin is added. However, these conventional CSPs are difficult to achieve miniaturization, thinning, and weight reduction as currently desired in portable electronic devices and the like. f is because the conventional csp has the relationship of the substrate of the branch building element. Due to the presence of the supporting substrate, the entire package is made thick, and there is a limit to miniaturization, thinning, and weight reduction. In addition, there is a certain limit to the improvement of heat dissipation. Japanese Patent No. 2002-94247 (Japanese Patent No. 2002-110717) [Draft of the Invention] 315641D01 6 200832661 In a package such as the BGA described above, the support substrate and the sealing member of the package are claimed. It is important to have sufficient tight bonding between the encapsulating resins. In particular, since the semiconductor module of the ISB described later does not have a support substrate, the requirements for tight interface bonding are very strict. The invention has been developed by the above-mentioned problem, and the purpose thereof is to "insulate the insulating substrate and the "barrier" formed on the insulating substrate, such as a semiconductor, in a mold assembly such as a semi-T body module. The encapsulation resin or joint bond of the component is improved. π Ί^^ The characteristics of the 毛 之 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含The semiconductor element " is connected to the insulating substrate and the semiconductor element is formed on the surface of the connecting edge of the prism body to form a micro wafer 1 in the present invention, the semiconductor component package #-^t^^ ^(chipconductor^;^ The multi-module is formed because the surface of the insulating substrate is formed on the surface of the insulating substrate, so that the insulating layer is well-bonded. The bonding of the e-body is tight. The insulator may be a sealed semiconductor element which may be disposed between the semiconductor element and the sealing member, such as a 4 LL rim substrate; the fef 袓 'the crater on the surface of the insulating substrate of the insulating substrate (four) Concave, while crater-shaped concave ^ can be shaped or in 〇· 1 um or more and 1 um or less. The diameter of # 316 can also be 31564ID01 7 200832661 The semiconductor module is formed in a diameter 〇1 _ or more, i _ except for the formation of minute protrusion groups on the surface of the insulating substrate. The following plurality of crater-like recesses provide a good bond between the insulating substrate and the insulator. The fine protrusion group preferably has a plurality of protrusions having an average diameter of 1 leg to 20 nm. Moreover, the number density is preferably 0. ·5χ1〇3 μπΓ2 or more, more preferably 〇·8 ΧΙΟ μπι2 to 2·Οχ1〇3 In particular, it is preferably 16_3〆 to _μτη, which can significantly improve the tight bond between the insulating substrate and the insulator. Another semiconductor module according to the present invention is characterized by comprising: an insulating substrate provided with a conductor circuit, a semiconductor element formed on the insulating substrate, and an insulator connecting the insulating substrate and the semiconductor element; ^In the surface of the insulating substrate to which the insulating substrate is bonded, the insulating substrate is composed of 'attenuated oxidized tree 曰 material' and is in the X-ray photoelectron spectroscopy near the surface When the detection intensity of the binding energy _284 5... is taken as • X ′, the detection intensity of the binding strength·286 eV is regarded as (4), and the value of y/x is 0.4 or more.

於此，束缚能-286 eV屬於結構C=0結合的Cls電子 =一方面，束缚能_284·5以屬於結構C—Ο結合或C_NJ —、 龟子這些比值在滿足上述條件時，可明顯改善2 絕緣基材和絕緣體之界面的緊密結合性。還有，將^ 數值的上限設為例如3以下。 、有關本發明之再一半導體模組之特徵為：包含設置妄 體包路的絕緣基材，形成於該絕緣基材上的半導體元件 315641D01 8 200832661 ‘二材以及該半導體元件的絕緣體；以及該 觸角為30度至120度。 纟路出¥，其對純水之接 此接觸角的樹脂材料，可明顯地改善對 絶緣基材和絕緣體之界面的緊密結合性。 的預Ϊ = 2體模組，例如，可藉由在沒有施加偏峰㈣ 、、疋釦件下進仃電漿（piasma)處理而得到。 有關本發明之又一半導體模組之特徵為.肖人_ ·:體電路的的絕緣基材，形成於該絕緣4上 1材:=.?緣基材和半導體元件的絶緣體二 基材係為含有多官能氧環丁燒（oxetane)化合物或環 化合物的光硬化性.熱硬化性樹脂。 曰 該半導體模組的絕緣基材，因為具有含 丁燒化合物或環氧樹脂化合物的光硬化性.執硬月匕= ，，而可進行型樣化⑽terning)，同時，可明顯地改盖= 馨絶緣基材和絕緣體的界面的緊密結合性。 ' ° 有關本發明之又一半導體模組的特徵為：包含 镫，以及—在基材之連接絕緣體的表面上，形成微小突起群。 、該模組因為在基材之連接絕緣體的表面上形成微小突 =群，使得於基材和絕緣體的界面之緊密結合性變得2 315641DO 1 9 200832661 此外，在基材之連結絕緣體的表面上，也可以形成複 數的火山口狀凹部，而該微小突起群也可以含有平均直^ 1 nm至20 nm之複數個突起。 二 再者，本發明之半導體模組的製造方法係為製作上述 之半導體模組的方法，其特徵為：包含對設立有導體電路 的絕緣基材的表面進行電漿處理的步驟，以及在該絕^基 材上，形成半導體元件以及連接該半導體元件之絕緣體的 •，驟’以及在不對該基板施加偏以bias)下，用含有惰性 氣體（惰性氣體）之電漿氣體進行該電漿處理。 藉由進行如上述之電漿處理，而能安定地得到對絕緣 基材和絕緣體之界面具有卓越的緊密結合性之半導體模 組。還有，所謂「偏壓」係不包括基板本身的偏壓。、 再者，本發明之模組的製造方法係為製作上述之模愈 的方法，其特徵為：包含對基材之表面進行電漿處理的步 驟’以及在基材上形成元件和連接元件之絕緣體的步驟； 以及在不對該基板施加偏，料㈣體 體進行該電漿處理。 电水碗 ^2進行如上述之電漿處理，而能安定地得到對基材 :絶緣面具有卓越的緊密結合性之半導體模組。還 所。月偏壓」係不包括基板本身的偏壓。 在本發明中’在半導體元件為裸晶片（b_ 緣體係由密封裸晶片之封裝樹脂構成時，特別具有效果、。 在知用相關結構的情況下，以薄型化而能實現輕量之封裝 315641D01 10 200832661 件之同時，往往於絕緣基材和 良問題，然而如果栌栌太…曰 曰之間有緊密結合不 本發明㈣卩可有效料這樣的問題。 材表面u 明導體1路’係為形成於基材内部或美 材表面，而由銅線路等構成的 次土 支撐半導體元株LV R ~〇所明絕緣基材，係為 而所謂絕缘體俜為f，、迷接之導體電路的絕緣性基材， 元件進裝 件之間的絕緣層或接=材戈等配置於絕緣基材和半導體元 緣其t·果根據本發明，在半導體模組等模組方面，可將絕 ，基材、形成於崎基材上的絕_、錢例如半導體元 件之封裳樹脂間白勺緊密結合性提冑。 【實施方式】 下將㈣有關本發明之實施形態，然而在進入說明 之前，先對在實施形態中採用的ISB構造相關進行說明。 • ^Integrated System in Board ;註冊商標），是根據本申 請^所開發之原創封裝件。ISB係以半導體裸晶片為中心 之毛子包路封裝件，而不使用到含有以銅製作之線路型樣 亚用來支撐電路零件的核心（基材）的原創無核心系統級封 裝件（coreless system inpackage)。 第2圖係表示iSB之一範例的概要結構圖。於此，為了 谷易知道ISB的全體構造，而僅顯示單一線路層，然而實 際上係由複數之線路層形成層疊構造。在該ISB中，LSI 裸晶片201、Tr裸晶片202以及晶片cr 203形成藉由以銅型 11 315641D01 200832661 “ 5構成之線路進行接線的構造 藉由銲接（bonding)今wn 稞b曰片201中，Here, the binding energy -286 eV belongs to the structure C=0 combined Cls electrons = on the one hand, the binding energy _284·5 belongs to the structure C-Ο binding or C_NJ —, the ratio of the turtle is obvious when the above conditions are satisfied. Improves the tight bond between the 2 insulating substrate and the interface of the insulator. Further, the upper limit of the value of ^ is set to, for example, 3 or less. Further, a semiconductor module according to the present invention is characterized by comprising: an insulating substrate provided with a body package, a semiconductor component 315641D01 8 200832661 formed on the insulating substrate, and an insulator of the semiconductor component; The antennae are 30 degrees to 120 degrees.纟路出¥, its resin material for the contact angle of pure water can significantly improve the tight bond of the interface between the insulating substrate and the insulator. The pre-twist = 2 body module can be obtained, for example, by a piasma treatment without applying a bias (four) and a snap fastener. Another semiconductor module according to the present invention is characterized in that: an insulating substrate of a body circuit is formed on the insulating material: a material of the substrate and an insulator of the semiconductor device It is a photocurable thermosetting resin containing a polyfunctional oxygen oxetane compound or a ring compound.绝缘 The insulating substrate of the semiconductor module has a photohardenability containing a butyl compound or an epoxy resin compound, and can be subjected to patterning (10) terning), and at the same time, it can be obviously modified. The tight bond between the interface of the sin-insulated substrate and the insulator. A further semiconductor module according to the present invention is characterized in that it comprises ruthenium, and - on the surface of the connection insulator of the substrate, a group of minute protrusions is formed. The module is formed by a microbump on the surface of the connecting insulator of the substrate, so that the tight bond between the substrate and the insulator becomes 2 315641 DO 1 9 200832661. Further, on the surface of the bonded insulator of the substrate A plurality of crater-like recesses may also be formed, and the micro-protrusion group may also contain a plurality of protrusions having an average diameter of from 1 nm to 20 nm. Further, the method of fabricating the semiconductor module of the present invention is a method of fabricating the above-described semiconductor module, comprising: a step of performing a plasma treatment on a surface of an insulating substrate on which a conductor circuit is formed, and On the substrate, the semiconductor element and the insulator connecting the semiconductor element are formed, and the plasma treatment is performed with a plasma gas containing an inert gas (inert gas) without biasing the substrate . By performing the plasma treatment as described above, it is possible to stably obtain a semiconductor module having excellent close adhesion to the interface between the insulating substrate and the insulator. Further, the "bias" means that the bias voltage of the substrate itself is not included. Furthermore, the method for manufacturing the module of the present invention is a method for producing the above-mentioned mold, which comprises the steps of: performing a plasma treatment on the surface of the substrate and forming the element and the connecting member on the substrate. a step of an insulator; and performing a plasma treatment on the substrate without applying a bias to the substrate. The electric water bowl ^2 is subjected to the plasma treatment as described above, and the semiconductor module having excellent excellent adhesion to the substrate: the insulating surface can be stably obtained. Also. The monthly bias does not include the bias of the substrate itself. In the present invention, when the semiconductor element is a bare wafer (the b-edge system is composed of a sealing resin for sealing the bare wafer, it is particularly effective. In the case where the related structure is known, the lightweight package can be realized by thinning 315641D01 10 200832661 At the same time, it is often a problem with insulating substrates and good problems. However, if there is a close combination between 栌栌 too... 不 不 发明 四 四 四 四 四 四 四 四 卩 卩 卩 卩 卩 。 。 。 。 明 明 明 明 明 明 明 明In the interior of the substrate or on the surface of the US material, the secondary soil supporting the semiconductor element strain LV R ~ 构成, which is composed of a copper wire or the like, is the insulating substrate of the so-called insulator f, f, and the insulation of the conductor circuit of the splicing The substrate, the insulating layer or the material between the component inlets and the like are disposed on the insulating substrate and the semiconductor element. According to the present invention, in the module of the semiconductor module, the base can be The material is formed on the substrate, and the adhesion between the resin and the sealing material such as the semiconductor element is improved. [Embodiment] Next, (4) the embodiment of the present invention is described, however, before entering the description, For ISB structure employed in the relevant embodiment will be described • ^ Integrated System in Board;. Registered trademark), is to ask the original package developed ^ according to the present application. ISB is a hair-encapsulated package centered on a semiconductor bare chip, without using an original coreless system-level package (coreless system) containing a core (substrate) for supporting circuit parts made of copper. Inpackage). Figure 2 is a schematic block diagram showing an example of an iSB. Here, in order to know the entire structure of the ISB, only a single circuit layer is displayed. However, in actuality, a plurality of circuit layers are formed into a laminated structure. In the ISB, the LSI bare chip 201, the Tr bare wafer 202, and the wafer cr 203 are formed by bonding a wiring formed by a copper type 11 315641D01 200832661 "5" by bonding in the current wnb ,

裸晶DOW τ 線 通引出電極和線路。在LSI 日日 、下方，設置有導電膏206,並透過該導雷古 將ISB安裝於印刷線 1尥这蛉電^ 日m A 線路基板上。而1SB全體則藉由以環氧樹 月曰4構成的樹脂封裝體207進行密封。 士 .若藉由此封裝，則能得到以下的優點。 (i) 因為能以益核心；鱼；如壯The bare DOW τ line leads to the electrodes and lines. On the LSI day and below, a conductive paste 206 is disposed, and the ISB is mounted on the printed circuit 1 through the lead wire. On the other hand, the entire 1SB is sealed by a resin package 207 made of epoxy tree. If you package by this, you can get the following advantages. (i) because it can benefit the core; fish;

!的小型.薄型化進仃、、且衣’而可實現電晶體、IC、LSI (iim t成及料由電晶體到系統现，還有晶片形式 (SI;:為以及電阻，而能實現高度化系統級封裝件! Small size, thinner, and woven, and can realize transistors, ICs, LSIs (iim t and materials from the transistor to the system, and wafer form (SI;: and resistance, can be realized High-grade system-level package

System in Package)。 (叫因為可組合現有的半導體元件，使系統lsi在短 即可開發出。 1 (IV)由於將半導體裸晶片直接裝在正下方的銅材上，而能 得到良好的散熱性。 b _(v)因為沒有電路線路係銅材之核心材，而具有低介電係 數率的電路線路，在快速資料傳送以及高頻電路上可 發揮優越的特性。 (0因為電極係為在封裝件内部的埋人構造，故可抑制電 • •極材料之微粒污染（particlecontamination)的發生。 (V11)封裝尺寸沒有限制(free)，❿因為將相當於m封裝件 ^廢料與64腳（pin)之SQFP封裝件比較，僅有約1/1〇的 量，因此能降低環境的負擔。 315641D01 200832661 e (Viii)從搭載零件的印刷電路基板，到置入機能的電路基板 • 中’都能實現新的概念的系統結構。 (IX) ISB的型樣設計如同印刷電路基板之型樣設計般容 易，製造商的工程師也可以自行設計。 其次對關於ISB之製造流程上的優點進行說明。第3圖 係為習知之csp以及有關本發明之ISB製造流程的對照 圖。第3(B)圖係表示習知之csp的製造流程。首先在基底 ⑩基板上形成框架（frame)，在由各框架所劃分之元件形成區 域上女衣日日片。之後，在各元件上藉由熱硬化性樹脂設置 封裝體。之後，在每個元件上利用模具進行衝壓。在最後 步驟的衝壓中，因為模製樹脂以及基底基板同時被切斷， 而產生切feif面之表面龜裂等問題。此外因為衝壓結束之後 大f產生廢料，而有環境負擔的問題。 另一方面，第3(A)圖係表示ISB的製造流程圖。首先， 在金屬箔上設置框架，在各模組形成區域上，形成線路型 _樣，並於其上搭載LSI等電路元件。其次在每個模組上施 行封衣’ 者刮剔區域進行切塊工程，以 传到產品。封裝結束後，在刮割步驟前，因為先除去做為 基底的金屬箔，所以在刮割步驟的切塊工程中，只有對樹 脂層進行切斷。因此，得以抑制切斷面的龜裂，並使切塊 的正確性提高 1一實施形鼯 以下，有關本發明的較佳實施形態，將以具有前述ISB 構造的半導體模組當作例子進行說明。第4圖係有關本實 315641D01 13 200832661 %形悲的半導體模組的斷面構造的表示圖。該半導體模組 -係由，將由線路407所構成的線路層以複數層層疊後於最 上層形成抗銲層（solder resist)408之多層線路構造體，以及 在其表面所形成之元件4i〇a以及41〇b所構成。其中，該線 路層係由層間絕緣膜4〇5以及銅所構成。在多層線路構造 體的为面’設置有銲錫球420。元件410a以及41 〇b係為以 模製樹脂415所封模的構造體。在第4(1))圖_，相對於第40) _圖的構造，更進一步設置了由金屬材料構成的假（dummy) 線路435由此，可提面多層線路構造體和模製樹脂41 5之 間的緊密結合性。 有關元件410a的組裝方法中，雖然在第4圖中採用了銲 線知接方式（wire bonding)，然而也可如第；[〇圖所示把元件 410a以面朝下（face d〇wn)配置之方式進行覆晶式⑴化 組裝。 在如第1圖所示之習知半導體模組中，LSI晶片1〇2具有 癱藉由封裝樹脂密封裸晶片之晶片構造。相對於此，在第4 ，的半導體模組中，S件41()係具有沒有藉由封裝樹脂封 裸晶片。為此，必須更加確實地實行吸濕對策。在模 'Ο知415和夕層線路構造之間的界面若產生剝離，則例 如在銲錫步驟中，水分會由該處浸入，使裸晶片直接受到 姓刀的办专。在此情況，會造成晶片之性能大幅度損害的 結果。由此，在如第4圖所示之ISB構造的半導體模組中， 如何改善該界面的緊密結合性而充分抑制水分的透過係 已成為重要的技術課題。System in Package). (Because the existing semiconductor components can be combined, the system lsi can be developed in a short time. 1 (IV) Since the semiconductor bare wafer is directly mounted on the copper material directly under it, good heat dissipation can be obtained. b _( v) Because there is no circuit circuit for the core material of copper, and the circuit line with low dielectric constant rate, it can exert superior characteristics in fast data transmission and high frequency circuit. (0) Because the electrode system is inside the package. Buried structure, it can suppress the occurrence of particle contamination of the electrode • (V11) package size is not limited (free), because it will be equivalent to m package ^ scrap and 64 pin (SQFP) Compared with the package, it is only about 1/1 ,, so the burden on the environment can be reduced. 315641D01 200832661 e (Viii) From the printed circuit board on which the component is mounted, to the circuit board in which the function is installed Conceptual system structure (IX) The design of the ISB is as easy as the design of the printed circuit board, and the manufacturer's engineers can also design it themselves. Secondly, the advantages of the ISB manufacturing process are carried out. Fig. 3 is a comparison diagram of a conventional csp and an ISB manufacturing process relating to the present invention. Fig. 3(B) is a view showing a manufacturing process of a conventional csp. First, a frame is formed on a substrate 10 substrate, The component divided by each frame forms a day-to-day film of the vestibule. Thereafter, the package is provided on each element by a thermosetting resin. Thereafter, the die is punched on each component by means of a die. Since the molded resin and the base substrate are simultaneously cut, problems such as surface cracking of the cut surface are generated. Further, since the waste is generated after the end of the press, there is a problem of environmental burden. On the other hand, the third (A) The drawing shows a manufacturing flow chart of the ISB. First, a frame is placed on the metal foil, and a line type is formed on each of the module forming regions, and circuit elements such as LSI are mounted thereon. Secondly, on each module. Perform the squeegee area of the squeegee to pass the dicing process to the product. After the end of the package, before the squeegee step, the metal foil as the base is removed first, so in the dicing process of the scraping step Only the resin layer is cut. Therefore, the crack of the cut surface is suppressed, and the correctness of the dicing is improved. The preferred embodiment of the present invention has the above-described ISB structure. The semiconductor module will be described as an example. Fig. 4 is a diagram showing the cross-sectional structure of the semiconductor module of the present invention. The semiconductor module is composed of a circuit layer composed of a line 407. A multilayer wiring structure in which a plurality of solder resists 408 are laminated on the uppermost layer and a component 4i〇a and 41〇b formed on the surface thereof are laminated. Among them, the wiring layer is composed of an interlayer insulating film 4〇5 and copper. Solder balls 420 are provided on the surface of the multilayer wiring structure. The elements 410a and 41b are structural bodies that are molded by the molding resin 415. In the fourth (1)) diagram, the dummy line 435 made of a metal material is further provided with respect to the configuration of the 40th-th diagram, whereby the multi-layered line structure and the molded resin 41 can be lifted. 5 tight bond between. In the method of assembling the element 410a, although wire bonding is employed in FIG. 4, it may be as shown in the figure; [the element 410a is face down (face d〇wn) as shown in the figure. The configuration is carried out by flip-chip (1) assembly. In the conventional semiconductor module shown in Fig. 1, the LSI wafer 1 2 has a wafer structure in which a bare wafer is sealed by a sealing resin. On the other hand, in the semiconductor module of the fourth aspect, the S member 41 () has a bare wafer which is not sealed with a sealing resin. Therefore, it is necessary to implement moisture absorption measures more reliably. If the interface between the mold Ο 415 and the ridge layer structure is peeled off, for example, in the soldering step, moisture will be immersed therein, so that the bare wafer is directly subjected to the name of the knife. In this case, the performance of the wafer is greatly impaired. Therefore, in the semiconductor module of the ISB structure shown in Fig. 4, how to improve the adhesion of the interface and sufficiently suppress the moisture transmission system has become an important technical problem.

315641D0I 14 200832661 _ 為了解決這樣的課題，在本實施形態中，藉由選擇預 - 定條件之電漿處理，對抗銲層408的表面進行改質。具體而 言，係在抗銲層408之與模製樹脂415連接側的表面上，形 成微小突起群。此外，在抗銲層408的上述表面上，當將束 缚能-284.5 eV的檢測強度當作X，將束缚能-286 eV的檢測 強度當作y時，使X線光電子分光分析光譜之y/x之值於0.4 以上。 還有，使抗銲層408之連接模製樹脂415的區域在露出 ®時，對純水的接觸角係於30至120度範圍内。 可各自獨立選擇樹脂材料作為構成抗銲層408、層間絕 緣膜405以及模製樹脂415的材料，例如，可列出BT樹脂 (Resin)等之三聚氰胺（melamine)衍生物、液晶聚合物 (polymer)、環氧樹脂、PPE樹脂、聚醯亞胺（polyimide)樹 月旨、氟樹腊、紛（phenol)樹脂、聚醯胺雙馬來蕴亞胺 (polyamide bismaleimide)等之熱硬化性樹脂。其中，較宜 •使用在高頻特性方面較卓越的液晶聚合物、環氧樹脂、BT 樹脂等之三聚氰胺誘導體。除了這些樹脂，也可適宜地添 加填充物（filler)或添加劑。 另外，宜使用環氧樹脂、BT樹脂、液晶聚合物等作為 構成本發明之絕緣基材的材料。藉由使用這樣的樹脂，可 得到具有卓越之高頻特性以及產品可靠性的半導體模組。 其次，關於如第4(a)圖所示之半導體模組的製造方法， 將參照第5至7圖進行說明。首先，如第5(A)圖，在金屬箔 400之預定表面上選擇形成導電被覆膜402。具體而言，以 15 315641D01 200832661 • 光阻（photo resist)401覆蓋金屬箔400之後，藉由電場電鍍 • 法，在金屬箔400的露出面上形成導電被覆膜402。將導電 被覆膜402的膜厚形成為例如1至10 μιη的程度。由於該導 電被覆膜402最終成為半導體模組的背面電極，所以較宜使 用與銲錫等銲料之接著性良好的金或銀形成。 其次，如第5(B)圖所示，在金屬箔400上，形成第一層 的線路型樣（pattern)。首先對金屬箔400進行化學研磨以進 行表面清潔和表面粗化。其次，在金屬箱400上以熱硬化性 β樹脂覆蓋導電被覆膜402之全面，對其加熱硬化使其成為具 有平坦表面的膜體。其次，在該膜中，形成到達導電被覆 膜402之直徑100左右的通孔（via hole)404。有關設置通孔 404的方法，在本實施形態中係以雷射加工進行，然而除此 之外，也可使用機械加工、藉由藥液之化學钱刻加工、使 用電漿的乾蝕刻法等。之後，以雷射照射除去蝕刻殘渣之 後，以填埋通孔404之方式在全面上形成銅電鍍層。之後， 參將光阻作為遮罩（mask)以蝕刻銅電鍍層，而形成由銅構成 的線路407。例如，可在從光阻露出的部位上，喷灑化學蝕 刻液，將不需要的銅箔蝕刻除去，而形成線路型樣。 如以上所述，藉由反覆進行層間絕緣膜405的形成、通 孔形成、銅電鍍層的形成以及銅電鍍層之型樣化之步驟， 而可如第5(C)圖所示，由線路407以及層間絕緣膜405構成 之線路層層疊而形成多層線路構造。 其次，如第6(A)圖所示，在形成抗銲層408之後，藉由 雷射加工在抗銲層408中形成接觸孔（contact hole)421。其 16 315641D01 200832661 中，可便用含有填充物之環轰 -的構成姑抖六士— 衣虱樹月曰糸絶緣膜作為抗銲層408 除此之外，也可日由田射加工進行，然而 乾峨等l?t械加工、藉由藥液之化學钱刻加工、 ==。之後，精由電漿照射除去做钱刻 漿處理。 及虱構成的電漿氣體進行該電 面广有前述形態㈨―1-)以及樹脂特性的表 | 、座士 竹週且地设定電漿照射條 通有，較且不對基板施加偏虔。 件進行。 例如可用如以下的條 偏壓：無施加 電裝氣體：氬10至20sccm，氧〇^〇sccm 藉由該電浆照射，除了除去線路4〇7表面的 ^也對^層彻的表面進行改質，而形成具有前料 悲以及树月曰特性之表面層。 其次如第6(削所示’在抗銲層彻上搭载元件他、 41〇b。有關兀件410’可採用電晶體、二極體、ic晶片等 導體兀件’或晶片電容、晶片電阻等被動元件。 可安裝CSP、爾等面朝下的半導體元件。在第6⑻圖的 構造中，兀件他是未封著之裸半導體元件（電晶體晶 片），而元件4H)b是晶片電容器。將這些元件固定於抗鲜層 408上。以此狀態再度進行電i處理。為形成具有前述形態 以及樹脂特性的表面層，而按照所使用的樹脂材料適宜地 315641D01 17 200832661 s 設定電漿照射條件。還有，較宜不對基板施加偏壓。例如 - 可用如以下的條件進行。 偏壓：無施加 電漿氣體：氬10至20 seem ，氧0至10 seem 藉由該電漿照射，除了可除去線路407表面的蝕刻殘渣 外，也可對抗銲層408的表面進行改質，而形成具有前述 形態以及樹脂特性的表面層。 之後，透過經形成之通孔，藉由線路407以及金線412 ⑩連接元件410a之後，以模製樹脂（molding resin)415對這些 結構進行封裝。第7(A)圖表示被封裝後的情況。半導體元 件的封裝係對設置於金屬箔400上之複數個模組，用模具 同時進行。該步驟可藉由轉移成模（transfer mold)、射出 成型（injection mold)、膠埋法（potting)或浸潰法（dipping) 而實現。在樹脂材料中，環氧樹脂等熱硬化性樹脂可用在 轉移成模或膠埋法中實行，而聚醯亞胺樹脂等熱塑性樹脂 肇則可在射出成型中實行。 之後，如第7(B)圖所示，從多層線路構造除去金屬箔 400，並在背面上形成銲錫球420。其中，可藉由拋光、研 磨、蝕刻、雷射之金屬蒸發等進行金屬箔400的除去。在本 實施形態中採用以下的方法。亦即，藉由拋光裝置或研磨 裝置將金屬箔400削除50μπι左右，而剩餘的金屬箔400則藉 由化學式濕蝕刻除去。還有，也可以藉由濕蝕刻除去金屬 箔400全部。藉由透過這樣的步驟，在搭載半導體元件侧之 對向侧的表面上，使第1層線路407的背面露出。據此，由 18 315641D01 200832661 .組的背面可變得平坦’而可具有此製 力而水^動導體模組時，㈣由薛錫等表面張 銲錫丄：覆固著銲錫等導電材，並形成 晶圓（f v體极組。之後，猎由切塊製程切斷 曰iUwafer)’而可得到半導體模組晶片 ，除去步驟為止，係將金屬請當作 之乍二。料，當使模製樹脂化成模時，其也可使至模且 运、拉具之組裝操作性變得良好。進行如以上之 而可得到如第4(·所示之構造的半導體模組。’ 該半導體模組，在第6⑻圖之步驟中，因為 θ Π進：氬電漿處理’而進行表面改質的關係，使抗：層二 和桓衣树脂415之間的界面緊密結合性明顯地改善。以 果，可使半導體模組的可靠性明顯提高。 於此，也可以用含有多官能氧環丁燒化合 化性·熱硬化性樹脂，作為構成= Η 才枓。猎此，因為除了微小突起，還可在表面形成複數 火山口狀凹部，而可更加改善緊密結合性。 至於抗銲層408的表面是否存在凹凸狀，可斜切斷抗 408’使用掃描型電子顯微鏡觀察等分析其斷面而確切。 此外，例如，在如抗銲層彻端部等部位沒有藉由模^ 樹脂化封裝的部份之表面是否有凹凸存在，也能使用= 描型電子顯微鏡觀察筝進行該表面之分析而確認。 Ψ 315641D01 19 200832661 弟二貫施形悲 在第一實施形態中，具有在括^曰 另隹柷鋅層408上由銲錫固定元 件410a、元件410b的結構，然而若 阳右不利用銲錫，也能以接 著劑等固著元件。在該情況下， 的構造。 也μ成沒有設置抗銲層 直接將元件接著於線路上 第一實施形態中所說明者 係使用環氧樹脂作為層間315641D0I 14 200832661 _ In order to solve such a problem, in the present embodiment, the surface of the solder resist layer 408 is modified by plasma treatment by selecting a predetermined condition. Specifically, on the surface of the solder resist layer 408 which is connected to the molding resin 415, a minute projection group is formed. Further, on the above surface of the solder resist layer 408, when the detection intensity of the binding energy of -284.5 eV is regarded as X, and the detection intensity of the binding energy of -286 eV is regarded as y, the y/ of the X-ray photoelectron spectroscopic analysis spectrum is made. The value of x is above 0.4. Further, when the region of the solder resist layer 408 to which the mold resin 415 is bonded is exposed, the contact angle with respect to pure water is in the range of 30 to 120 degrees. The resin material may be independently selected as a material constituting the solder resist layer 408, the interlayer insulating film 405, and the mold resin 415. For example, a melamine derivative such as a BT resin (Resin) or a liquid crystal polymer may be listed. A thermosetting resin such as an epoxy resin, a PPE resin, a polyimide tree, a fluorobar wax, a phenol resin, or a polyamide bismaleimide. Among them, it is preferable to use a melamine inducer such as a liquid crystal polymer, an epoxy resin, or a BT resin which is excellent in high frequency characteristics. In addition to these resins, a filler or an additive may be suitably added. Further, an epoxy resin, a BT resin, a liquid crystal polymer or the like is preferably used as the material constituting the insulating base material of the present invention. By using such a resin, a semiconductor module having excellent high frequency characteristics and product reliability can be obtained. Next, a method of manufacturing a semiconductor module as shown in Fig. 4(a) will be described with reference to Figs. First, as shown in Fig. 5(A), the conductive coating film 402 is selectively formed on a predetermined surface of the metal foil 400. Specifically, after the metal foil 400 is covered with a photo resist 401, a conductive coating film 402 is formed on the exposed surface of the metal foil 400 by an electric field plating method. The film thickness of the conductive coating film 402 is formed to the extent of, for example, 1 to 10 μm. Since the conductive coating film 402 eventually becomes the back surface electrode of the semiconductor module, it is preferable to use gold or silver which is excellent in adhesion to solder such as solder. Next, as shown in Fig. 5(B), a wiring pattern of the first layer is formed on the metal foil 400. The metal foil 400 is first chemically ground for surface cleaning and surface roughening. Next, the entire surface of the conductive coating film 402 is covered with a thermosetting β resin on the metal case 400, and heat-hardened to form a film body having a flat surface. Next, in the film, a via hole 404 reaching a diameter of about 100 of the conductive coating film 402 is formed. Although the method of providing the through hole 404 is performed by laser processing in the present embodiment, mechanical processing, chemical etching by a chemical liquid, dry etching using a plasma, or the like may be used. . Thereafter, after the etching residue is removed by laser irradiation, a copper plating layer is formed over the entire surface by filling the via holes 404. Thereafter, the photoresist is used as a mask to etch the copper plating layer to form a line 407 made of copper. For example, a chemical etching solution may be sprayed on a portion exposed from the photoresist to etch away the unnecessary copper foil to form a wiring pattern. As described above, by repeating the steps of forming the interlayer insulating film 405, forming via holes, forming a copper plating layer, and patterning the copper plating layer, as shown in FIG. 5(C), The circuit layers formed of 407 and the interlayer insulating film 405 are laminated to form a multilayer wiring structure. Next, as shown in Fig. 6(A), after the solder resist layer 408 is formed, a contact hole 421 is formed in the solder resist layer 408 by laser processing. In its 16 315641D01 200832661, it is possible to use the ring-like material containing the filler - the 抖 六 — — 虱 虱 — — — — 曰糸 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 408 Dry sputum and other l?t mechanical processing, processing by chemical money of chemical liquid, ==. After that, the fine is treated by plasma irradiation to remove the money for slurry treatment. The plasma gas composed of the ruthenium and the ruthenium has a surface in which the above-mentioned form (9) -1) and the resin characteristics are widely distributed, and the plasma irradiation strip is set in the shovel, and the substrate is not biased. Pieces are carried out. For example, a bias can be used as follows: no applied electrification gas: argon 10 to 20 sccm, and oxygen 〇^〇sccm is irradiated by the plasma, except that the surface of the wiring 4〇7 is removed, and the surface of the layer is also modified. Quality, and form a surface layer with the characteristics of forehead and tree. Secondly, as shown in the sixth section (shown as 'there is a component mounted on the solder resist layer, 41〇b. The related component 410' can be a conductor element such as a transistor, a diode or an ic chip, or a chip capacitor or a chip resistor. A passive component such as a CSP or a face-down semiconductor device can be mounted. In the configuration of Fig. 6 (8), the component is an unsealed bare semiconductor component (transistor wafer), and the component 4H)b is a wafer capacitor. . These components are fixed to the anti-fresh layer 408. The electric i process is again performed in this state. In order to form the surface layer having the above-described morphology and resin characteristics, plasma irradiation conditions are set in accordance with the resin material to be used suitably 315641D01 17 200832661 s. Also, it is preferred not to apply a bias to the substrate. For example - can be done under the following conditions. Bias: no applied plasma gas: argon 10 to 20 seem, oxygen 0 to 10 seem. By irradiating the plasma, in addition to removing the etching residue on the surface of the line 407, the surface of the solder resist layer 408 can be modified. On the other hand, a surface layer having the above-described morphology and resin properties is formed. Thereafter, after the elements 410a are connected through the formed via holes by the wiring 407 and the gold wires 412 10, the structures are encapsulated by a molding resin 415. Fig. 7(A) shows the case after being packaged. The package of the semiconductor component is performed simultaneously on the plurality of modules disposed on the metal foil 400 by using a mold. This step can be achieved by transfer mold, injection molding, potting or dipping. Among the resin materials, a thermosetting resin such as an epoxy resin can be used in a transfer molding or a cementing method, and a thermoplastic resin such as a polyimide resin can be carried out in injection molding. Thereafter, as shown in Fig. 7(B), the metal foil 400 is removed from the multilayer wiring structure, and solder balls 420 are formed on the back surface. Among them, the removal of the metal foil 400 can be performed by polishing, grinding, etching, metal evaporation of a laser or the like. In the present embodiment, the following method is employed. That is, the metal foil 400 is removed by a polishing apparatus or a grinding apparatus by about 50 μm, and the remaining metal foil 400 is removed by chemical wet etching. Further, all of the metal foil 400 may be removed by wet etching. By the above-described procedure, the back surface of the first layer line 407 is exposed on the surface on the opposite side on which the semiconductor element side is mounted. Accordingly, the back surface of the group can be made flat by 18 315641D01 200832661. When the force is applied to the water and the conductor module is used, (4) the surface soldering tin such as Xue Xi: the conductive material such as solder is fixed, and A wafer (fv body group is formed. Then, the shovel process is cut off by 切iUwafer) is used to obtain a semiconductor module wafer, and the metal is taken as a second step. When the molded resin is molded into a mold, it can also improve the assembly workability of the mold and the puller. As described above, a semiconductor module having the structure shown in FIG. 4 can be obtained. 'The semiconductor module is subjected to surface modification in the step of FIG. 6(8) because θ is advanced: argon plasma treatment' The relationship between the anti-layer layer and the coating resin 415 is significantly improved. The reliability of the semiconductor module can be significantly improved. Here, the polyfunctional oxygen ring can also be used. The composition of the heat-suppressing and thermosetting resin is as follows: 构成 , , , , , , , 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎 猎Whether or not the surface has a concavo-convex shape, and the oblique anti-408' can be analyzed by a scanning electron microscope or the like, and the cross section is determined by, for example, a resin-free encapsulation at a portion such as a solder resist layer. If there is any irregularity on the surface of the part, it can be confirmed by using the electron microscope to observe the kite and analyze the surface. Ψ 315641D01 19 200832661 The second embodiment is in the first embodiment, and has Further, the zinc layer 408 is fixed by the solder fixing member 410a and the element 410b. However, if the solder is not used, the element can be fixed with an adhesive or the like. In this case, the structure is also The solder resist layer is provided directly on the line, and the epoxy resin is used as the interlayer between the first embodiment.

第9圖係表示沒有抗銲層時， 的結構。多層線路構造係具有於 之相同構造。在本實施形態中， 絕緣膜405。 ”該+導體模組可如以下所述般進行製造。首先進行到 弟5(C)圖為止的步驟。隨後，如第_般藉由接著劑而固著 二二Γ41。'。在該狀態下對元件形成面進行電裝 心。電水處理係以第-實施形態之同樣方式進行 該電漿照射，使線路4G7的表面具有清潔的狀態，而使元件 4=讀410b以及線路術間可具有良好的接線。此外， =並猎由電漿處理而同時對層間絕緣膜彻的表面進行 改質’而形成具有前述之形態以及樹脂特性的表面層。 ^之後，藉由線路407和金線412對元件4H)a進行接線之 後模製樹月旨415對這些結構進行封模。根據以上之步驟 :::导到如第9圖所示之構造的半導體模組。該半導體模組 弟圖的步驟中，因為對層間絕緣磨405進行氬電漿處 而進行表面改質的關係，使層間絕緣膜405和模製樹脂 415之間的界面緊密結合性明顯改善。該結果可使半導體模 組的可靠性明顯提高。、 315641D01 20 200832661 t ;也可以用含有多官能氧環丁燒化合物或環氧榭 月曰化合物的光硬化性·熱硬化性_ 緣 磨層4。5的材料。藉此，因為除了微小突起，還;=开緣 成稷數火山口狀凹部，而可更加改善緊密結合性。' …此：，可斜切斷層間絕緣膜層4 〇 5後，使用掃描型電 减微鏡硯察等分析其斷面㈣行在絕緣膜層他的表面是 否有凹凸狀存在之確認。 此外，例如，在如絕緣膜層405端部等部位沒有藉由 製樹脂化封裝的部份之表面是否有凹凸狀存在，也能使才用 知描型電子顯微鏡觀察等進行該表面之分析而確認。 實施形轉 透過接著材料510 在本實施形態中，如第15圖所示 將元件502接著於基板506上。 一據此，在元件502和基板506間界面之緊密結合性不佳 的話，會有從該地方發生元件502剝離的疑慮，而造成半導 _體模組之可靠性大幅度損害的結果。 —t了解決這樣的課題，在本實施形態中，藉由選擇和 第一實施形態以及第二實施型態相同的條件之電漿處理， 而對連接接著材料510之基板506的表面進行改質。其中， 該接著材料.510係連接元件502的下表面。具體而言，係在 基板506具有線路層的表面上，形成微小突起群和，例如， 直徑100 nm以上之複數火山口狀凹部。此外，在基板5〇2 之上返表面上，g將束缚能-284 · 5 eV的檢測強度當作X， 3I5641D01 21 200832661 胃 將束缚能-286 eV的檢測強度當作y時，係使X線光電子分光 - 分析光譜之y/χ之值於0.4以上。 還有，在露出基板506之與模製樹脂415連接的區域 時，其對純水的接觸角係在30至120度的範圍内。 在這裡，也可以用含有多官能氧環丁烷化合物或環氧 化合物的光硬化性·熱硬化性樹脂作為構成基板506的材 料。藉此，因為除了微小突起外，還在表面形成複數之火 山口狀凹部，而可改善緊密結合性。 ® 此外，可斜切斷基板506後，藉由使用掃描型電子顯微 鏡觀察等分析其斷面而進行在基板506的表面是否有凹凸 狀存在之確認。 此外，例如，在如基板506端部等部位沒有藉由模製樹 脂415封裝的部份之表面是否有凹凸狀存在，也能藉由使用 掃描型電子顯微鏡觀察等進行該表面之分析而確認。 以上說明了適合本發明之實施形態。，但是，本發明非 馨僅限定於上述之實施形態，本業者在本發明的範圍内當然 也可實行上述之實施形態的變型。 例如，有關上述之實施形態中，係對半導體模組相關 進行說明，然而本發明也可適用於半導體模組以外的模組。 此外，有關上述之實施形態中，係對採用設置有線路 407的抗銲層408之形態進行說明，然而，也可以採用例如 設置有導線架（lead frame)等之線路407以外之導電體的抗 鮮層。 22 315641D01 200832661 此外，有關上述之實施形態中，係針對使用抗銲層408 - 為絕緣基材的形態進行說明，然而也可以使用絕緣基材以 外的基材。 實施例 實施例1 在銅箔表面貼上乾抗钱膜（dry film resist)(商品名 PDF300，新日鐵化學社製）之後，對該抗蝕膜進行型樣化， 而露出銅箔表面之一部份。在該狀態下，對含銅箔露出面 ®以及乾抗蝕膜面之全面進行氬電漿處理。其中，改變電漿 氣體裏面的氧濃度而製造出2種類的樣品。 偏壓電壓：無施加 電漿氣體：樣品1 氬10 seem，氧0 seem 樣品 2 氬 10 seem，氧 10 seem RF功率（W) : 500 壓力（Pa): 20 φ處理時間（sec) ·· 20 藉由掃描型電子顯微鏡，而對電漿照射前後的乾抗蝕 膜表面進行了觀察。結果如第Π圖、第12圖以及第13圖所 示。第11圖表示樣品1、第12圖表示樣品2、第13圖表示未 電漿處理之外觀。可清楚地瞭解，藉由電漿照射可在樹脂 表面形成複數之微小突起。使用藉由掃描型電子顯微鏡觀 察所得到的晝像資料，對微小突起的平均直徑以及密度進 行測定。密度係對長度1 μιη之直線上之微小突起數量（線密 23 315641D01 200832661 度）進行測定，並將該數量乘以2後而求得。將結果於以下 表示。 樣品1 平均直徑4 nm 數量密度1.2xl03個/μπι2 才篆品2 平均直徑4 nm 數量密度1.6xl03個/μπι2 其次，對該樣品1、2相關進行X線光電子分光分析。 將結果表示於第14圖。在圖中，除了樣品1、2外，也顯示 了氬電漿處理前的曲線以作為參照。可知道藉由電聚照 射，在有關286 eV的C=0結合而來的強度增加的同時，有 關284.5 eV之C—0結合或0_^^結合而來的強度反而減 少。把有關284.5 eV的C—〇結合或C —;^結合而來的強度 _當作X，把有關286 eV的〇〇結合而來的強度當作y時，: 有關本實施例之模組之y/x的數值中，樣品丨、2都大約為 續之’對該樣品1、2測量接觸角。在抗蝕膜表面上 下純水後’以放大鏡觀察水滴形狀並測量其接觸角。該 觸角之測定係於樣品製作2天後進行。所得到的接觸角： :如下所不。據此，可知在採用乾抗钱膜（商品名卿％ ^雜學的樣品卜樣心，具有接觸角為30至 度之々人滿意的表現。 315641D01 24 200832661 • 樣品1 52.0度 • 樣品2 53.6度 於第一實施型態所陳述之製程中，應用與上記樣品1 以及樣品2同樣之成模、電漿處理製程以製造半導體模組。 該半導體模組將樣品1、2的乾抗蝕膜作為抗銲層，並於其 表面搭載有半導體元件。對該半導體模組進行評償後，除 了熱循環（heat cycle)性十分卓越外，於壓力锅(pressure ⑩cooker)試驗也有良好的結果。 實施例2 在銅箔表面上貼上乾抗蝕膜（商品名AIJS402，太陽 INK社製）之後，對該抗蝕膜進行型樣化，而露出銅箔表面 之一部份。在該狀態下，對含銅箔露出面以及環氧樹脂系 抗蝕膜面之全面進行氬電漿處理。 此外，於此，上述之乾抗韻膜（商品名AUS402，太陽 鲁INK社製）因為係使用含有多官能氧環丁烷化合物或環氧 化合物的光硬化性·熱硬化性樹脂所製造出，而在表面存 在有火山口狀凹部。 偏壓：無施加 電漿氣體：氬10 seem，氧0 seem RF功率（W):500 壓力（Pa) : 20 處理時間··樣品3 ·· 20(sec) 樣品 4 : 60(sec) 25 315641D01 200832661 夺面：由型電子顯微鏡，對電漿照射前後的乾抗蝕膜 二祭。結果如第16圖、第17圖以及第18圖所 不弟16圖係表示樣口 ^ μ m ^ - σ口3、弟17圖係表不樣品4、第18圖係 理之外觀。可清楚地瞭解，藉由電漿照射可 s、曰、面形成複數之微小突起。使用藉由掃描型電子顯 微鏡觀察所得到的晝像㈣，對微小突起的平均直=：； :度，定：密度係對長度1μιη之直線上之微小突起數 里（、、、！山度)進行測定’並將該數量乘以2後而求得。將結果 於以下表示。 樣品3 平均直徑 4 nm 數里德、度2χ 1 〇3個/μ^2 樣品4 馨平均直徑4 nm 數量密度2xl〇3個/μιη2 其次，對上述樣品進行Χ線光電子分光分析。將結果表 不於第19圖。在圖中，係將氬電漿處理前的曲線作為參照 而顯不樣品4的曲線。可知道藉由電漿照射，在有關286 eV 的c=o結合而來的強度增加的同時，有關284·5 eV之 結合或C — N結合而來的強度反而減少。把有關284·5 eV的 C一 Ο結合或C — N結合而來的強度當作χ，把有關286 £¥的 315641D01 26 200832661 〇〇結合而來的強度當作y 的數值約為0.4。 1本η施例的模組之y/x -貝之，對上述樣品進行接觸角的量測 一 上滴下純水後，以放大户a 抗蝕肤表面 敌大鏡鏡祭水滴形狀 該接觸角之測定係於樣品製 ；里/、接觸角。 的數值係如下所示。衣作2天後知。所得到的接觸角 樣品3 80度 樣品4 105度 二卜=態所陳述之製程中，應用與上述樣品同 ^、電漿處理$程，而製造半導體模組。該半導體 Μ將上述樣品的乾抗韻膜作為抗鲜層，並於其表面 m。對該半導體模組進行評價後，除了熱猶環 !·生十为卓越外，於壓力賴驗也具有良好㈣果。 【圖式簡單說明】 Φ 第1圖係為BGA構造的說明圖。 第2圖係為ISB(登錄商標）構造的說明圖。 第3(A)及3(B)圖係為BGA以及⑽（登錄商標）之製造 流程的說明圖。 第4(a)及4(b)圖係為相關半導體模組之構造的說明 圖。 策5(A)至5(C)圖係為相關半導體模組之製造方法的 說明圖。 " 第6(A)及6(B)圖係為相關半導體模組之製造方法的 315641D01 27 200832661 ’ 說明圖。 弟7(A)及7(B)圖係為相關半導體模組之製造方法的 說明圖。 第8圖係為相關半導體模組之製造方法的說明圖。 第9(A)及9(B)圖係為相關半導體模組之製造方法的 說明圖。 第10(a)及10(b)圖係為相關半導體模組之構造的說明 圖。 \第11圖係藉由掃瞎型電子顯微鏡觀察電裝處理後之 抗姓膜表面的結果的表示圖。 第12圖係藉由掃瞄型電子 枋飩暄矣而认沾田 I包千颂微鏡歲祭電漿處理後之 抗姓膜表面的結果的表示圖。 弟13圖係藉由掃目结型電 4^^^. I包千頭微鏡觀察電漿處理後之 柷蝕肤表面的結果的表示圖。 叉又 第14圖係為電漿處理後之 ►分光分析結果的表示圖。 、又之X線光電子 導體模組之構造-_。 罘16圖係猎由掃瞄型電 ^ 抗蝕膜表面的結果的表示圖。〜微鏡喊祭電漿處理後之 之 抗心：果藉:表掃：電子顯微鏡觀察”處理後 抗蝕膜表面的結:::::電子顯微鏡觀察電漿處理後 之 第19圖係為電漿處後之抗餘膜表面之[線光電子 315641D01 28 200832661 Λ 分光分析結果的表示圖。 ^ 【主要元件符號說明】 100 球閘陣列封裝（BGA) 102 LSI晶片 104 金屬線 106 環氧基板 108 接著層 110 封裝樹脂 112 録錫球 201 LSI裸晶片 202 Tr裸晶片 203 晶片CR 204 金旅 205 銅型樣 206 導電膏 207 樹脂封裝體 208 銲錫球 400 金屬f# 401 光阻 402 導電被覆膜 404 通孑L 405 層間絕緣膜 407 線路 408 抗銲層 410a， 410b元件 412 金線 415 模製樹脂 420 焊錫球 421 接觸孑L 435 假線路 502 元件 506 基板 510 接著材料 29 315641D01Fig. 9 shows the structure when there is no solder resist layer. The multilayer wiring structure has the same configuration. In the present embodiment, the insulating film 405 is provided. The +conductor module can be manufactured as described below. First, the steps up to the fifth (C) diagram are performed. Subsequently, the second layer 41 is fixed by the adhesive as in the first place. The element forming surface is electrically mounted. The electro-hydraulic treatment performs the plasma irradiation in the same manner as in the first embodiment, so that the surface of the line 4G7 has a clean state, and the element 4 = reading 410b and the line can be inter-operative. It has good wiring. In addition, = and the surface of the interlayer insulating film is modified by plasma treatment to form a surface layer having the aforementioned morphology and resin characteristics. ^ After that, by line 407 and gold wire After the components 412 are connected to the component 4H)a, the molding process is performed to mold the structures. According to the above steps::: to the semiconductor module constructed as shown in Fig. 9. The semiconductor module In the step of performing surface modification by performing argon plasma on the interlayer insulating mill 405, the interface tightness between the interlayer insulating film 405 and the molding resin 415 is remarkably improved. The reliability of the 315641D01 20 200832661 t ; It is also possible to use a photocurable·thermosetting _ edge-grinding layer 4. 5 material containing a polyfunctional oxycyclobutane compound or an epoxy oxime compound. , also; = open edge into a number of crater-like recesses, and can improve the tight bond. 'This:, can be obliquely cut off the interlayer insulating film layer 4 〇 5, using scanning-type electric micro-mirror observation, etc. In addition, for example, the surface of the portion of the insulating film layer having no irregularities is formed on the surface of the insulating film layer. In the present embodiment, it is also confirmed that the surface is analyzed by a scanning electron microscope observation or the like. The transfer of the transfer material 510 is performed in the present embodiment, and the element 502 is attached to the substrate 506 as shown in FIG. Accordingly, if the interface between the element 502 and the substrate 506 is not tightly coupled, there is a concern that the element 502 is peeled off from the place, and the reliability of the semiconductor module is greatly impaired. —t understand In such a problem, in the present embodiment, the surface of the substrate 506 to which the bonding material 510 is bonded is modified by plasma treatment under the same conditions as those of the first embodiment and the second embodiment. Next, the material .510 is connected to the lower surface of the element 502. Specifically, on the surface of the substrate 506 having the wiring layer, a minute protrusion group and, for example, a plurality of crater-shaped recesses having a diameter of 100 nm or more are formed. On the surface of the surface above 5〇2, g will measure the intensity of the binding energy of -284 · 5 eV as X, 3I5641D01 21 200832661 When the detection intensity of the stomach binding energy -286 eV is regarded as y, the X-ray photoelectron is split- The value of y/χ of the analytical spectrum is above 0.4. Further, when the region of the substrate 506 which is joined to the molding resin 415 is exposed, its contact angle with respect to pure water is in the range of 30 to 120 degrees. Here, a photocurable thermosetting resin containing a polyfunctional oxycyclobutane compound or an epoxy compound may be used as the material constituting the substrate 506. Thereby, in addition to the minute protrusions, a plurality of fire mountain-like recesses are formed on the surface, and the tight bondability can be improved. Further, after the substrate 506 is obliquely cut, it is confirmed whether or not the surface of the substrate 506 is uneven by analyzing the cross section by scanning electron microscopic observation or the like. Further, for example, if the surface of the portion which is not encapsulated by the molding resin 415 is present at the end portion of the substrate 506 or the like, whether or not there is a concavo-convex shape, it can be confirmed by analyzing the surface using a scanning electron microscope observation or the like. The embodiments that are suitable for the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and it is a matter of course that those skilled in the art can implement the modifications of the above-described embodiments within the scope of the present invention. For example, in the above embodiments, the semiconductor module is described. However, the present invention is also applicable to modules other than the semiconductor module. Further, in the above-described embodiment, the form of the solder resist layer 408 provided with the wiring 407 is described. However, for example, an electric conductor other than the wiring 407 provided with a lead frame or the like may be used. Fresh layer. 22 315641D01 200832661 In the above embodiment, the case where the solder resist layer 408 - is used as the insulating base material will be described. However, a base material other than the insulating base material may be used. EXAMPLES Example 1 After a dry film resist (trade name: PDF300, manufactured by Nippon Steel Chemical Co., Ltd.) was attached to the surface of a copper foil, the resist film was patterned to expose the surface of the copper foil. a part. In this state, argon plasma treatment was performed on the copper-containing foil exposed surface ® and the dry resist film surface. Among them, two kinds of samples were produced by changing the oxygen concentration in the plasma gas. Bias voltage: no applied plasma gas: sample 1 argon 10 seem, oxygen 0 seem sample 2 argon 10 seem, oxygen 10 seem RF power (W): 500 pressure (Pa): 20 φ processing time (sec) ·· 20 The surface of the dry resist film before and after the plasma irradiation was observed by a scanning electron microscope. The results are shown in Fig. 12, Fig. 12, and Fig. 13. Fig. 11 shows the sample 1, Fig. 12 shows the sample 2, and Fig. 13 shows the appearance of the unplasma treatment. It is clearly understood that a plurality of minute protrusions can be formed on the surface of the resin by plasma irradiation. The average diameter and density of the microprotrusions were measured by observing the obtained image data by a scanning electron microscope. The density is determined by measuring the number of minute protrusions on the line of length 1 μιη (line density 23 315641D01 200832661 degrees) and multiplying the number by two. The results are shown below. Sample 1 Average diameter 4 nm Number density 1.2xl03/μπι2 Product 2 Average diameter 4 nm Number density 1.6xl03/μπι2 Next, X-ray photoelectron spectroscopy analysis was performed on the samples 1 and 2. The results are shown in Fig. 14. In the figure, in addition to the samples 1, 2, the curve before the argon plasma treatment was also shown as a reference. It can be known that by electro-convergence, the intensity of C=0 combined with 286 eV is increased, and the intensity of C-0 combination or 0_^^ of 284.5 eV is reduced. When the intensity _ combined with the C-〇 combination of 284.5 eV or C-;^ is regarded as X, and the intensity of the combination of 286 286 eV is regarded as y, the module of the embodiment is In the values of y/x, the samples 丨, 2 are approximately continued 'measure the contact angle for the samples 1, 2 . After the pure water was applied to the surface of the resist film, the shape of the water drop was observed with a magnifying glass and the contact angle was measured. The measurement of the antennae was carried out 2 days after the preparation of the sample. The resulting contact angle: : None of the following. According to this, it can be seen that the dry anti-money film (the sample name of the product name, the sample has a contact angle of 30 to 10 degrees.) 315641D01 24 200832661 • Sample 1 52.0 degrees • Sample 2 53.6 In the process described in the first embodiment, the same mold and plasma processing process as in the above sample 1 and sample 2 is used to fabricate a semiconductor module. The semiconductor module will dry the resist film of samples 1 and 2. As a solder resist layer, a semiconductor element was mounted on the surface thereof, and after the evaluation of the semiconductor module, in addition to excellent heat cycle, the pressure cooker (pressure 10 cooker) test also had good results. Example 2 After a dry resist film (trade name: AIJS402, manufactured by Sun Ink Co., Ltd.) was attached to the surface of the copper foil, the resist film was patterned to expose a part of the surface of the copper foil. The entire surface of the copper-containing foil exposed surface and the epoxy resin-based resist film surface are subjected to argon plasma treatment. In addition, the above-mentioned dry anti-speech film (trade name: AUS402, manufactured by Sunlu Ink Co., Ltd.) is used in a large amount. Functional oxygen ring A photocurable or thermosetting resin of an alkyl compound or an epoxy compound is produced, and a crater-like recess is present on the surface. Bias: no plasma gas is applied: argon 10 seem, oxygen 0 seem RF power (W) :500 Pressure (Pa) : 20 Processing time ··Sample 3 ·· 20 (sec) Sample 4 : 60 (sec) 25 315641D01 200832661 Face: A dry resist film before and after plasma irradiation by a type electron microscope The results are as shown in Fig. 16, Fig. 17, and Fig. 18, which show the appearance of the sample ^ μ m ^ - σ port 3, and the younger figure 17 is not the sample 4 and the 18th figure. It is clearly understood that a plurality of minute protrusions can be formed by s, 曰, and surface by plasma irradiation. The average image of the micro-protrusions is obtained by observing the obtained image (4) by a scanning electron microscope. The density is determined by measuring the number of microprotrusions on the straight line of length 1 μm (, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , De, 2 χ 1 〇 3 / μ^2 Sample 4 Xin average diameter 4 nm Quantity density 2xl 〇 3 / Ιη2 Next, the above sample was subjected to Χ-line photoelectron spectroscopy. The results are shown in Fig. 19. In the figure, the curve before the argon plasma treatment is used as a reference to show the curve of the sample 4. It is known that Slurry irradiation, while the intensity of c=o combined with 286 eV is increased, the intensity of the combination of 284·5 eV or C-N is reduced. Combining C and 284 about 284·5 eV Or the strength of C-N combined is taken as χ, and the strength of 315641D01 26 200832661 有关 of 286 £¥ is taken as the value of y is about 0.4. 1 y / x - shell of the η embodiment, measuring the contact angle of the above sample, after dropping the pure water, to enlarge the a surface of the surface of the retina The measurement is based on the sample; in /, contact angle. The values are as follows. Clothes are known after 2 days. The resulting contact angle sample 3 80 degrees sample 4 105 degrees Dibu = state stated in the process, the application of the same sample ^, plasma treatment, to manufacture semiconductor modules. The semiconductor crucible uses the dry anti-stasis film of the above sample as an anti-fresh layer on the surface m. After evaluating the semiconductor module, in addition to the heat of the ring, the life is also excellent (four). [Simple description of the drawing] Φ Figure 1 is an explanatory diagram of the BGA structure. Fig. 2 is an explanatory diagram of an ISB (registered trademark) structure. The 3(A) and 3(B) drawings are explanatory diagrams of the manufacturing flow of the BGA and (10) (registered trademark). Figures 4(a) and 4(b) are explanatory views of the structure of the related semiconductor module. The diagrams 5(A) to 5(C) are explanatory diagrams of the manufacturing method of the related semiconductor module. " Figures 6(A) and 6(B) are diagrams of the manufacturing method of the related semiconductor module 315641D01 27 200832661'. The brothers 7(A) and 7(B) are diagrams showing the manufacturing method of the related semiconductor module. Fig. 8 is an explanatory view showing a method of manufacturing a related semiconductor module. The figures 9(A) and 9(B) are explanatory diagrams of the manufacturing method of the related semiconductor module. Figures 10(a) and 10(b) are diagrams showing the construction of related semiconductor modules. Fig. 11 is a diagram showing the results of the anti-surname film surface after the electric dressing treatment by a broom type electron microscope. Fig. 12 is a representation of the results of the surface of the anti-surname film after the treatment of the plasma film of the Izumi Miyoshi micro-mirror by the scanning type electron 枋饨暄矣. The 13th figure is a representation of the result of the surface of the etched surface after the plasma treatment by means of a sweeping junction type 4^^^. Fig. 14 is a representation of the results of the spectroscopic analysis after the plasma treatment. And the construction of X-ray optoelectronic conductor module -_. The 罘16 image is a representation of the result of scanning the surface of the resist film. ~ Micro-mirror shouting the anti-heart after the treatment of plasma: Fruit: Table scan: Electron microscopy" The surface of the resist film after treatment::::: Electron microscopy observation of the 19th image after plasma treatment is [Resistance of the surface of the anti-surveillance film after the plasma [Line photoelectron 315641D01 28 200832661 Λ Spectroscopic analysis results. ^ [Main component symbol description] 100 Ball Gate Array Package (BGA) 102 LSI Wafer 104 Metal Wire 106 Epoxy Substrate 108 Next layer 110 encapsulation resin 112 recording ball 201 LSI bare wafer 202 Tr bare wafer 203 wafer CR 204 gold brigade 205 copper pattern 206 conductive paste 207 resin package 208 solder ball 400 metal f # 401 photoresist 402 conductive coating film 404 pass孑L 405 interlayer insulating film 407 line 408 solder resist layer 410a, 410b element 412 gold wire 415 molded resin 420 solder ball 421 contact 孑L 435 dummy circuit 502 element 506 substrate 510 then material 29 315641D01

Claims (1)

200832661 β 十、申請專利範圍： -i. 一種半導體模組，包含設置有導體電路的絕緣基材、於 該絕緣基材上形成的半導體元件、連接該絕緣基材以及 該半導體元件的絕緣體，其特徵為： 在該絕緣基材之連接該絕緣體之表面附近的X線 光電分子分光光譜中，當將於束缚能284.5 eV之檢測強 度當作X，將於束缚能286 eV之檢測強度當作y時，y/x 值為0 · 4以上。 ❿ 30 315641D01200832661 β X. Patent application scope: -i. A semiconductor module comprising an insulating substrate provided with a conductor circuit, a semiconductor element formed on the insulating substrate, an insulator connecting the insulating substrate and the semiconductor element, The characteristic is: in the X-ray photoelectric molecular spectroscopic spectrum near the surface of the insulating substrate connected to the insulator, when the detection intensity of the binding energy of 284.5 eV is taken as X, the detection intensity of the binding energy of 286 eV is regarded as y. When the y/x value is 0 · 4 or more. ❿ 30 315641D01
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JP6698647B2 (en) * 2015-05-29 2020-05-27 リンテック株式会社 Method of manufacturing semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI621232B (en) * 2016-03-15 2018-04-11 Toshiba Memory Corp Semiconductor device

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