TW200423344A - Composite metal column for mounting semiconductor device - Google Patents

Composite metal column for mounting semiconductor device Download PDF

Info

Publication number
TW200423344A
TW200423344A TW092130857A TW92130857A TW200423344A TW 200423344 A TW200423344 A TW 200423344A TW 092130857 A TW092130857 A TW 092130857A TW 92130857 A TW92130857 A TW 92130857A TW 200423344 A TW200423344 A TW 200423344A
Authority
TW
Taiwan
Prior art keywords
component
components
contact
wafer
solder
Prior art date
Application number
TW092130857A
Other languages
English (en)
Inventor
John P Tellkamp
Akira Matsunami
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of TW200423344A publication Critical patent/TW200423344A/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0233—Sheets, foils
    • B23K35/0238—Sheets, foils layered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10242—Metallic cylinders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10992—Using different connection materials, e.g. different solders, for the same connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/033—Punching metal foil, e.g. solder foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

200423344 玖、發明說明： 【發明所屬之技術領域】 本發明一般有關半導體元件及製程之領域，更特別有關 積體電路晶片及封裝體的互連構件之結構及方法。 【先前技術】 在積體電路（1C)晶片藉由銲料迴銲以組裝至一諸如基材 或電路板等外部部件之期間及其後、然後在元件操作期 間’半導體晶片與基材之間出現了顯著的溫差及溫度循 環。銲接接點的可靠度受到半導體材料及基材材料的熱膨 脹係數之強烈影f。譬如，梦與FR_4的熱膨膳係數之間具 有大於-個數量級的差異。此差異造成鲜接點必須吸收之 熱力學應力。 因為銲球的共面性問題及難以獲得最有利的高度直徑比 及銲料互連的均勻,f生’而使熱力學應力之困難加劇。這些 困難首先在於銲球附接製程。在—範例中，當銲膏以機具 配送時，冑膏的容積可能改變，故難以控制銲膏的高度。 當使用預先製造的銲料，已經知道難以避免遺漏附接部 位0
因此迫切地需要一種用於製造具均句容積的銲球且將. 輸送到附接部位而不遺漏部位之—貫的低M 法應具有足夠彈性以施加至不同的半導體產品家族及廣，、 不同的設計與製程變化。 ’
並且，文件中的詳細計算且包括銲料連接部的最佳高/ 及谷積及疲勞與裂痕㈣期起點係顯示具有短長度W
O:\88\88887.DOC 200423344 勾寬度之銲料連接邵不利於應力分佈及應變吸收。應力保 持集中在晶片側銲接點之區域中，在此處導致早期的材料 疲勞及裂痕現象。概呈球形的銲料連接部比起長形連接部 更為敏感。 對於球柵陣列型封裝體及晶片尺度封裝體（csp)，再度以 略為修改的形式出現了包含覆晶之製造方法及可靠度問 喊。大部份CSP途徑係以在封裝體外部具有銲料凸塊或銲球 之覆日曰組裝為基礎，以與系統或配線板互為介面。 在銲料迴銲步驟之後，覆晶組裝的晶片及封裝體係時常 在晶片或封裝體及中介層、基材或PCB之間使用一聚合性 底4填料。這些底邵充填材料減輕了熱膨脹係數（CTE)不匹 配所造成之部分熱力學應力。但在處理步驟中，底部充填 很耗時且昂貴，因此不受歡迎。 在過去十年，已經在製造時將元件結構、材料、或處理 步驟實行數種變異，藉以減輕熱力學應力問題。其在成本 或製造流程或材料選擇方面皆具有某些缺陷。 因此已經迫切地需要一種用於製造積體電路晶片及半導 體元件的覆晶組裝件之一貫的低成本方法，其提供了一種 根本的結構性及冶金性之熱力學應力可靠度解決方案。此 万法應具有足夠彈性以施加至不同的半導體產品家族及廣 泛不同的設計與製程變化。最好應採用已經裝設的設備^ 礎來達成這些創新，所以不需要投資新的製造機具。 【發明内容】 本發明的第-實施例包含—種用於形成具均勾容積的銲
O:\88\88887.DOC 200423344 料接觸球及將這些球組裝在一半蝴r曰 iA u ^ ^ "且日曰片的積體電路（1C) 接觸塾^而不遺漏接觸塾之方法。提供_片的銲料材料； 此片的厚度決定了銲球容積的一維度。 進-步提供-用於引導-衝擊工具之二部件式壓模；各 邵件具有-用來匹配IC塾圖案之結構。銲料片夹固在壓模 :件之間。一衝壓工具具有複數個衝墨銷；銷的橫剖面積 決疋了銲球容積的其他維度β銷的分佈方式可匹配電路執 的分佈方式。衝壓工具、具有被夹固的銲料片之壓模、: 半導體晶圓係對準以使各衝壓敎位在多個電路勢的其中 一者上方。工具加壓通過壓模及銲料片以 衝出一小板外，對於各整區域生成一個小板。使== 產生表面式接觸。然後將熱量施加至個別銲料小板及晶圓 以使小板融化。最後，融化的銲料係迴銲，以在各接觸墊 區域形成一銲球。 本發明的方法之一種技術優點係為用於_IC晶圓的所有 銲球在-批次製程中生成、具有相同容積且不會遣漏接觸 塾。此方法具有低成本且很可靠。 本發明的第二實施例中，將此方法施用至批次製程，形 成銲球且將銲球組裝在一半導體封裝體的接觸墊上。本發 明的一技術優點係為此方法可施用至許多家族的表面銲接 封裝體，諸如球柵陣列封裝體、晶片尺度封裝體及晶片尺 寸封裝體。 本發明的第三實施例包含一種具有複數個墊及藉由迴鲜 附接連接至外部部件之不可迴銲的接觸構件之積體電路晶 〇：\88\88887 DOC -8- 200423344 ^廷些接觸構件各具有利於在熱力學應力下吸收應變之 一高度直徑比及均勻的直徑。接觸構件具有位於一^上之 :::表面及位於各端上之一層可迴銲材料。各接觸構件 崎上銲料附接至一晶片接觸墊，而各接觸構件的另一 端可操作以迴銲附接至外部部件。 =度直徑比最好大於或等於丨且構件的直徑料構件整 體高度保持固定^構件最好由—種低模數材料製成；較= 的選擇包括鋁、銅、鎳及其合金。構件的端表面可具：包 括銅、鎳、鈀及其合金等可銲材料構成之—黏附層：各： 件端點上之此層可迴銲材料最好係包含錫及錫合金。對於 許多元件應用而言，選擇可迴銲材料層使得位於面對晶片 心構件端點上的材料比起位於預定附接至外部部件之構件 端點上的材料具有更高的迴銲溫度之方式係為一項優點。 本發明的第四實施例包含一種具有複數個墊及藉由迴銲 附接連接至外部部件之不可迴銲的接觸構件之半導體封裝 體，諸如一球柵陣列或一晶片尺度封裝體。這些接觸構件 各具有利於在熱力學應力下吸收應變之一高度直徑比及均 勻的直徑。接觸構件具有位於各端上之—可鐸表面及位於 各端上之一層可迴鲜材料。各接觸構件在—端上銲料附接 至一晶片接觸墊，而各接觸構件的另—端可操作以迴銲附 接至外部部件。 用於製造不可迴銲的接觸構件及將這些構件組裝在半導 體晶圓的積體電路墊、或半導體元件的封裝體塾上之處理 泥程首先係提供一金屬片，其具有一中心層的不可迴銲金 O:\88\88887 DOC -9- 200423344 選擇片的厚度使其 屬及位於各表面上纟_層彳迴鮮材料 決定待製造構件之高度。 進 步提供 用於引導一衝壓工具之二 部件具有-用來匹配1C塾或封裝體塾的二之=模:各 片2固在壓模部件之間。衝壓工具含有複數個衝壓銷= 接觸塾的分体方^ h佈万切匹配於 Μ工具、具有被夾固的片之壓模、及半導體晶圓（或分 別為封裝體）係對準以使各衝壓銷位於"㈣㈣Μ -者上万。工具加壓通過壓模及片以衝出此片的一構件， 並對於各塾區域生成_個構件。在構件與塾產生接觸之 後’施加熱量直到構件料之間可迴銲材料融化為止。當 溫度再度降魅Φ於迴銲溫度時，各構件變成制地附接 至其各別的接觸塾。 本發明的方法之一種技術優點係為藉由選擇金屬片厚度 及衝壓工具銷直徑來控制連接構件之高度直徑比。所有構 件具有均勻的尺寸。因此可盡量加大熱力學應力的公差。 本發明的另一優點係為在選擇連接構件時可藉由選擇不 可迴銲的金屬片、其可濕潤表面及其可迴銲材料層所以可 取用廣泛的材料變異範圍。 可從本發明較佳實施例的下文描述連同圖式及申請專利 範圍中之新穎特性來得知本發明所代表的技術優點及其型 態0 【實施方式】 O:\88\88887 DOC -10- 200423344 具有示意性質的圖⑴描述用於本發明第一及第二實施 :處里其包含製造具有均勾容積的銲料接觸球及 將k些銲料接觸球組裝在一半導體晶圓的積體電路（⑹接 觸塾上，或者分別將其組裝在一半導體封裝體或一諸如印 T電路板等基材之接觸墊上。本文所界定的接觸球不暗指 銲料接觸部必然為球形。其可能具有各種不同的形式，諸 如半球形或半圓頂形。基於本發明的方法，所有接觸球具 有大致相同的容積及相同高度。 處理流程開始係為一片或帶狀的銲料材料101，如第i圖 所7F銲料材料選自包括下列各物的群組··錫、包括錫/銅、 錫/銦、錫/銀、錫/鉍、錫/鉛等錫合金、銦及傳導性黏質化 合物。片或帶101具有均勻的厚度1〇2。厚度1〇2決定了待製 造銲球的容積之一維度。 銲料片101定位在一壓模之間，如第2圖的示意橫剖視圖 所示。壓模具有包含複數個開口 2〇la之第一部件2〇1，將該 等開口20 la設計為可匹配衝壓工具並操作對於衝壓工具的 銷作為導件之用。壓模的第二部件標為2〇2 ;其面對元件（譬 如晶片、晶圓、封裝體或基材）203的表面2〇3a。複數個接 觸墊203b位於元件（譬如晶片、晶圓、封裝體或基材）2〇3的 表面203a上，已經將該等接觸墊2〇3b製備成為可接受待形 成的球。此製備包括一可銲式接觸表面。 第2圖中亦顯示具有複數個衝恩銷2〇4a之衝壓工具204的 示意橫剖視圖。銷204a的圖案係由壓模的開口 20 la及元件 (譬如晶片、晶圓、封裝體或基材）203的接觸墊203a加以匹 0 \88\88887 DOC -11 - 200423344 配這些銷的檢剖面積係包含可有效決定銲球容積之另兩 維度。衝壓銷可概括稱為柱體，且這些拄體的橫剖面可選 自包括下列各物的群組：圓形、橢圓形、正方形、長方形、 及任何其他的適當組態。 第3圖顯示將銲料片ι〇1夾固於第一壓模部件2〇1與第二 壓模部件202之間的處理步驟。第3圖中進一步顯示將衝壓 工具204、具有位於部件間的被夾固片ι〇1之壓模部件2〇1及 2〇2、及元件（譬如晶片、晶圓、封裝體或基材）2〇3對準以使 各衝壓銷204a定位在數個接觸墊2〇3b的其中一者上方之處 理步驟。 如第4圖所示，下個處理步驟中，衝壓工具2〇4加壓通過 壓楱邵件201及202且經過銲料片1〇1，使得各衝壓銷2〇乜從 片1 〇 1衝製一小板4〇 1。在此處理步驟中，對於元件（譬如晶 片、晶圓、封裝體或基材）2〇3上的各接觸墊區域2〇讣生成 一個小板401。令接觸墊203b皆設有一銲料小板401。 在放大的橫剖視圖中，第5圖顯示已經與接觸墊2〇3b產生 表面接觸後之少量的這些小板4〇丨。可看出，衝壓方法生成 具相等尺寸與容積之銲料小板。高度取決於銲料片101的厚 度102，且面積取決於衝壓柱體204a的橫剖面，已經選擇衝 壓柱體204a的橫剖面使其等於接觸墊2〇扑的面積。 可在壓模及銲料片與元件（譬如晶片、晶圓、封裝體或基 材）203對準之前將銲料助劑施加至接觸墊2〇3b。因此，將 ^ I施加至個別銲料小板及元件（譬如晶片、晶圓、封裝體 或基材）2〇3<後，小板將融化並濕潤接觸墊203b的整體區
O:\88\88887 DOC -12- 200423344 域。此迴銲處理步驟顯示於第6圖中’其中表面張力已經從 融化的銲料形成”球”601(更精確地說，"半圓頂”）。所有球 601大致具有相同的銲料容積及相同的高度6〇la，因為其完 全覆蓋接觸部203b的（相等）面積。 本發明的方法得以製造具有廣泛尺寸範圍之銲球。當體 邵203為一矽晶圓且墊2〇3b為一 1C的接觸墊時，銲”球”高度 一般介於0.1至0.3公厘之間。此組裝件採用覆晶表面銲接方 式。當體部203為一半導體封裝體或一基材時，且墊2〇扑為 封裝體接觸墊或基材接觸墊時，銲”球”高度一般為〇·5公厘 及顯著更大。半導體封裝體包括球栅陣列封裝體、晶片尺 度封裝體、晶片尺寸封裝體、或藉由表面銲接及迴銲材料 組裝至外部部件之任何封裝體。 第7圖的示意橫剖視圖描述將一晶片或封裝體2〇3表面銲 接式組裝在一基材702的接觸塾701上之典型結果。銲，，球 ”601迴銲第二次；在壓力下，其變形成為互連部7〇3的鼓起 形狀，且特徵在於突起中心區7〇3&及較窄的銲接點7〇3b。 具有示意性質的第8A/8B圖至第12圖描述用於本發明第 二及第四實施例之處理步驟，其包含製造不可迴銲的接觸 構件及將這些構件組裝在一半導體晶圓的1(：接觸墊上，或 者分別將其組裝在一半導體封裝體或一諸如印刷電路板等 基材之接觸墊上。 處理步驟開始係為第8 A圖中標為800之層狀的片或帶。此 片具有均勻的厚度801。厚度801決定了待製造構件之高度。 第8B圖的橫剖視圖描述片8〇0的層狀結構。片8〇〇的組成
O:\88\88887 DOC -13- 200423344 物及製造可確保低成本。較厚的中心層81〇由選自包括下列 各物的群組之不可迴銲的金屬製成且最好為低模數材料·· 銘、銅、錄、鈥、叙、鎢、錫、錯及其合金（錫及錯最好只 使用在低於其迴銲溫度的溫度範圍中）。一種較佳的低成本 選擇疋鋁。當層810的金屬為不可銲時，可銲材料的一額外 黏附層811係位於中心層81〇的兩側上。額外金屬選自包括 下列各物的群組：銅、鎳、金、銀、鈀及其合金。相較於厚 的中心層81〇,可銲層811可為薄狀或只是一溢料（fiash)。 片800的最外表面為可迴銲材料的黏附層，可迴銲材料選 自包括下列各物的群組··錫、包括錫/銅、錫/銦、錫/銀、 錫/鉍 '錫/鉛、銦等錫合金及傳導黏性化合物。在一較佳實 施例中，用於與晶片互連之可迴銲層812係比用來將元件附 接至一外部部件的可迴銲層813具有一更高之迴銲溫度。 ▲如第9圖所示，將片8〇〇定位在一具有一第一部件之壓 模之間第部件1具有複數個開口 90 1 a，該等開口 90 1 a 設計成可以匹配衝壓工具及操作作為對於衝壓工具的銷之 導件。壓模的第二部件標為9〇2 ;其面對元件（譬如晶片、 晶圓、封裝體或基材）903的表面9〇3a。複數個接觸墊9〇扑 位於7C件（譬如晶片、晶圓、封裝體或基材）9〇3的表面 上’接觸墊903b由可銲金屬製成並已經製備成為可接受待 形成的連接構件。此製備可包括使助劑沉積。 第9圖中亦顯示具有複數個衝壓銷904a之衝壓工具904的 不思性橫剖視圖。銷9〇4a的圖案係被壓模的開口 90la及元 件（譬如晶片、晶圓、封裝體或基材）9〇3的接觸墊9〇3b予以
O:\88\88887 DOC -14- 200423344
匹配。這些銷的直徑決定了姓制、止k AL 』且仅/天疋了待製造構件之直徑。衝壓銷一 般可稱為柱體，Η ;玄此D触人』生上丨_ k二枉ω的;^ 4面可選自包括下列各物 的群組：圓形、橢圓形不女 U y 正万开/、長万形及任何其他的適 當組態。 、第10圖顯示將片800夾固在第一壓模部件9〇1與第二壓模 4件902之間的處理步驟。第1〇圖進一步顯示將衝壓工具 904、具有夾固在部件間的片8〇〇之壓模部件9〇1及9〇2、及 元件（3如印片、晶圓、封裝體或基材）9〇3對準以使各衝壓 銷904a位於數個接觸墊9〇3b的其中一者上方之處理步驟。 在下個處理步驟中，如第11圖所示，衝壓工具904加壓通 過壓模部件901及9〇2且經過片800,使得各衝壓銷9〇4a從片 800衝製一構件11〇1。在此處理步驟中，對於元件（譬如晶 片、曰εϊ圓、封裝體或基材）9〇3上的各接觸墊區域9〇3b生成 一個構件lioi。令接觸墊903b皆設有一連接構件11〇1。 第12圖以放大的橫剖視圖顯示已經與接觸墊903b產生表 面接觸後之少量的這些連接構件11〇1。可看出，衝壓方法 生成具有相等直徑l101a及高度11〇lb的構件，各構件對於 整體高度具有均勻的直徑。為了在熱力學應力下吸收應 ’支’較佳的咼度直徑比大於或等於1。高度1 1 〇 1 b取決於片 800的厚度801，且直徑1101&取決於衝壓柱體904a的直徑。 構件1101的主要部分是由片中心層81〇的不可迴銲材料（譬 如銘或銅）製成之中心部12〇丨。如果不可迴銲金屬12〇1本質 上不可銲，則可由可銲金屬（譬如銅或金）的一黏附層丨2〇2 來提供構件各端上之可銲表面。層1203及1204由可迴銲材 O:\88\88887 DOC -15- 200423344 料製成。層1204選擇的材料最好係具有比層12〇3選用材料 更同之一迴銲溫度。第12圖中，層1204已經迴銲，藉以將 構件hoi附接至元件（譬如晶片、晶圓、封裝體或基材）9〇3 的接觸墊903b。相反地，層12〇3尚未迴銲且仍可操作以迴 銲附接至外部部件。 可在壓模及片與元件（譬如晶片、晶圓、封裝體或基材） 對準之前將銲料助劑施加至接觸墊9〇3b。因此，將熱量施 加至個別連接構件及元件（譬如晶片、晶圓、封裝體或基材） 又後，層1204將融化並濕潤接觸墊9〇3b的整體區域。此迴 銲處理步驟藉由層1204的鼓起周邊輪廓顯示於第12圖中。 第1 3圖的示意橫剖視圖描述將一晶片或封裝體9〇3覆晶 表面銲接式組裝在一基材1302的接觸墊1301上之典型結 果。將此組裝件加熱至層1203的迴銲溫度，使得層1203的 可迴銲材料融化。在組裝件的輕微壓力下，層丨2〇3變形成 為如第13圖所示略為鼓起的周邊。不同於銲料層12〇3，構 件之不可迴銲的欄具120 1保持不受組裝溫度所改變：均勻 直徑及均勾南度之柱體係定位為相對於基材墊丨3 〇丨平面呈 垂直狀。 現在參照第7圖，在作為範例的一量產元件中，蟄高部7〇5 為180微米’而鼓起邵703a具有270微米的直徑704。此元件 中，元件的（銅製）接觸墊203b具有140微米的直徑706，板的 (銅製）接觸墊7〇1具有175微米的直徑7〇7。板7〇2 一般具有比 元件203更咼的熱膨脹係數。因此，由於在從-4〇至+1 5〇它 的可靠度測試期間或元件操作時經歷了應力，應力係在溫 O:\88\88887.DOC -16- 200423344 度循環期間生成於銲接點上。對於相關的幾何結構，慣量 的計算係顯示出估計之260 · 10E6微米E4。 將此數值與具有第1 3圖的欄形構件之相同元件進行比 較。墊高部1305為180微米，而連接欄具的直徑1304在欄具 全長皆為140微米。元件的接觸墊903b具有140微米的直徑 1306，板的接觸墊1301具有175微米的直徑13〇7。板13〇2通 常具有比元件903更高之熱膨脹係數。因此，由於在從-4〇 至+150 °C的可靠度測試期間或元件操作時經歷了應力，應 力係在溫度循環期間生成於銲接點上。對於相關的幾何結 構，慣量的計算係顯示出估計之18.8 · 10E6微米E4。 此數值是優於第7圖組裝件的計算數值之13倍的改良。對 於可相比較的楊氏模數及相同位移，可將此改良轉換成為 降低至少10倍因數之應力。 雖然已經參照示範性實施例來描述本發明，不應將本文 描述視為限制性質。熟習該技術者可參考本文描述得知示 範性實施例及本發明其他實施例之各種不同修改及組合。 範例中仗片啟始材料在使用位置上衝製複數個具相 等鬲度的不可迴銲性互連部然後在一部件與另一部件組裝 時附接這些互連部之概念係可適用於廣泛的產品範圍。這 些產品特別可出現但不拘限於由多種不同組件構成之電子 板因此，申請專利範圍預定涵蓋了任何此等修改或實施 例0 【圖式簡單說明】 第1至6圖顯示本發明的第一及第二實施例；
O:\88\88887 DOC -17- 200423344 第1圖為一片銲料材料之立體圖； 第2圖為根據本發明進行組裝之複數個分離的部件之示 意橫剖視圖，其中包含銲料片、衝壓工具、二部件式壓模、 及元件（譬如晶片、晶圓、封裝體或基材）； 第3圖為與第2圖相同的部件之示意橫剖視圖，其中銲料 片夾固在壓模的兩部件之間； ，第4圖為與第2圖相同的部件之示意橫剖視圖，其中藉由 衝壓工具從該片衝製銲料小板； 罘5圖為在銲料小板已經&該片衝壓且附接至接觸塾之 後元件（譬如晶片、晶圓、封裝體或基材）的—部分之示意橫 剖視圖； 第6圖為在銲料小板迴銲之後與第5圖相同之元件（譬如 晶二、晶圓、封裝體或基材）的部分之示意橫剖視圖； 、弟7圖為在兀件（譬如晶彳、晶圓、封裝體或基材）迴鲜附 接至夕卜邵邵件上之後銲接點的示意橫剖視圖； 第8至12圖顯示本發明的第三及第四實施例； 圖為根據本發明之—組合片的附接材料之立體圖； 第8B圖為根據本發明之^片的附接材料之示意橫剖視 圖 第9圖為根據本發明進行組裝之複數個分離的部件之示 意橫剖視圖，其中包含組合片、衝壓工具、二部件式壓模、 及疋件（譬如晶片、晶圓、或封裝體、或基材）； 第1〇圖為與第9圖相同的部件之示意橫剖視圖，其中組合 片夾固在壓模的兩部件之間·，
O:\88\88887 EXDC -18- 200423344 第11圖為與第9圖相同的部件之示意橫剖視圖，其中藉由 衝壓工具從該片衝製組合式欄具； 第圖為在組合式欄具已經從該片衝壓且附接至接觸墊 《後;^件（譬如晶片、晶圓、或封裝體、或基材）的—部分之 示意橫剖視圖； 第13圖為在元件（譬如晶片、晶圓、封裝體或基材）迴銲附 接至-外部部件上之後利用組合式攔具之互連部的示意橫 剖視圖。 【圖式代表符號說明】 101 102, 801 201， 901 201a，901a 202, 902 203, 903 203a，903a 銲料片 厚度 第一壓模部件 開口 第二壓模部件 元件（譬如晶片、ΕΪ m 日3囡、封裝體或基材） 表面 203b，701，903b，1301 接觸 204, 904 衝壓工具 204a，904a 衝壓銷 401 銲料小板 601 銲球 601a， 1101b 高度 702, 1302 基材 703 互連部 O:\88\88887 DOC -19- 200423344 703a 突起中心區 703b 較窄的銲接點 704, 706, 1101a， 1304, 1306, 1307 705, 1305 墊高部 800 片 810 中心層 811 可銲層 812, 813 可迴銲層 1101 連接構件 1201 中心部 直徑 1202 黏附層 1203, 1204 層 O:\88\88887 DOC -20-

Claims (1)

  1. 拾、申請專利範圍： 1 · 一種積體電路晶片，其具有複數個墊及藉由迴銲附接連 接至外部部件之不可迴銲的接觸構件，包含： 各該等構件具有利於在熱力學應力下吸收應變之一高 度直徑比及大致均勻的直徑； 孩等構件具有位於各端上之一可銲表面及位於各端上 之一層可迴銲材料；及 各肩等構件在一端上銲料附接至一接觸塾，各構件的另 一端可操作以迴銲附接至外部部件。 •如申Μ專利範圍第i項之晶片，其中該高度直徑比大於 或等於1。 3·如申請專利範圍第丨項之晶片，其中該等構件由選自包 括下列各物的群組之低模數材料製成：鋁、銅、鎳、鈦、 叙、鎢、錫、鉛及其合金。 4.如申請專利範圍第丨項之晶片’其中對於該面對晶片之 構件端戶斤選㈣可迴銲材料❹有比對於該預定附接 至外邵邵件之構件端所選用的可迴銲材料更高之一迴 銲溫度。 5·種半導體封裝體，其具有複數個塾及藉由迴鲜附接連 接至外部部件之不可迴銲的接觸構件，包含： 各^等構件具有利於在熱力學應力下吸收應變之一高 度直徑比及大致均句的直徑； 各該等構件迴銲附接至一各別的連接墊；及 各該等構件在其未附接端上具有—層可迴銲材料，俾使 O:\88\88887 D〇c 200423344 該構件保持可操作以迴銲附接至外部部件。 6·如申請專利範圍第5項之封裝體，其 直徑比大於或等於丨。 μ ”冓件的高度
    由選自 錄、欽 如申請專利範圍第5項之封裝體，其中 包括下列各物的群組之低模數材料製成洶、銅、 鋰、鎢、錫、鉛及其合金。 8.如申料利範圍第5項之封裝體，其中對於該面對封裝 體心構件端所選用的可迴鮮材料係具有比對㈣預定 附接至外部部件之構件端所選用的可迴鮮材料更高之 一迴銲溫度。 9· 一種用於形成連接構件及將該等構件組裝在一半導體 兀件上的接觸墊上之方法，包含下列步驟： 才疋供一金屬片，其具有一中心層的一不可迴銲金屬及 黏附至各表面之一層可迴銲材料，該片的厚度決定了該 等連接構件的高度； 提供一用於引導一衝壓工具之二部件式壓模，各部件 具有一結構以匹配該等接觸墊的圖案； 將該片定位及夾固在該等壓模部件之間； 提供一具有複數個衝壓銷之衝壓工具，該等銷的直徑 決定了該等連接構件的直徑，該等銷的分佈方式匹配於 該接觸整*的分佈方式； 對準該工具、該具有夾固在部件間的片之壓模及該半 導體元件’以使各衝壓銷定位在該等接觸墊的其中一者 上方； O:\88\88887 DOC -2- 200423344 將該工具加壓通過該壓模及該片，以使各衝壓銷從該 片衝製一連接構件，對於各接觸墊生成一連接構件； 使該等構件與該等墊產生表面接觸； 將熱量施加至該等個別的構件及該元件以融化該等 構件與該等墊之間的可迴銲材料；及 將溫度冷卻至低於該迴銲溫度，藉此使各構件變成穩 固地附接至其各別的墊。 1 〇.如申請專利範圍第9項之方法，其中將該等衝壓銷定型 為具有選自包括下列各物的群組之一橫剖面之柱體：圓 形、橢圓形、正方形及長方形。 O:\88\88887.DOC -3-
TW092130857A 2002-12-31 2003-11-04 Composite metal column for mounting semiconductor device TW200423344A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43736602P 2002-12-31 2002-12-31
US43759302P 2002-12-31 2002-12-31

Publications (1)

Publication Number Publication Date
TW200423344A true TW200423344A (en) 2004-11-01

Family

ID=32659480

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092130857A TW200423344A (en) 2002-12-31 2003-11-04 Composite metal column for mounting semiconductor device

Country Status (5)

Country Link
US (1) US7125789B2 (zh)
EP (1) EP1443548A3 (zh)
JP (1) JP2004214676A (zh)
KR (1) KR20040062411A (zh)
TW (1) TW200423344A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448872A (zh) * 2014-08-29 2016-03-30 展讯通信（上海）有限公司 一种改进的芯片连接结构及其制作工艺

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US6929170B2 (en) * 2003-09-30 2005-08-16 Ted Ju Solder deposition method
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
JP4576270B2 (ja) * 2005-03-29 2010-11-04 昭和電工株式会社 ハンダ回路基板の製造方法
WO2007007865A1 (en) 2005-07-11 2007-01-18 Showa Denko K.K. Method for attachment of solder powder to electronic circuit board and solder-attached electronic circuit board
US20090041990A1 (en) * 2005-09-09 2009-02-12 Showa Denko K.K. Method for attachment of solder powder to electronic circuit board and soldered electronic circuit board
KR20090039740A (ko) * 2006-08-03 2009-04-22 쇼와 덴코 가부시키가이샤 땜납 회로 기판의 제조 방법
EP2206145A4 (en) * 2007-09-28 2012-03-28 Tessera Inc FLIP-CHIP CONNECTION WITH DOUBLE POSTS
SG152101A1 (en) 2007-11-06 2009-05-29 Agency Science Tech & Res An interconnect structure and a method of fabricating the same
JP2009158593A (ja) * 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US8178970B2 (en) * 2009-09-18 2012-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strong interconnection post geometry
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8501615B2 (en) * 2011-06-15 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal bump formation
EP2800129A4 (en) * 2011-12-27 2015-07-08 Panasonic Ip Man Co Ltd CONNECTION STRUCTURE
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9842819B2 (en) 2015-08-21 2017-12-12 Invensas Corporation Tall and fine pitch interconnects
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
CN111394612B (zh) * 2020-04-29 2023-10-20 西安同为工业技术有限公司 一种基于十字或雪花孔型的合金材料芯片的防垢装置
US20220246543A1 (en) * 2021-01-29 2022-08-04 Raytheon Company Composite structure for image plane normalization of a microelectronic hybrid device
CN114986012A (zh) * 2022-06-06 2022-09-02 中国科学院宁波材料技术与工程研究所 复合柱状软焊材料及其制备方法与应用

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
JP2792532B2 (ja) 1994-09-30 1998-09-03 日本電気株式会社 半導体装置の製造方法及び半導体ウエハー
US5736074A (en) * 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
WO1997019466A1 (en) 1995-11-22 1997-05-29 Fry's Metals, Inc. Method and apparatus for forming solder bumps on a substrate
US6249963B1 (en) 1996-11-27 2001-06-26 Texas Instruments Incorporated System and method for coupling conductive pellets to a component of an integrated circuit
KR100278219B1 (ko) * 1997-06-18 2001-01-15 클라크 3세 존 엠. 플립칩과볼그리드어레이(bga)를상호접속시키는방법
US6550666B2 (en) * 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
US7087458B2 (en) * 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448872A (zh) * 2014-08-29 2016-03-30 展讯通信（上海）有限公司 一种改进的芯片连接结构及其制作工艺

Also Published As

Publication number Publication date
KR20040062411A (ko) 2004-07-07
US7125789B2 (en) 2006-10-24
EP1443548A2 (en) 2004-08-04
US20040135251A1 (en) 2004-07-15
EP1443548A3 (en) 2004-08-18
JP2004214676A (ja) 2004-07-29

Similar Documents

Publication Publication Date Title
TW200423344A (en) Composite metal column for mounting semiconductor device
US6825552B2 (en) Connection components with anisotropic conductive material interconnection
US5558271A (en) Shaped, self-aligning micro-bump structures
US6221691B1 (en) Method and system for attaching semiconductor dice to substrates
US6740960B1 (en) Semiconductor package including flex circuit, interconnects and dense array external contacts
EP1386356B1 (en) Fluxless flip chip interconnection
TW546693B (en) Hollow solder structure having improved reliability and method of manufacturing the same
US6348399B1 (en) Method of making chip scale package
EP1381081A1 (en) Radiation type bga package and production method therefor
US20020019076A1 (en) Method for fabricating semiconductor package including flex circuit,interconnects and dense array external contact
US20090289360A1 (en) Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing
JP3450236B2 (ja) 半導体装置及びその製造方法
JP2010541244A (ja) 二重ポスト付きフリップチップ相互接続
KR20120116373A (ko) 반도체 장치의 제조 방법
US20060012055A1 (en) Semiconductor package including rivet for bonding of lead posts
US7550852B2 (en) Composite metal column for mounting semiconductor device
US20090080169A1 (en) Method for forming BGA package with increased standoff height
JPH07235618A (ja) 多端子半導体パッケージ
TWI284376B (en) Bump manufacturing method
TW533556B (en) Manufacturing process of bump
JP3585806B2 (ja) ピン付き配線基板
JPH11112133A (ja) はんだバンプの平坦化方法
JP3553246B2 (ja) Ｉｃカード用ｉｃモジュールの製造方法、ｉｃモジュールの製造方法
JP4084984B2 (ja) 半導体装置の製造方法
JPS60130132A (ja) 半導体装置の製造方法