TW200421537A - Semiconductor device contact process and structure - Google Patents

Abstract

A kind of semiconductor device contact process and structure are revealed in the present invention. The semiconductor device contains the first conduction type base region formed on a substrate. The manufacturing process includes the followings: forming a heavily doped first shallow layer with the first conduction type on the surface of the substrate; depositing an insulation layer on the first shallow layer; etching the insulation layer and the first shallow layer to divide the first shallow layer to form contact hole where high temperature process is conducted to drive in for increasing the longitudinal depth of the first shallow layer; implanting a heavily doped second shallow layer with the second conduction type in the contact hole where a metal layer is deposited in the contact hole to have electric connection with the first shallow layer and the second shallow layer.

Description

200421537 V. Description of the invention (1) I- _ Technical field to which the invention belongs. The present invention relates to a contact process and structure of a semiconductor element, in particular to a contact process and structure of a power semiconductor element. The traditional power semiconductor contact manufacturing process of the prior art is quite simple. The main purpose is to reduce the contact resistance between the source material and the metal. Therefore, a high concentration of source N + implantation and P + contact implantation are required to obtain good results. Ohmic contact, so the mask defining the N + region of the source and the mask defining the contact opening must overlap the layout to get a good ohmic contact. The first diagrams (a) to (g) are schematic diagrams of the source contact process of a conventional N-type trench power metal-oxide half-field summer effect transistor. As shown in the first figure (a), the power metal-oxide half field effect transistor includes an N-epitaxial layer 12 on an N + substrate 10 ′, and a gate electrode 16 and P are formed on the N-epitaxial layer 12. Type base region 14, the process includes using a photomask 20 to define and implant to form the source N + region 18, such as implanting arsenic (As), and then using high temperature drive (dr ive in) to diffuse the N + region 18, as shown in the first figure (b). Next, as shown in the first figure (c), an insulating layer 22 is deposited and annealed. Preferably, the insulating layer 22 is formed by NSG / BPSG, and then the insulating layer 2 is defined and etched by a photomask 24. 2 to form a contact hole 26, as shown in the first figure (d). Thereafter, the P + region 28 is implanted from the contact opening 26, for example, boron difluoride (BF2) is implanted, as shown in the first figure (e). As shown in Figure (f), annealing treatment and blanket etching are performed to make the insulating layer 22 smooth, and the N + region 18 and the P + region are removed.

Page 5 200421537 V. Description of the invention (2) The surface of domain 28. Finally, metal layers 30 and 32 are deposited as source and drain electrodes, as shown in the first figure (g). In such a power semiconductor structure, since the lateral diffusion length of the N + junction is equivalent to the depth of the junction, the actual N + region length will be much larger than the length defined by the source N + mask. For power semiconductor devices, in addition to limiting the size of the element unit, the longer source N + length will reduce the current carrying capacity of the device itself, resulting in, for example, trench power metal-oxide semiconductor field-effect transistors. Secondary breakdown and latch-up effect of the insulated gate bipolar transistor (IG β τ), etc. SUMMARY OF THE INVENTION The process and the structure withstand current are deposited on the surface of the base area based on the degree of formation, The deposited metal layer is on the contact hole layer. According to the present invention, a half-piece contains a first purpose on a substrate, in order to reduce the single capacity of the component. According to the present invention, a half-substrate first forms a heavy layer. The doped first edge layer is etched, and the high-temperature contact hole is implanted. One is to propose a semiconductor element contact element size and increase the cell density of the element and a conductor element contact process. The semiconductor element conductivity type base region. The process A conductive first shallow layer, and the upper edge layer and the first shallow layer to divide the first approach to deepen the vertical direction of the first shallow layer Deep heavily doped shallow second conductive type of a second, electrically connected to the first and second shallow shallow ί ί member contact structure, the semiconductor region i of the conductive element, the contact structure comprising

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A heavily doped first conductive type covers the first shallow layer; a contact opening is heavily doped with a second conductive type electrically connected to the second shallow layer and aligned with the contact opening. A shallow layer is on the base region; an insulating layer covers the insulating layer and the first shallow layer; a layer is on the base region; and a metal layer is a shallow layer and a second shallow layer; wherein the first embodiment

Maybe, ϊ Ξ: (two Lg) is a power metal-oxygen half-field effect electric power according to the present invention. As shown in the second figure *, the power oxygen half field effect transistor of the present invention includes an N-epitaxial layer 36 on an N + substrate 34, and a gate electrode 40 and a p-type are formed on the N-epitaxial layer 36. Base region 38. The process of the present invention includes implanting an N + region 42 into the P-type base region 38, such as implanting arsenic (As). The N + region 42 is a shallow layer. The implantation of the N + region 42 includes vertical and oblique. Angle implantation of the "better" oblique angle 45 degrees is implanted into the N + region 4 2 to form a cell-like appearance 4 4 at the edge of the gate 40. Next, as shown in the second figure (b), an insulating layer 46 is deposited on the N + region 42 and annealed. Preferably, the insulating layer 46 is formed of NSG / BPSG. As shown in the second figure (c), the insulating layer 46 is etched, and the N + region 42 is divided to form a contact hole 48 by over etching, and the N + region 42 is etched to a thickness of about 100 Angstroms ( A), as shown in the second figure (d). In order to improve the subsequent metal deposition quality, the insulation layer 46 after the button must be as smooth as possible. Therefore, the insulation layer 46 is first made a surplus. Wet etch or isotropic etch, followed by dry etch or anti-isotropic etch to divide the N + region into 42 points.

200421537 V. Description of the invention (4) Cutting. In order to remove the oxide on the surface of the base region 38, it will be overetched for a certain period of time when it is etched to the surface of the base region 38. Therefore, the base region 38 is etched with a certain thickness. The region 42 is a shallow layer, so the N + region 42 can be divided using this over-etching without changing the etching machine or gas. As shown in the second figure (e), a pad oxide layer 50 is deposited on the base region 38 from the contact hole 48. The pad oxide layer 50 grows the oxide layer at a low temperature to about 200 angstroms (A). When the N + region 42 is driven at a high temperature, a high concentration of phosphorus impurities diffuse from the N + region 4 2 into the air, which will reduce the N + concentration in future contact with the metal and increase the contact resistance value. The pad oxide layer 5 can prevent this. diffusion.

As shown in the second figure (f), after driving the N + region 42 at a high temperature to diffuse the N + region 42, the pad oxide layer 50 is removed. In different embodiments, a hafnium oxide layer 50 may be left as a sacrifice for subsequent processes, and finally removed with a blanket surface for a while. After being driven in at a high temperature, the insulating layer 46 becomes smooth. As shown in the second figure (g), a P + region 52 is implanted on the p-type base region 38, for example, boron difluoride is implanted. After the P + region 52 is implanted, it is annealed and carpeted. As shown in the second figure (h), the surface of the p + region 52 is removed, and the thickness of the blanket etched P + region 52 is about 500 angstroms (a). Finally, metal layers η and 56 are deposited as source and drain electrodes as shown in the second figure (i). The present invention can spread the length of the source electrode laterally in the existing process, and the secondary collapse effect of the transistor can be reduced. It can also reduce the density of the element unit size and save a definition of light.

, Photomask and metal deposition ability to reduce the trench power metal-oxide half field effect edge gate bipolar transistor latch effect, increase the cover per inch area of the component to reduce manufacturing costs. The description in the examples is for clarification

Page 8 200421537 V. Description of the invention (5) Purpose, without intending to limit the present invention to exactly the disclosed form. Modifications or changes are possible based on the above teaching or learning from the embodiments of the present invention. In order to explain the principle of the present invention and allow those skilled in the art to use the present invention in practical applications to select and describe in various embodiments, the technical idea of the present invention is intended to be determined by the scope of the following patent applications and their equivalents.

Page 9 200421537 Schematic description For those skilled in the art, from the detailed description made below, with the accompanying drawings, the present invention will be more clearly understood, its above and other objectives and advantages will be It becomes more obvious, in which: the first diagrams (a) to (g) are schematic diagrams of the source contact process of a conventional N-type trench power metal-oxide half-field effect transistor; and the second diagrams (a) to ( g) is a schematic diagram of a source contact process of a power metal-oxygen half field effect transistor according to the present invention. Drawing number comparison table: 10 N + substrate _ 12 N-epitaxial layer 14 P-type base region 16 gate 18 N + region 20 photomask 22 insulation layer 24 photomask 26 contact hole 2 8 P + region 3 0 metal layer 32 metal Layer φ 34 N + substrate 36 N-epitaxial layer 38 P-type base region

Page 10 200421537 Brief description of the diagram 40 Gate 42 N + area 44 Cell appearance 46 Insulating layer 48 Contact hole 50 Pad oxide layer 52 P + area 54 Metal layer 56 Metal layer

Claims (1)

200421537 VI. Application for Patent Scope 1. A semiconductor device contact process comprising a base region of a first conductivity type on a substrate. The process includes the following steps: A heavily doped first conductivity type is formed on the surface of the base region. A first shallow layer; depositing an insulating layer; etching the insulating layer and the first shallow layer to divide the first shallow layer and forming a contact hole; high temperature entering to deepen the longitudinal depth of the first shallow layer; A second shallow layer of heavily doped second conductivity type is implanted in the contact hole; and a metal layer is deposited on the contact hole to electrically connect the first shallow layer and the second shallow layer. Wherein the first shallow layer is formed by ion implantation, the insulating layer is etched at an oblique angle, the first shallow layer is etched, and the plasma is etched. 2. The process layer according to the first scope of the patent application uses ion implantation. Into. 3. If the process of item 2 of the scope of patent application includes oblique angle implantation. 4. The process angle of item 3 in the scope of patent application is about 45 degrees. 5. The process of item 1 in the scope of patent application is wet etching. 6. If the process of item 1 of the scope of patent application is applied, the layer is plasma etched. 7. If the process of item 6 of the patent application is applied, overly etch directly downward to etch away a thickness of the base region. 8. If the process of item 1 of the scope of patent application is applied, it also includes the high temperature trend Page 12 200421537 VI. When the scope of patent application has previously entered the high temperature on the surface of the first shallow layer, the second shallow layer is 0. 9. If the patent application scope of the eighth layer is to grow a thin layer of oxygen using low temperature 1 0 For example, the annealing layer is applied to the insulating layer after the patent application. 11. If the second shallow layer in the scope of patent application is applied for annealing treatment. 1 2. If the second metal layer is applied before the second metal layer is applied for the patent, the second is left. 1 3. A semiconductor element is connected to a substrate of the first conductivity type, and a heavily doped one of the first conductivity type is covered with an insulating layer covering the first. A shallow contact hole passes through the insulating one heavily doped metal layer of a second conductivity type on the contact hole layer; wherein the second shallow layer is aligned with the 14th, as in the scope of the patent application, the first has a depth greater than the second shallow Layer 15: If the scope of patent application, the first and second shallow layers do not overlap each other. A pad oxide layer is formed to prevent diffusion of impurities of the first conductivity type into the air, wherein the pad oxide layer is formed. The process of item 1 is further included in the process of depositing the item of 1, and the process of implantation 1 is further included in the deposition shallow layer. A contact structure comprising the semiconductor region, the contact structure comprising: a first shallow layer on the base region; a layer; a layer and a first shallow layer; a second shallow layer on the base region; and electrically connecting the first layer A shallow and second shallow contact opening. 1 The depth of the structure of 3 items. 1 item 3 structure wherein the first shallow layer wherein the first shallow layer Page 13