TW582094B - Semiconductor device contact process and structure - Google Patents

Abstract

A kind of semiconductor device contact process and structure are revealed in the present invention. The semiconductor device contains the first conduction type base region formed on a substrate. The manufacturing process includes the followings: forming a heavily doped first shallow layer with the first conduction type on the surface of the substrate; depositing an insulation layer on the first shallow layer; etching the insulation layer and the first shallow layer to divide the first shallow layer to form contact hole where high temperature process is conducted to drive in for increasing the longitudinal depth of the first shallow layer; implanting a heavily doped second shallow layer with the second conduction type in the contact hole where a metal layer is deposited in the contact hole to have electric connection with the first shallow layer and the second shallow layer.

Description

The technical field to which the invention belongs is related to the semiconductor element contact process and force rate + conductor element contact process and structure. The structure, especially the prior art low-source contact process is quite simple. The main purpose is to reduce the contact resistance between the material and the metal. Therefore, it must be obtained by high-intensity source N + implantation and ρ + contact implantation. Good ohmic contact, so the mask of the N + region of the sense source and the mask defining the contact opening must be laid out in order to obtain a good ohmic contact.

The first diagrams (a) to (g) are schematic diagrams of a source contact process of a conventional N-type trench power metal-oxide half-field effect transistor. As shown in the first figure (a), the power metal-oxide half field effect transistor includes an N-stupid layer 12 on an N + substrate 10, and a gate 16 and a P-type are formed on the N-stupid layer 12 The base region 14, the process includes the use of a mask 20 to define and implant to form N + regions 18 of the source, such as arsenic (As) implantation, and then drive in to diffuse the N + region 18, As shown in the first figure (b).

Next, as shown in the first figure (c), an insulating layer 22 is deposited and annealed. Preferably, the insulating layer 22 is formed by NSG / BPSG, and then the insulating layer 2 is defined and etched by a photomask 24. 2 to form a contact hole 26, as shown in the first figure (d). Thereafter, a P + region 28 is implanted from the contact hole 26, such as boron difluoride (BF2), as shown in the first figure (e). As shown in the first figure (f), annealing treatment and blanket etching are performed to make the insulating layer 22 smooth, and the N + region 18 and the P + region are removed.

Page 5 582094 V. Description of the invention (2) Surface of domain 28. Finally, a metal layer is deposited and used as the source and anode, as shown in the first figure (g). In such a power semiconductor structure, since the lateral expansion of the N + junction is equivalent to the depth of the junction, the actual N + region length will be much larger than the length defined by the N + mask. For power semiconductor devices, in addition to limiting the reduction in the size of the element unit, the source N + length lowers the current carrying capacity of the device itself, causing, for example, the second breakdown of the trench power gold field-effect transistor and the insulation gate double Polarity transistor (IGBT) latch effect (latch_up), etc. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor device process and structure, so as to reduce the size of the device unit and increase the capacity of the device unit to withstand current. According to the present invention, a semiconductor element contact process includes the base region of a first conductivity type on a substrate. The process includes forming a first shallow layer of heavily doped first conductivity type on the surface of the base region, and An insulating layer is deposited, the insulating layer and the first shallow layer are etched to divide the shallow layer to form a contact hole, and a high temperature tends to deepen the depth of the first shallow layer. A heavily doped second conductive layer is implanted in the contact hole. The second shallow-deposited metal layer is electrically connected to the first shallow layer and the first layer at the contact opening. According to the present invention, a semiconductor element contact structure includes a semiconductor device having a first conductive type base region on a substrate, and the contact structure has a much larger electrical dissipation than a latching system and a voxel element with a long source that reduces oxygen. The first deep layer above, the two shallow voxels include

582094 5. Description of the invention (3) A first shallow layer heavily doped with a first conductivity type is on the base region; an insulating layer covers the first shallow layer; a contact hole passes through the insulating layer and the first shallow layer; A second shallow layer of heavily doped second conductivity type is on the base region; and a metal layer is electrically connected to the first shallow layer and the second shallow layer at the contact opening; wherein the second shallow layer is aligned with the contact Hole. Embodiments The second figures (a) to (g) are schematic diagrams of a source contact process of a power metal-oxygen half field effect transistor according to the present invention. As shown in the second figure (a), the power metal-oxide half-field effect transistor of the present invention includes an N_ epitaxial layer 36 on an N + substrate 34, and a gate electrode 40 and P-type base region 38. The process of the present invention includes implanting a N + region 42 in the P-type base region 38, for example, implanting Shi Shen (As), the N + region 42 is a shallow layer, and the implantation of the N + region 42 includes vertical And oblique angle implantation, preferably, the N + region 42 is implanted at an oblique angle of 45 degrees to form a cellular appearance 44 at the edge of the gate 40. Next, as shown in the second figure (b), an insulating layer 46 is deposited on the N + region 42 and annealed. Preferably, the insulating layer 46 is formed by NSG / BPSG. As shown in the second figure (c), the insulating layer 46 is etched, and the N + region 42 is divided to form a contact hole 48 by over etching, and the N + region 42 is etched to a thickness of about 1,000 angstroms (A). As shown in the second figure (d). In order to improve the subsequent metal deposition quality, the insulating layer 46 after the engraving must be as smooth as possible. Therefore, the insulating layer 4 6 is first etched (wet etch or isotropic etch). Dry etch or anti-isotropic etch to divide the N + region by 42 points

Page 7 582094 V. Description of the invention (4) Cutting. In order to remove the oxide on the surface of the base region 38, it will be overetched for a certain period of time when it is etched to the surface of the base region 38, so the base region 3 8 is etched to a certain thickness. Since the N + region 42 is a shallow layer, the N + region 42 can be divided using this over-etching without changing the etching machine or gas. As shown in the second figure (e), a pad oxide layer 50 is deposited on the base region 38 from the contact hole 48. The pad oxide layer 50 grows the oxide layer at a low temperature to about 200 angstroms (A). When the N + region 42 is driven at a high temperature, a high concentration of phosphorus impurities diffuse from the N + region 4 2 into the air, which will reduce the N + concentration in future contact with the metal and increase the contact resistance value. The pad oxide layer 5 can prevent this. diffusion. As shown in the second figure (f), after driving the N + region 42 at a high temperature to diffuse the N + region 42, the pad oxide layer 50 is removed. In different embodiments, an oxide layer 50 may be left as a sacrifice for subsequent processes, and finally removed with a blanket surface. After being driven in at a high temperature, the insulating layer 46 becomes smooth. As shown in the second figure (g), a p + region 52 is implanted on the p-type base region 38, for example, boron difluoride is implanted. After the P + region 52 is implanted, after annealing and blanket etching, as shown in the first figure (h), the surface of the P + region 52 is removed. Finally, metal layers 54 and 56 are deposited as source and drain electrodes as shown in the second figure (i). The invention can eliminate the length of the lateral diffusion of the source under the existing process, photomask and metal deposition capability, and can reduce the secondary collapse effect of the trench power metal-oxide half field effect transistor and the latching of the insulating gate bipolar transistor Effect, it can further reduce the size of the element unit, increase the unit density of the element per inch area, and save the definition of a mask, reducing the manufacturing cost. The foregoing description of the preferred embodiment of the present invention is for the purpose of illustration

582094 V. Description of the invention (5) Purpose, without intending to limit the present invention to exactly the disclosed form. Modifications or changes are possible based on the above teachings or learning from the embodiments of the present invention. The embodiments are intended to explain the present invention. The principle of the invention and let those skilled in the art use various embodiments to select and describe the invention in practical applications. The technical idea of the invention is intended to be determined by the scope of the following patent applications and their equality.

Page 582094 Brief description of the drawings For those skilled in the art, the present invention will be more clearly understood from the following detailed description and accompanying drawings, and the above and other objects and advantages will become It is more obvious, in which: the first diagrams (a) to (g) are according to the conventional N-type trench power metal-oxide half field effect transistor source contact process, and the second diagrams (a) to (g) ) Is a schematic diagram of a source contact process of a power metal-oxide half-field effect transistor according to the present invention. Drawing number comparison table: 10 N + substrate 12 N-epitaxial layer 14 P-type base region 16 gate 18 N + region 20 mask 22 insulation layer 24 mask 2 6 contact opening 28 P + region 3 0 metal layer 32 metal layer 34 N + Substrate 3 6 N-stupid layer 38 P-type base region

Page 10 582094 Brief description of the diagram 40 Gate electrode 42 N + region 44 Cell appearance 46 Insulation layer 48 Contact hole 50 Pt oxide layer 52 P + region 54 Metal layer 56 Metal layer

Claims (1)

582094 VI. Application for Patent Scope 1. A semiconductor device contact process comprising a base region of a first conductivity type on a substrate, the process including the following steps: forming a heavily doped first conductivity type on the surface of the base region A first shallow layer; depositing an insulating layer; etching the insulating layer and the first shallow layer to divide the first shallow layer and forming a contact hole; high temperature entering to deepen the longitudinal depth of the first shallow layer; A second shallow layer of heavily doped second conductivity type is implanted in the contact hole; and a metal layer is deposited on the contact hole to electrically connect the first shallow layer and the second shallow layer. 2. For the process of claim 1 in the scope of patent application, wherein the first shallow layer is formed using ion implantation. 3. For the process of applying for item 2 of the patent scope, the use of ion implantation includes oblique implantation. 4. If the process of item 3 of the scope of patent application is applied, the angle of the oblique implantation is about 45 degrees. 5. The process of item 1 in the scope of patent application, wherein the insulating layer is etched using wet etching. 6. The process of item 1 in the scope of patent application, wherein the first shallow layer is etched using plasma etching. 7. The process of item 6 in the scope of patent application, wherein the plasma etching is over-etched vertically downward to etch away a thickness of the base region. 8. If the process of item 1 of the scope of patent application is applied, it also includes the high temperature trend Page 12 582094 VI. When the scope of the patent application has previously entered the high temperature on the surface of the first shallow layer, the second shallow layer is 0. 9. If the 8th layer of the patent scope is used to grow a thin layer of oxygen at low temperature 1 0 For example, the annealing layer is applied to the insulating layer after the patent application. 11 1. If the second shallow layer in the patent application scope is subjected to annealing treatment. 1 2. If the metal layer is applied before the second metal layer is applied, the second etching is performed on the blanket. 1 3. A semiconductor element is connected to a substrate of the first conductivity type, and a heavily doped one of the first conductivity types is used to cover the first shallow layer. A contact hole passes through the insulating and heavily doped metal layer of a second conductivity type on the contact hole layer; wherein the second shallow layer is aligned with the 14, for example, the scope of the patent application has a depth greater than the second shallow layer 1 5. If the first and second shallow layers of the scope of patent application do not overlap each other. A pad oxide layer is formed to prevent diffusion of impurities of the first conductivity type into the air, wherein the pad oxide layer is formed. The process of item 1 is further included in the process of depositing the item of 1, and the process of implantation 1 is further included in the deposition shallow layer. A contact structure comprising the semiconductor region, the contact structure comprising: a first shallow layer on the base region; a layer; a layer and a first shallow layer; a second shallow layer on the base region; and electrically connecting the first layer A shallow and second shallow contact opening. Structure of item 13, wherein the depth of the first shallow layer. 1 item 3 structure, wherein the first shallow layer