TW200418171A - Flash memory cell with unique split programming and reading channel - Google Patents

Abstract

The present invention provides a flash memory cell with unique split programming and reading channel. It includes a substrate, a floating gate, a control gate, a source, an isolation layer, and a first and second drain. The floating gate is disposed on the substrate. The control gate is disposed on the floating gate. The source is in the substrate and disposed on a first side of the floating gate. The isolation layer is in the substrate and isolates the first and second drain on a second side of the floating gate from each other. The width of the floating gate near the first drain is larger than that near the second drain while the width of the control gate near the first drain is smaller than that near the second drain.

Description

200418171

FIELD OF THE INVENTION The present invention relates to a flash memory, and more particularly to a flash memory with separate write and read channels, which can avoid write interference after long-term use ( increased pro gram disturbance) with better endurance. In the prior art, a nonvolatile semiconductor device with a flash memory unit erases and writes data electronically, and can even save data without a power supply. Therefore, such non-volatile semiconductor devices are widely used in many different applications. Taking a common NOR-type non-volatile semiconductor device as an example, it usually has a plurality of memory cells connected in parallel to a bit line, and between the memory cells; and between the pole and the source only Connect a transistor. This structure can increase the current of the memory cell and allow fast operation. Because these memory cell lines are connected in parallel to a bit line, when reading a selected memory cell, other memory cells connected to the same bit line with that memory cell are likely to accidentally erase data. Read interference (re addisturbance) phenomenon. In addition, if the threshold voltage of the transistor in the memory cell is reduced due to some factors, or even lower than the control gate potential of the unselected memory cell, the above-mentioned reading interference phenomenon will also occur. In order to remove the phenomenon of read interference, a non-volatile semiconductor device will add an additional transistor structure to form a memory cell with two transistors, which is commonly known as flash memory. However in one

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 5 200418171 V. Description of the invention ⑵ '~ " ----- The use of two transistors in a memory cell consumes a lot of circuit area and is not good for the chip. Miniature. Many types of non-volatile semiconductor devices currently use different structures to solve the problem of excessive circuit area. One example is a split gate semiconductor device. In this device, word lines (ie, selection gates and control gates) are formed above a floating gate. The figure shows the structure of such a device. In the first figure, the floating gate electrode 14 is formed on the substrate 10, and an insulating layer 12 is located between the floating gate electrode 14 and the substrate 1 (). The floating terminal 14 is composed of a polycrystalline silicon layer. Another insulating layer is formed on the floating gate electrode 14, and the substrate is also provided with a through-insulation layer 18 for erasing data. The through-insulation layer 18 is connected to the insulation layer 16 and is also attached to The two sides of the floating gate 14. The word line 20 is composed of a polycrystalline silicon layer and is formed above the insulating layer. The word line 20 is used for selecting the gate and controlling the gate. The writing operation is performed by means of hot electron injection (hei) or FN (Fowler-Nordheim) tunneling, and the erasure of data is performed only by FN (Fowler-Nordheiin) tunneling. Take the writing method of hot electron injection as an example, when a high potential (such as 12V) is applied to the source "and a vss potential is applied to the drain 24 via the bit line (ov), the gate 14 is floating. Will have -preset electrical & due to voltage coupling. At this time, if a sufficient potential (such as yth) is generated on the word line 20, a channel will appear between the source 22 and the drain 24, and the hot electrons generated at the drain 24 will be injected into the floating gate. 14 in. If the potential of the word line 20 can be controlled appropriately, the electric field around the floating gate 14 will be amplified and the effect of writing will be enhanced to achieve the goal of power saving.

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd 200418171 V. Description of the invention (3). Therefore, when ^ ^ —, this t e = 5 of the floating gate of the memory cell is filled with + by the writing action; the threshold voltage of the mouth cell will be filled. It is full of electrons, and it is added on the character line 20, and then it is read to make the boundary: two: f (such as 3 ~ 4V) 3 temples, due to high threshold electric dust abortion peak primary pole 22 It is impossible to form the first and second data with the drain 24: it is possible to distinguish the two different states of the memory cell: on i, the potential (such as 15V) will be applied ... ^ Floating gate 14 ♦ The occluded line receives the VSS potential, stores it in the outflow, and then wipes it out: information; write through the insulation layer 18 in the way of face-to-face ^ ^ ^ In the flash memory structure, because the selected and non-selected write Incoming action 3 is connected to the same bit line. When the selected memory cells are interspersed with $ = ^ non-selected memory cells will be disturbed by nearby selected memories and malfunction. In addition, if there is a defect in the tunneling insulation layer 18, Cao Xinyi's anti-tunneling interference will occur, and the non-selected memory cell = intrusion. If in the process, the character line 20 is caused by the alignment problem, it is caused by the alignment problem, or a certain process is missing, which causes the threshold voltage value of the memory cell to decrease. The selected memory cells are rewritten. Traditionally, there are many ways to solve this interference phenomenon. The first example is to increase the thickness of the insulation layer under the selection gate and increase the threshold voltage of the selection gate. However, in this method, there is a certain limit due to the increase in the thickness of the insulating layer ', which is very difficult in the practical application of the semiconductor process. Another example is the doping of boron ions under the selection gate of the memory cell, but m 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 7 200418171 V. Description of the invention (4) This method will cause reading When reading, the reading current becomes smaller, making it difficult to judge the state of the memory cell, and increasing the difficulty of reading data. U.S. Patent No. 6,348, 3 78 also proposes a flash memory structure that can avoid write interference due to punch-through. It is to add an "anti-punch-thorugh region" around the drain region to prevent the occurrence of the punch-through phenomenon. However, in this method, an additional ion value step must be added to the manufacturing process, which makes the manufacturing process more complicated. In addition, another type of flash memory structure uses separate channels for writing and reading in a memory cell, as shown in Figure 2A. Figures 2B and 2C are sectional views of Figure 2A cut along XX and YY ', respectively. The memory cell 30 is composed of a base 3, a floating gate 34, a control gate 33, a source 3 1 and two drains 3 6 1 and 3 6 2 isolated by a shallow trench isolation layer (g τ I) 3 2. When reading, the reading channel will be formed between :: and pole 3 6 1 and source 31; and when writing, the writing channel will be between :: and pole 3 6 2 and source 3 1 Between formation. Since the writing and reading channels of each adjacent memory cell are separated by two shallow trench isolation layers 32, the chance of interfering interference is reduced. However, in this type of flash memory with separate writing and pre-fetching channels, since the control gate and the immobility of the read channel / side are turned on during writing, it is used for a period of time. Later, the read channel still has the problem of write interference. In addition, it also needs to use a higher source potential to move the hot electrons in the floating gate, which will cause greater interference. SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides

0503-8776TWF (Nl); TSMC2002-0716; vmcent.ptd 8th tribute 200418171 V. Description of the invention (5) Increase in write interference with the read channel The present invention takes channels faster than the source region on the substrate. , Located in the base and away. The floating gate layer has a width near the first drain region. The fast substrate of the present invention for accessing the channel; forming a substrate on the side to form a substrate and the distance from the first one> and the polar region, and the gate-controlling layer is adjacent to the fast flash of the access channel of the present invention; The first purpose flash memory, which has a large memory, is square; one is controlled in the substrate; the floating body is connected to the floating pole, and the floating gate is adjacent to the width of the second pole. A better use is to provide a device including: a substrate; a gate layer, which is located after the period of use and is under stress. A floating write and read gate layer is separated, a bit above the floating gate and a first side of the floating gate; and a first second side, which is adjacent to the first layer and the electrodeless region. It is smaller than the second drain, the isolated first drain region, and the control layer is adjacent to the width. A gate source region on a memory substrate, the floating gate and a second wide gate gate, and the second third flash memory are intended to provide a method for manufacturing a body, including forming a floating gate gate layer; Forming a drain region of one of the gates in the substrate and in the substrate. The width of the drain layer is adjacent to the floating layer. The purpose is to form a body, including a second side, in which the floating gate layer is adjacent to the first non-polar region, and the separation steps are written: the floating gate is separated from the floating gate; the isolation gate layer is used The width of the adjacent second drain electrode is smaller than that of the gate electrode and the width of one gate electrode and the width of the gate electrode adjacent to the second region. The control provides a substrate with separate writing and reading; a first conductive layer

0503-8776TWF (Nl) · TSMC2002-0716; vincent.ptd Page 9 200418171 V. Description of the invention (6) Above the substrate; a second conductive layer located above the first conductive layer; a first doped region Is located in the substrate and a first side of the first conductive layer; an insulating layer is located in the substrate; and a second and third doped region are located in the substrate and one of the first conductive layers. On both sides, they are isolated from each other by the insulating layer. The width of the first conductive layer adjacent to the second doped region is greater than the width of the first conductive layer adjacent to the third doped region, and the width of the second conductive layer adjacent to the second doped region is smaller than the first conductive layer. The two conductive layers are adjacent to the width of the third doped region. Therefore, the present invention increases and reduces the width of the floating gate and the control gate respectively located in the writing channel, and makes the potential on the word line 0 volts during the writing operation. Write interference will occur. At the same time, because of the lower VSS voltage, interference phenomena such as reverse tunneling, punchthrough and leakage current are also reduced. The process of the present invention can be completed only by changing two photomasks in the original process. Hereinafter, an embodiment of a flash memory having separate write and read channels and a method for manufacturing the same according to the present invention will be described with reference to the drawings. Embodiments Figures 3A, 3B, 3C to 6A, 6B, and 6C show the process of a flash memory manufacturing method with separate write and read channels in an embodiment of the present invention. Figures 3B, 4B, 5B, 6B and 3C, 4C, 5C, and 6C are cross-sectional views cut along lines X X 'and Y Y' in Figures 3A, 4 A, 5 A, and 6 A. First, as shown in Figures 3A, 3B, and 3C, a crystal plane is provided as

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 10 200418171

<1 Oj>, I ^ 'Shixi substrate 4', and then a shallow trench isolation layer 4 1 is formed on the silicon substrate 4 = an active region (actlve aTea). The formation method of the shallow trench isolation layer 41 is to form a photoresist layer with a pattern on the silicon substrate 4 (not shown in the figure to expose the area where the shallow trench isolation layer 41 is to be formed. The photoresist layer may be An oxide layer and a nitride layer are composed of stacked layers. After the photoresist layer is used as a photomask for exposure, an exposed step is performed on the silicon substrate 4 by a step of etching down to a certain depth. Groove. This step is a dry silver engraving using plasma. Because the plasma engraving may cause the lattice of the groove wall of Shixi substrate 4 to be damaged, the surface of the groove wall will be shaped by thermal oxidation. An oxide film with a thickness of about 50 to 100 A. Next, a silicon nitride layer is formed on the oxide film on the trench wall. Then, a high-density plasma (HDP) is used to form a filled trench. And the insulating layer on the entire surface of the substrate 4. Finally, the entire surface is polished by chemical mechanical polishing to remove the photoresist layer and the extra insulating layer until the surface of the substrate 4 is exposed. The formation of the shallow trench isolation layer 41 Position, as shown in the figure, on every two faces A larger isolation layer is placed between the larger ones. A memory cell line is formed between two large-area isolation layers, while a small-area isolation layer is used to isolate the write channel and the read channel within a memory cell. Next, as shown in FIGS. 4A, 4B, and 4C, a floating gate electrode 42 is formed on the silicon substrate 4 across two large-area shallow trench isolation layers 41. First, the active state of the Shixi substrate 4 is dry-oxidized. The surface of the region is oxidized to form a silicon dioxide layer with a thickness of about 10: 2 50 A. This silicon oxide layer is used as a gate oxide between floating gate electrodes. Next, a low-pressure chemical gas is used. Phase deposition (LPCVD) deposits polycrystalline silicon with a thickness of about 2 0 0 to 3 0 0 A over the entire surface.

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page Π 200418171 V. Description of the invention (8)

What is the round surface? J &amp;. IM's E or Pi, narrow ',', K political law, or ion implanted square a, resistivity: cause: ί just deposited polycrystalline silicon, "reduced; 1 The high-concentration dagger: 1 step will remove the surface of the polycrystalline stone due to the ionization of the Shixi layer. Usually it is the surface, after this layer of stone has to go through this removal step,-S =, the mixed solution to The tungsten tungsten layer deposited on the Duo Shishiju will be made of low-pressure chemical gas. ":::：:: Using polycrystalline stone and stone two :: =: for gasification ... attach i ::. As a result, after the formation of gold i: core-polycrystallization and oxygen / tungsten layer> After the product is completed, ^ Tian Xijing silicon layer to define the graph of the interpolar layer t, go to the process, so that the Then, the wafer is sent to dry etching; the photochemical and polycrystalline stone layers on the surface are removed, and the photoresist layer-covered stone layer gate 42 is formed, and the square iron is continued on it. In addition, the insulation between the control gates to be formed on the floating surface is used as :: and: as a flash memory for access and read channels. The width on both sides is not the same: the gate electrode 42 has a larger width above a small area, but has a smaller width on the side that will be used as a writing channel. In:-::: do: read the channel area The upper mask pattern is used to form the floating pole. Then, as shown in Figures 5HB and 5C, it is floating; Fang 0503-877611 ^ (Nl); TSMC2002-0716; vincent.ptd Page 12 200418171 5 、 Explanation of the invention (9) The method of controlling the formation of a through shallow trench isolation layer 41 is the same as that of the floating gate layer 42, and it is used as ^. It is also necessary to control the gate layer 44 before the same as the conventional flash memory. The control electrode layer 44 (not shown in the figure) is thought on both sides of the floating gate electrode 42: tunnel through the insulating layer ground, and form a control idler 44 with the traditional industry; The difference in flash memory is that the control gate ::::: is the same as the item access, but above the area that will be used as the write channel Above the area that will be used as the reading channel: ΐί: The view. In this step, you only need to change the control mode of the flash memory system in the flash memory system. This can be achieved by writing the mask pattern required for writing 卽, and checking the + + # I wind path gate, without any additional process steps. H, as shown in Figures 6A, 6B, and 6C, in Shixi Base f regions 461, 462, and a plug base and wire structure 41 are formed on the drain regions 461, 462. The formation system of the source region 45 and the drain regions 461, 々 is used to control the gate 44 and the floating connection. The gate 42 is a mask, and phosphorus is used as an ion source. The whole wafer is implanted with phosphorus ions. The ion concentration used in this ion implantation step is not high, about 1 to the power of one. 〇1Vcm2 is mainly used as a lightly doped drain (LDD) to prevent the short channel effect from occurring. Later, it will be formed on the side of the common stacked layer of the control gate 44 and the floating gate 42. A spacer wall composed of an oxide layer. Then, a stacked layer formed by the control gate 44, the floating idler electrode 42 and the spacer wall is used as a mask to carry out heavy doping. ing), using phosphorus or arsenic with higher solid-solubility in silicon as the ion source 'for high-concentration and deep-depth ion implantation of the wafer, with a concentration of about 1015 / cm2 as the source region 45 Drain regions 461, 46 2

0503-8776TWF (Nl); TSMC2002-0716; vmcent.ptd page 13 200418171 V. Description of the invention (10) Finally, a metallization process step is performed to form contact plugs and wire structures 47 on the drain regions 4 6 1 and 4 6 2 to complete the connection of the bit lines. From the above steps, it can be known that in the process of the present invention with separate write and read flash memory, only two photomask patterns used in making the floating gate and controlling the idle pole need to be changed. Yes, no additional process steps are required. ^ So ‘the flash memory with separate write and read channels in the present invention ^ The structure of cell 40 is shown in Figures 6A, 6B and 6C. It includes a silicon substrate ^, a gate electrode layer 4 2, a control gate layer 44, a source region 45, an isolation layer 41, and two drain regions 461 and 462. The floating gate layer is "above the silicon substrate 4. The control gate layer 44 is located above the floating gate 42. The source region 45 is in the silicon substrate 4 and one side of the floating gate 42. The isolation layer 41 is located on the silicon In the soil bottom 4, it is used to isolate the memory cell from the write and read channels in the memory cell. The drain regions 461 and 462 are located in the silicon substrate 4 and the other of the floating gate 42 is isolated from each other by the isolation layer 41. In the #, the floating gate layer 42 is adjacent to the drain electrode 4. The width of the gate electrode is larger than the width of the adjacent electrodeless region 462, and the width of the control electrode spreading near the drain electrode region 461 is smaller than that of the adjacent drain electrode region 462. Method ΐ Ϊ The operation of flash memory with separate write and read channels During the write operation, the source of the selected memory cell receives one ::,: Intermediate electrode reception, the potential of the time, its The electrode potential lasts for 50 # seconds. Instead of receiving a potential of 8 volts per day, it protects the 5 selves and cells selected by it, and its source electrode is the gate of the ancestor Hongzu receives a voltage of 10 volts. Keep floating, the duration is 2 0 // seconds.

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 14 200418171 V. Description of the invention (11) Bit, duration 2: The t-cell control gate receives the electric potential at 12.5 volts, and controls: : Then :: 22 potentials, the poles receive "the current value of the dog to determine the stored bit,. Potential 'and read the memory cell to generate the traditional flash memory 丨 sound body 卩 私 私 私%% ~ e Under the car, the flash memory structure of the present invention is in the write selection mode, and the control potential used by 栌 π 合 / — π Mucha inch is 0 volt%, so it will not take the channel Pe m. On one side generates write interference, so in a long period of time: ι memory will produce: = = 7 ^ ± j. Faster off-write and read channels. The electrode potential is also low, and the interference _ ^ 1¾. / Rt T r; 乂 丨 reduces the interference of back teeth, breakdown, and leakage current........ According to the above, the present invention provides a separate write and read The fetched flash memory is used to increase and decrease the width of the floating gate and the control gate respectively located in the write channel. When the line write operation is performed, the potential on the word line is 0 volts, so that write interference will not occur in the read channel. At the same time, the lower VSS voltage is used to reduce reverse tunneling and impact. Interference phenomena such as punchthrough and leakage current. This can avoid the phenomenon of increased write interference caused by traditional flash memory with separate write and read channels after long-term use, and can have better resistance to use In addition, the present invention can be completed only by changing two photomasks in the original process in the manufacturing process. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Artists, without departing from the spirit of the invention

IB1I

0503-8776rrWF (Nl); TSMC2002-0716; vincent.ptd Page 15 200418171 V. Description of the invention (12) Within the scope of God and God, there can be some changes and retouching, so the scope of protection of the present invention should be attached as The ones defined in the scope of patent application shall prevail.

II _ ΙΙΙΓ 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 16 200418171 Brief description of the diagram Figure 1 shows the structure of traditional flash memory; Figures 2A, 2B and 2C show the traditional Flash memory structure of the write and read channels; Figures 3A, 3B, 3C ~ 6A, 6B, and 6C show a flash memory with separate write and read channels in an embodiment of the present invention Manufacturing method flow. Explanation of symbols 10, 3, 4 to the substrate '1 2, 1 8, 1 6, 4 3 to the insulating layer; 1 4, 3 4, 4 2 to the floating gate layer; 22, 24, 31, 361, 3 6 2, 45, 461, 462 ~ source, / pole area; 20, 3, 4 4 ~ control gate layer; 3 5, 4 7 ~ bit line; 3 2, 4 1 ~ shallow trench isolation layer; 3 0, 4 0 ~ memory cells.

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page 17

Claims (1)

200418171 VI. Application Patent Scope 1. A flash memory with separate write and read channels, comprising: a substrate; a floating gate layer located above the substrate; a control gate layer located on the floating Above the gate; a source region in the substrate and a first side of the floating gate; an isolation layer in the substrate; and a first and second drain region in the substrate And a second side of one of the floating gate electrodes is isolated from each other by the isolation layer; wherein the width of the floating gate layer adjacent to the first drain region is greater than that of the floating gate layer adjacent to the second drain region And the width of the control gate layer adjacent to the first drain region is smaller than the width of the control gate layer adjacent to the second drain region. 2. The flash memory with separate write and read channels as described in item 1 of the patent application scope, wherein the substrate is a P-type substrate. 3. The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, wherein the floating gate layer is a polycrystalline silicon layer. 4. The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, wherein the control gate layer is a polycrystalline silicon layer. 5. The flash memory with separate write and read channels as described in item 1 of the patent application scope, wherein the isolation layer is a shallow trench isolation layer (STI). 6. Separate writing and reading as described in item 1 of the scope of patent application 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 18 200418171 VI. Patent application flash memory for channel access, which also includes an insulating layer between the floating gate layer and the substrate . 7. The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, which further includes an insulating layer between the control gate layer and the floating gate layer. 8. The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, further comprising a plurality of contact plugs electrically connected to the first and second drain regions. 9. The flash memory with a separate write and read channel as described in item 1 of the scope of the patent application, wherein when writing to the flash memory, a write channel is in the source region and Generated between the first drain regions. 10. The flash memory having separate write and read channels as described in item 1 of the scope of patent application, wherein when reading the flash memory, a read channel is in the source region And the second drain region. 1 1. A method of manufacturing a flash memory with separate write and read channels, comprising the following steps: providing a substrate; forming a floating gate layer over the substrate; forming over the floating gate A control gate layer; forming a source region in the substrate and a first side of one of the floating gates; forming an isolation layer in the substrate; and forming a source region in the substrate and one of the floating gates Two sides forming a first and a second drain region isolated from each other by the isolation layer; 0503-8776TWF (Nl); TSMC2002-0716; vmcent.ptd Page 19 200418171 6. The scope of patent application where the width of the floating gate layer adjacent to the first drain region is greater than the floating gate layer adjacent to the first The width of the two drain regions and the width of the control gate layer adjacent to the first drain region is smaller than the width of the control gate layer adjacent to the second drain region. 1 2. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of patent application, wherein the substrate is a P-type substrate. 1 3. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of the patent application, wherein the floating gate layer is a polycrystalline silicon layer. 14. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of the patent application, wherein the control gate layer is a polycrystalline silicon layer. 1 5. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of patent application, wherein the isolation layer is a shallow trench isolation layer (STI). 1 6. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of patent application, further comprising the following steps: forming between the floating gate layer and the substrate An insulating layer. 1 7. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of the patent application, further comprising the following steps: at the control gate layer and the floating gate An insulating layer is formed between the layers. 0503-8776TWF (Nl); TSMC2002-0716; vmcent.ptd Page 20 200418171 VI. Application for patent scope 1 8 · The application of separate application for write and read as described in item 11 of the scope of patent application A The manufacturing method of flash memory and flash memory further includes the following steps: ： y is electrically connected to the first and second drain regions with a plurality of contact plugs. The method of manufacturing with separate writing and §WB b _j.,, And flash § self-memory as described in Item 11 of the patent scope, wherein when writing to the flash memory, ^ T A write channel is generated between the source region and the first drain region. 2 0. Shikou Shenhan Taizhi •, called the body h and ^ with the separate writing and reading channels described in item 11 of the patent scope. The memory performs reading, and a read channel is generated between the source region and the second drain region. 2 1 head] Includes flash memory with separate write and read channels, a substrate; an electric layer, which is located above the substrate; an electric layer, which is located at the first conductive layer Above; ^ second brother-doped region, is located in the substrate and one of the first conductive layer first side; two two is located in the substrate; and a thicker one doped region is located in the substrate and the The first conductive pillars are isolated from each other by the insulating layer; "", the width of a conductive layer adjacent to the first conductive layer adjacent to the third doped region is greater than the width of the doped region and the second conductive region Neighbor 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page 21 200418171 6. Scope of patent application The width of the near-second doped region is smaller than the width of the second conductive layer adjacent to the third doped region. 2 2. The flash memory with separate write and read channels as described in item 21 of the scope of patent application, wherein the substrate is a P-type substrate. 2 3. The flash memory with separate write and read channels as described in item 21 of the scope of patent application, wherein the first and second conductive layers are polycrystalline> 5x4. The flash memory with separate write and read channels as described in item 21 of the patent application scope, wherein the insulating layer is a shallow trench isolation layer (STI). 2 5. The flash memory with separate write and read channels as described in item 21 of the scope of patent application, further comprising a second insulating layer between the first conductive layer and the substrate. 2 6. The flash memory with separate write and read channels as described in item 21 of the scope of patent application, further comprising a second insulating layer between the second conductive layer and the first conductive layer between. 2 7. The flash memory with separate write and read channels as described in item 21 of the patent application scope, further comprising a plurality of contact plugs electrically connected to the second and third doped regions. 2 8. The flash memory with separate write and read channels as described in item 21 of the scope of patent application, wherein when writing to the flash memory, a write channel is on the first Generated between the doped region and the second doped region. 2 9. Separate writing and 0503-8776TWF (Nl); TSMC2002-0716; vmcent.ptd page 22 200418171 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page 23