TW586220B - Flash memory cell with unique split programming and reading channel - Google Patents

Abstract

The present invention provides a flash memory cell with unique split programming and reading channel. It includes a substrate, a floating gate, a control gate, a source, an isolation layer, and a first and second drain. The floating gate is disposed on the substrate. The control gate is disposed on the floating gate. The source is in the substrate and disposed on a first side of the floating gate. The isolation layer is in the substrate and isolates the first and second drain on a second side of the floating gate from each other. The width of the floating gate near the first drain is larger than that near the second drain while the width of the control gate near the first drain is smaller than that near the second drain.

Description

586220 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a flash memory, and in particular to a flash memory with a separate write and read channel, which can be avoided after long-term use The resulting increase in program disturbance has better use and f endurance. Prior art non-volatile semiconductor devices with flash memory cells were electronically erased and written, and data could be stored even without power supply. Therefore, such non-volatile semiconductor devices are widely used in many different applications. Taking a common NOR-type non-volatile semiconductor device as an example, it usually has multiple memory cells connected in parallel to the-position, and only between the drain and source of the memory cell. Connect a transistor. ^ ^ ^ ^ 4 ^, Λ., 禋 ,,, " structure can increase the current of 圯 memory cells and can perform fast operation. Because these self-remembering cell lines are connected in parallel to each other _ back to the '" " " line 7C, when Jingyu chooses a selected memory cell, it is likely that other memory cells kissed by him The 怿, 兀, &, &; raw shells were accidentally erased and the read disturbance occurred. In addition, if the memory threshold voltage is lowered due to some factors, or even lower than the control gate potential of the two-electrode body, the above-mentioned interference phenomenon of taking s, bedding, fe, and k is also taken. will happen. In order to remove the phenomenon of reading interference, an additional electric cell will be added to the memory cell. The case of the V-body device with two transistors, that is, a flash memory with a single cell body. However, on page 5 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd 586220 V. Description of the invention (2) Said η :: The use of two transistors consumes a lot of circuit area and is not conducive to the use of structured semiconductor devices The problem that the gate area of different gates is too large. One example is separation (that is, the choice of interrogation and control in this device, the character line diagram does not show the structure of this device. The force is in the figure 1-", Luo LaM ϋ 1 yf JX, 丄, margin The layer 12 is located on the floating gate = 4Q = 4 and 1 on the base 10, and it is between the W® gate 14 and the base 10. The floating gate 14 is formed by IA r 1 η. Another insulating layer 16 is formed on the western-connected gate electrode 14: 2: 2: there is a tunneling insulating layer 18 for erasing data. With the insulation = the Pakistani 16 are connected together and also attached to The floating gates 14 and 70 are composed of polycrystalline silicon layers and are formed above the insulating layers 16 to 18. The word line 20 is used for selecting and controlling the gates. The write operation is performed by means of thermal electron injection (ηε ^ or FN (Fowler-Nordhelm)), and the erasure of data is performed only by FN (Fowler-Nordheiin) tunneling. Taking the writing method of hot electron injection as an example, when a high potential (such as i2v) is applied to source 22 and a vss potential is applied to drain 24 via bit line (ov), floating gate 14 Will be engaged due to voltage And it has a preset potential. At this time, if a sufficiently high potential (such as vth) is generated on the word line 20, a channel appears between the source 22 and the drain 24 and the heat generated at the drain 24 The electrons will be injected into the floating gate 14. If the potential of the word line 20 can be controlled appropriately, the electric field around the floating gate 14 will be amplified to enhance the effect of writing and achieve the goal of saving power

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page 6 586220 5. Description of the invention (3). Therefore, if 'memory cell_', the threshold voltage of this memory cell will be = lifted, filled with electrons, and added to the word line 2G by the action of-into the electric line (= the existence of the following for reading, so that Source electrode 22 and drain: 24: Second, due to high voltage: voltage, voltage, etc., such as bumumu…, law forms a channel, but no electricity: the purpose of data. '彳 distinguish between two different states of memory cells Reaching dagger = Si: Except day T — 咼 potential (such as 1 M will be applied to the word line 20 source, electrode 22 will receive vss potential via the bit line, and the electrons stored in :: will pass through the tunnel insulation layer 18 The purpose of erasing data is achieved by FN tunneling / removal. ≫ j In the above flash memory structure, since the selected and non-selected cells j are connected to the same bit line, in When the selected memory cell is written, the non-selected memory cell will be disturbed by the adjacent selected memory and malfunction. In addition, if there is a defect in the tunneling insulation layer 18, there is an 'anti-tunneling interference' Will happen, and the non-selected memory cell will be rewritten. In character line 20, the length of word line 20 is shortened due to alignment problems, or the threshold voltage of memory cells is reduced due to the loss of a certain process, which will cause a breakdown phenomenon, which will cause unselected memory cells to be rewritten. Traditionally, there are many ways to solve this kind of interference phenomenon. The first example is to increase the thickness of the insulation layer under the selection gate and increase the threshold voltage of the selection gate. However, in this method, due to the insulation layer There is a certain limit to the increase in thickness. It is very difficult to practically apply the semiconductor process. Another example is the doping of boron ions under the select gate of the memory cell. However,

586220 V. Description of the invention (4) However, this method will cause the reading current to become smaller when reading, making the state of the memory cells difficult to judge, and increasing the difficulty of reading data. U.S. Patent No. 6,348, 3 78 also proposes a flash memory structure that can avoid write interference due to punch-through. It is to add an "ant i-punch-1horugh region" around the drain region to prevent the occurrence of the puncture phenomenon. However, in this method, an additional ion value step must be added to the manufacturing process, which makes the manufacturing process more complicated. In addition, another type of flash memory structure uses separate channels for writing and reading in a memory cell, as shown in Figure 2A. Figures 2B and 2C are sectional views of Figure 2A cut along XX 'and YY', respectively. The memory cell 30 is composed of a base 3, a floating gate 3 4, a control interrogator 3 3, a source 31, and two non-poles 361 and 3 62, which are separated by a shallow trench isolation layer (STI) 32. When reading, a read channel is formed between the drain 36m and the source 31; and when writing, a write channel is formed between the drain 362 and the source 31. Since the writing and reading channels of each adjacent memory cell are separated by two shallow trench isolation layers 32, the mutual interference mechanism is reduced. However, in this type of flash memory with separate write and read channels, since the control gate and the drain on one side of the read channel are turned on during writing, after a period of use, the read Taking channels still has the problem of writing interference. In addition, it also requires the use of a higher source 'electric meter to move the hot electrons in the floating gate', which will cause greater interference. SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides

586220 V. Description of the invention (5) Increase in write interference with the read channel The present invention takes channels faster than the source region, the separation layer, the substrate, and the substrate on the substrate. Among them, the floating gate layer is near the width of the first sub-region. The substrate of the present invention for accessing the channel is fast; on the side, a substrate is formed on one side and the distance from one of the first electrodeless region is formed, and the control gate layer is adjacent to the channel of the present invention for fast flashing. The current first flash memory square; a floating source and a second wide gate on the base, the substrate, the floating, the floating, and a second flash memory substrate adjacent to the pole region The second and third flash memory, which has a purpose in the body, includes controlling the bottom and middle of the gate; and one of the gates has a gate layer adjacent to the second drain width smaller than the purpose of the body forming layer. ; In: the gate > and the polar region adjacent to the floating layer in the non-polar region of the object, the package can be avoided in the long-term better use resistance to provide a: a substrate; one layer, located in the floating gate The extreme and the forces generated after the second use. Separate write and read floating gate layers, located above the gates; one to one side; one second to second drain region, located on the second side, separated from each other by the isolation layer The width of the first drain region is greater than the width of the region, and the control gate layer is adjacent to the control gate layer and adjacent to the control panel. It also provides a method for fabricating the gate electrode layer including a floating gate layer. A quilt is formed in the substrate and a second side is formed in the substrate. The floating gate layer is adjacent to the width of the brother-drain region. Separately write less steps: leave the floating gate at the floating gate; separate the gate layer adjacent to the isolation layer; the width of the electrode is less than the input and read to provide a gate on the gate and close to the sibling area. The width of the control includes: · a type with a substrate; a separate write and the first conductive layer, bit

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd --- Page 9 586220 V. Description of the invention (6) Above the substrate; a second conductive layer located on the first conductive layer and a first doping A region is located in the substrate and above the first conductive layer; a side; an insulating layer is located in the substrate; and a second and second to second regions are located in the substrate and one of the first conductive layer On the second side, the doped edge layers are isolated from each other. Wherein, the width of the first conductive layer adjacent to the first broken layer is larger than the width of the first conductive layer adjacent to the third doped region, and the width of two conductive layers adjacent to the second doped region is smaller than the second conductive layer. The width of the third doped region. ~ ㈢ Adjacent to this, the present invention increases and reduces the width of the floating gate and the control gate respectively located in the write channel, and the potential on the character is 0 volts during the write operation, so the read Taking a channel does not cause write interference. At the same time, because of the lower vss voltage, interference phenomena such as reverse tunneling, punchthrough and leakage current are also reduced. The process of the present invention can be completed only by changing two photomasks in the original process. Hereinafter, an embodiment of the flash memory having separate write and read channels and a method for manufacturing the same according to the present invention will be described with reference to the drawings. Embodiment 3A, 3B, 3C ~ 6A, 6B, and 6C show a flash memory manufacturing method process with separate write and read channels in one embodiment of the present invention. Figures 3B, 4B, 5B, 6B and 3C, 4C, 5C, and 6C are sectional views cut along lines XX and γγ in Figures 3A, 4A, 5A, and 6A. First, as shown in Figures 3 A, 3 B, and 3 C, a crystal plane is provided as

586220

<, 10j >, a p-type silicon substrate 4, and then a shallow trench isolation layer M is formed on the silicon substrate 4 to form an active area. The shallow trench isolation layer 41 is usually formed by first forming a patterned photoresist layer on the silicon substrate 4 (not shown in the figure to expose the area where the shallow trench isolation layer 41 is to be formed. The photoresist layer can be An oxide layer and a nitride layer are composed of stacked layers. After the photoresist layer is used as a photomask for exposure, the exposed area on the silicon substrate 4 is etched downward to form a trench of a certain depth through an etching step. This etching step is dry etching using a plasma. As the plasma etching may cause the lattice of the groove wall of the silicon substrate 4 to be damaged, the surface of the trench wall will also be shaped by thermal oxidation. An oxide film of 504 00 A. Next, a silicon nitride layer is formed on the oxide film of the trench wall. Then, a high-density plasma (HDP) is used to form an insulation filling the trench and the entire surface of the substrate 4. Finally, the entire surface is polished by chemical mechanical polishing to remove the photoresist layer and the extra insulating layer until the surface of the substrate 4 is exposed. The formation position of the shallow trench isolation layer 41 is as shown in FIG. Shown in every two A larger isolation layer is placed between the larger areas. A memory cell line is formed between two large-area isolation layers, while a small-area isolation layer is used to isolate the write channels and reads in a memory cell. Then, as shown in FIGS. 4A, 4B, and 4C, floating floating electrodes 42 across two large-area shallow trench isolation layers 41 are formed on the silicon substrate 4. First, the silicon substrate 4 is actively activated by a dry oxidation method. The surface of the area is oxidized to form a silicon dioxide layer with a thickness of about 100 ~ 250 A. This silicon oxide layer is used as a gate oxide layer (Gate 0xlde) for floating electrodes. Next, a low-pressure chemical gas is used. Phase deposition method (LPCVD) deposits polycrystalline stones with a thickness of about 2 0 0 to 3 0 0 A on the entire surface.

586220 V. Description of the invention (8) Resistivity of phosphorus or arsenic on the wafer surface. However, a layer is formed as a result of the removal and the doped phosphorous glass is removed. After this removal, the polycrystalline material is used to define the gate resistance between the silicon oxide layer and the silicon silicide layer and the tungsten silicide layer. It is formed with the polycrystalline gate 4 2 and the read-through insulating layer 4 1 is formed with a small read and write mask pattern above the two regions. Then, it is doped by thermal diffusion or ions. The newly deposited guest S & Nai will make π / chen degrees this step will ;; Γ Ⅱ to reduce the polycrystalline stone layer ’s thin layer of stone layer 层; = face owing to oxygen and dishes, etc. The intermediate polycrystalline stone layer has good subsequent petrified metal. Usually, it is necessary to use HF or 丄 to carry out this layer of stone Xi + Su De, h 〆 mixed solution of HF. On the silicon layer. The reason why the word says " low £ chemical vapor deposition gate layer, 俜: = poor adhesion between silicon and tungsten silicide two layers = = material or petrified metal material increase-polycrystalline silicon layer to avoid Service: f is eliminated after silicidation metal layer and oxygen deposition are completed; problem. When the polycrystalline stone layers are patterned, transferred; cavities; under-lithographic processes' in order to use the circle to enter the age of ^ coating on the surface of the tungsten silicide, the machine will not come The resistive expansion is removed by a broken layer t to form a floating gate electrode 42. Hereafter, after =, edit the square on it, and manually control the gate between the gates 0 ~, 43 'as the flash memory for the channel. ? Traditionally, the width of the separate write side is not the same: "'Yu gate 42 has a larger width in a small area,"; is the width of the write channel. Here 4 = the channel flash memory system on the read channel area ^, only need to change the traditional separation type, it is not necessary; two: the use of floating gates as shown in Figure 5A, 5B, 5C The steps of the clothing process. Nowhere, above floating gate 42

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 12 586220

Gate 4 4 Before the control gate is formed in a shallow and shallow manner, it must be transmitted to the ground (not shown in the figure). The width of the flash memory on the side of the control gate does not have a smaller width. The flash memory can be achieved in this channel. The control gate layer 4 2 of the trench isolation layer 41 is the same, and the flash memory is the same as the floating gate 4 2 and the gate 44 is different. The same, Instead, in a step that will be done, the shape of the system requires other sides, and the traditional control gate will only be changed to read outside the control system as the reading, but it will have a pole 4 in the shape and insulation. 4 In order to change the traditional gate of the write channel, the gate is controlled to form a tunneling layer. 4 3 The isolation layer is used to separate the electrode layer 4 4 which is used for separate read over the area of the small-area insulated channel. Similarly, there is a large masking and writing mask pattern above the two areas of the read through layer 41. Finally, as shown in FIGS. 6A, 6B, and 6C, a source region 45 and a drain electrode are formed in the Shixi substrate 4. The regions 46 1 and 462 form contact plugs and wire structures 47 on the drain regions 461 and 46 2. The source region 45 and the drain region 4 6 1 and 4 6 2 are formed by controlling the gate 44 and the floating gate 42 as a screen, and using phosphorus as an ion source to implant phosphorus ions on the entire wafer. Into. The ion concentration used in this ion implantation step is not high, and the order is between about 1013 / cm2. It is mainly used as a lightly doped anode (L⑽) to prevent short channel effects from occurring. Use. After that, a partition wall composed of an oxide layer will be formed on the side of the common stacked layer of the control gate 44 and the floating gate 42. Then, the stacked layer formed by the control gate 44, the floating gate 42 and the gap wall is used as a mask, and heavy doping is performed. Phosphorous or arsenic with a higher solubility in silicon is used as the ion source. 'Ion implantation of the wafer with high concentration and deeper depth, the concentration is about 1 015 / c m2' as the source region 4 5 and the drain region 4 6 1, 4 6 2 main body

586220

V. Description of the invention (11) During the erasing operation, the value is 6 times $ ', the duration is 2, and when the closed-second electrode is receiving 12.5 volts, the source electrode receives 0 volt potential and the control electrode Then receive 2.5 electricity and = receive a current value of 1 volt to determine the stored bit. However, the reason for the formation of the thought cell = t is lower. After the flash memory of the present invention is used between nodes, it will not occur; for example; the long-term interference is lower in the-segment and the reaction is further reduced. With the breakdown, breakdown, and leakage current, the first night t ΐ ^, the present invention provides a separate writer and read pass two; J: s Ji Yi 胄 'increase and decrease the write channel respectively The floating phenomenon of the flash memory will increase the write interference caused by long-term use of the flash memory, which can have better endurance. In addition, the present invention can be completed by changing two photomasks in the original process. Although the present invention has been disclosed as above with a preferred embodiment, it does not limit the present invention. Anyone skilled in this art will not depart from the breadth of the present invention, and let = online when performing a write operation. ^ The potential is G volts', so there will be no interference with writing in the reading channel. At the same time, due to the use of a lower VSS voltage, the phenomenon of reverse tunneling f (reverse tUnneling), punching (punchthrough) and leakage current are also reduced. This can avoid the traditional separate write and read channels.

586220

0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 16 586220 Case No. 92105451 Brief description of the revised diagram 14, 22, 20, 35 '32, 30, 3 4, 4 2 to the floating gate layer 24 '31, 361, 362, 45 3 3, 4 4 ~ control gate layer; 4 7 ~ bit line; 4 1 ~ shallow trench isolation layer; 4 0 ~ memory cell. 461, 462 ~ source / drain region

0503-8776TWl (Nl) .ptc page 17-2 2004. 02. 24.018

Claims (1)

586220 6. Application patent scope 1. A flash memory with separate write and read channels, comprising: a substrate; a floating gate layer located above the substrate; a control gate layer located on the floating Above the gate; a source region in the substrate and a first side of the floating gate; an isolation layer in the substrate; and a first and second drain region in the substrate And a second side of one of the floating gate electrodes is isolated from each other by the isolation layer; wherein the width of the floating gate layer adjacent to the first drain region is greater than that of the floating gate layer adjacent to the second drain region And the width of the control gate layer adjacent to the first drain region is smaller than the width of the control gate layer adjacent to the second drain region. 2. The flash memory with separate write and read channels as described in item 1 of the patent application scope, wherein the substrate is a P-type substrate. 3. The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, wherein the floating gate layer is a polycrystalline silicon evening layer. 4. The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, wherein the control gate layer is a polycrystalline silicon layer. 5. The flash memory with separate write and read channels as described in item 1 of the patent application scope, wherein the isolation layer is a shallow trench isolation layer (STI). 6. Separate writing and reading as described in item 1 of the scope of patent application 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 18 586220 VI. Applying for quick access to the channel and thinking, including an insulation layer, located on the floating gate The substrate. '7 · As described in item 1 of the scope of the patent application, a flash memory with a separate write and read channel, which has an insulating layer, is located between the control gate and the floating gate. Between layers. 2.18. The flash memory with separate write and read channels described in item 1 of the scope of the patent application, further comprising a plurality of contact plugs electrically connected to the first and second drain regions. 9 · The flash memory with a separate write and read channel as described in item 1 of the scope of patent application, wherein when writing to the flash memory, the / write channel is in the source region and Generated between the first drain regions. 1 〇 The flash memory with separate write and read channels as described in item 1 of the scope of the patent application, wherein when the flash memory is read, the read channel is in the source region And the second drain region. 1 1 · A method for manufacturing a flash memory with separate write and read channels, including the following steps: providing a substrate; forming a floating gate layer over the substrate; forming over the floating gate A control gate layer; forming a source region in the substrate and a first side of one of the floating gates, forming an isolation layer in the substrate; and forming a source layer in the substrate and one of the floating gates Forming two first and second non-polar regions isolated from each other by the isolation layer on both sides; 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd Page 19 586220 6. The scope of the patent application, wherein the width of the floating gate layer adjacent to the first drain region is larger than that of the floating gate layer adjacent to the first The width of the two drain regions and the width of the control gate layer adjacent to the first drain region is smaller than the width of the control gate layer adjacent to the second drain region. 1 2. The method for manufacturing a flash memory having separate write and read channels as described in item 11 of the scope of the patent application, wherein the substrate is a P-type substrate. 1 3. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of patent application, wherein the floating gate layer is a polycrystalline silicon layer. 1 4. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of patent application, wherein the control gate layer is a polycrystalline silicon layer. 1 5. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of the patent application, wherein the isolation layer is a shallow trench isolation layer (S T I). 1 6. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of patent application, further comprising the following steps: forming between the floating gate layer and the substrate An insulating layer. 1 7. The method for manufacturing a flash memory with separate write and read channels as described in item 11 of the scope of the patent application, further comprising the following steps: the control gate layer and the floating gate layer An insulating layer is formed between them. 11 ill 0503-8776T \ VF (Nl); TSMC2002-0716; vincent.ptd p. 20 586220, Shen Qiaozhuan, please apply for the first item described in the patent scope with separate writing and 1 flash The manufacturing method of the memory further includes the following steps of reading through the remote step: / The travel contact plug is electrically connected to the first and second drain regions. 1 2 The method for manufacturing a flash memory with a separate write and read channel 2 as described in item 11 of the scope of the patent application, wherein when the flash memory F is written eight times, a write channel is in the ° 2 is generated between the source region and the first non-polar region. The method for manufacturing a flash memory with a separate write and read channel as described in item 11 of the scope of the patent application. When reading from the flash memory, a read channel is generated between the source region and the second drain region. 2 types of flash memory with separate write and read channels, including: a substrate; a first, conductive layer 'is located above the substrate; a second conductive layer is located above the first conductive layer; a first The doping region is located in the substrate and a first side of the first conductive layer; an insulating layer is located in the substrate; and a first M first doped region is located in the substrate and the first conductive layer One of the second sides is isolated from each other by the insulating layer; the width of an electric layer adjacent to the second doped region is greater than the width of the second doped region and the second conductive layer is adjacent 0503-8776TWF (Nl); TSMC2002-0716; Vincent.ptd Page 21 586220 VI. Patent application scope The width of the doped region is smaller than the second conductive layer adjacent to the third dopant_take 2 through 2. The 21st item in the patent scope has a separate * write and flash memory, where the substrate is a p-type substrate.浐 The path is as described in item 21 of the patent scope with separate writing and ‘layers. And flash memory, wherein the first and second conductive layers are polycrystalline edge bubbles, and have a separate write and (1τ flash memory as described in item 21 of the patent application range, wherein the insulating layer It is a shallow trench isolation layer green β2. As described in item 21 of the patent application, it has a separate write and No. 11: 7 memory. It also includes a second insulating layer, which is located in the V brother layer of the younger brother and Between the two bases:-2: "Shou Ru Xi", the patent scope of the 21st household has a separate writer and the 5th electrical :: memory, which also includes a second insulation layer, located in the 4th brother Between a V electrical layer and the first conductive layer. Includes flash memory with separate writing and oral access as described in item 21 of U.S.T. The second and third doped regions include: (1) the number of contact plugs electrically connected; (2) if the scope of the patent application is 2j, the flash of the read channel, 咅 咅, L; L is a write-away When entering, -write through "two ir ;: When writing to the flash memory. Xuandi a doped region and the second doped region produce 29. If applied Lee scope of the item 21 is written with separating type II; () 503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page 22586220 0503-8776TWF (Nl); TSMC2002-0716; vincent.ptd page 23