200417062 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於具備在室溫具有廣禁帶寬之磷化硼系半 導體層之磷化硼系半導體元件，及其製造方法。 【先前技術】 近年來，利用屬於III-V族化合物之一的磷化硼（化 學式：BP)層，構成發光二極體（LED )或者雷射二極體 (LD )等的發光元件之技術有被揭露（例如，參照專利 文獻1)。在憐化硼半導體中，由於電動（hole)的有效 質量比電子小，因此容易獲得p形之傳導層（例如，參照 專利文獻2 )。最近，將p形之磷化硼當作用來形成歐姆 電極之電極形成層（接觸層）而具備之發光元件，爲人所 知（例如，參照專利文獻3 )。 例如，令其接觸至被設置在由III族氮化物半導體層 所成之發光層上的P形磷化硼所成之接觸層而設置的先前 之P形電極，是由金（Au ) /鋅（Zn )合金之單一層所 構成的（參照上記專利文獻2 )。在磷化硼層上具備有兼 任用來結線之台座電極的電極的先前磷化硼系半導體發光 元件，令其接觸P形或η形之磷化硼表面而設置已經是一 般的通例（例如，參照專利文獻3 )。 [專利文獻1 ] 美國專利第6,069,02 1號公報 [專利文獻2] -4- (2) (2)200417062 日本特開平2 - 2 8 8 3 8 8號公報 [專利文獻3 ] 曰本特開平1 0-2425 67號公報 【發明內容】 但在此同時，令電極的底面部位，接觸至導電性之r 形或P形磷化硼層之正確表面而設置的先前構成當中，爲 了驅動發光元件而供給之電流（元件驅動電流），會以較 電極的底面部位更爲短路地往下層流通之問題，總是無法 完全避免。因此，例如，隔著爲了在發光層上方設置電極 之磷化硼結晶層，而將發光取出至外部之方式的L E D中 ’會發生元件驅動電流完全無法擴散至發光領域之不良情 形。因此，要令發光領域擴張、以增加磷化硼系半導體發 光元件的發光強度，現狀是會遇到障礙的。 本發明係爲了克服先前技術之缺點，其目的在於，除 了提示可有效令元件驅動電流擴散至發光領域的廣泛維的 台座電極之構成，還提供具備了此種台座電極的磷化硼系 半導體發光元件，以及用來製造該磷化硼系半導體發光元 件的製造方法。 亦即，本發明爲了達成上記目的，提供如下記： (1 ) 一種磷化硼系半導體發光元件，其特徵爲：含有 發光層的半導體層是被形成在結晶基板上當作基底層；該 半導體層的第1領域上形成有磷化硼系半導體非晶質層； 該磷化硼系半導體非晶質層係含有高阻抗的磷化硼系半導 -5- (3) (3)200417062 體非晶質層；該高阻抗磷化硼系半導體非晶質層上形成有 結線用之台座電極；前記當作基底層的前記半導體層上之 前記第1領域以外之第2領域上，導電性磷化硼系結晶層 是被形成爲任意延伸存在於前記磷化硼系半導體非晶質層 之一部份爲止；前記台座電極係自底面至上部和前記磷化 硼系半導體結晶層相接。 (2) —種磷化硼系半導體發光元件，其特徵爲：含有 發光層的半導體層是被形成在結晶基板上當作基底層；該 半導體層的第1領域上形成有磷化硼系半導體非晶質層； 該磷化硼系半導體非晶質層係含有傳導形和前記當作基底 層之前記半導體層相反的磷化硼系半導體非晶質層；該高 阻抗磷化硼系半導體非晶質層上形成有結線用之台座電極 ;前記當作基底層的前記半導體層上之前記第1領域以外 之第2領域上，導電性磷化硼系結晶層是被形成爲任意延 伸存在於前記磷化硼系半導體非晶質層之一部份爲止；前 記台座電極係自底面至上部和前記磷化硼系半導體結晶層 相接。 (3) 如申請專利範圍第1項或第2項所記載之磷化硼 系半導體發光元件，其中，前記磷化硼系半導體非晶質層 ，是具有：被形成爲相接至前記當作基底層之前記半導體 層且具有相反於前記當作基底層之前記半導體層之傳導形 的磷化硼系半導體非晶質層，及被形成在該當相反傳導形 磷化硼系半導體非晶質層之高阻抗之磷化硼系半導體非晶 質層的重疊層積構造。 -6 - (4) (4)200417062 (4) 如申請專利範圍第1項或第2項所記載之磷化硼 系半導體發光元件，其中，前記磷化硼系半導體非晶質層 ，是由非摻雜之磷化硼系半導體所構成。 (5) 如申請專利範圍第3項所記載之磷化硼系半導體 發光元件，其中，構成前記磷化硼系半導體非晶質層之前 記重疊層積構造的兩層磷化硼系半導體非晶質層，都是由 非摻雜之磷化硼系半導體所構成。 (6) 如申請專利範圍第1項或第2項所記載之磷化硼 系半導體發光元件，其中，前記台座電極之和前記導電性 磷化硼系半導體結晶層相接部份，是由和該當導電性磷化 硼系結晶層發生歐姆接觸之材料所構成。 (7) 如申請專利範圍第6項所記載之磷化硼系半導體 發光元件，其中，前記台座電極之由和前記導電性磷化硼 系半導體結晶層發生歐姆接觸之材料所形成的部份，是延 伸存在於前記導電性磷化硼系半導體結晶層上。 (8) 如申請專利範圍第1項或第2項所記載之磷化硼 系半導體發光兀件’其中’前記台座電極的底面部位，是 由相對前記磷化硼系半導體非晶質層爲非歐姆接觸發生材 料所構成。 (9) 如申請專利範圍第1項或第2項所記載之磷化硼 系半導體發光兀件’其中，前記台座電極，具有：位於前 g己磷化硼系半導體非晶質層上的底面部位，及被形成在該 底面上，形狀中心是一致於該當底面部位之平面形狀之中 心的歐姆電極部位。 (5) (5)200417062 (1 0)如申請專利範圍第9項所記載之磷化硼系半導體 發光元件’其中，前記台座電極的前記歐姆電極部位，是 具有超過前記台座電極之前記底面部位平面積之平面積。 (11) 如申請專利範圍第1 〇項所記載之磷化硼系半導 體發光元件’其中，前記台座電極的前記歐姆電極部位， 是延伸存在至前記導電性磷化硼系半導體結晶層表面上爲 止。 (12) —種磷化硼系半導體發光元件之製造方法，其特 徵爲=以氣相成長法在結晶基板上形成含有發光層的半導 體層；將該半導體層當作基底層且以令結晶基板的溫度爲 250 °C以上120(TC以下之氣相成長法，將該基底層和相反 導電形或高阻抗之磷化硼系半導體非晶質層予以堆積；選 擇性地去除該磷化硼系半導體非晶質層，以使在第1領域 中留下該當磷化硼系半導體非晶質層、使其他以外的第2 領域中前記當作基底層之前記半導體層露出；該當露出之 前記當作基底層之前記半導體層上及前記磷化硼系半導體 非晶質層上’以令結晶基板的溫度爲750C以上1200C以 下之氣相成長法，將導電性磷化硼系結晶層堆積；選擇性 地去除前記第1領域之該導電性磷化硼系結晶層以使前記 磷化硼系半導體非晶質層露出；將結線用台座電極形成在 該當露出之磷化硼系半導體非晶質層上且連接至前記磷化 硼系結晶層；之後’將個別之發光元件予以裁斷。 (1 3)如申請專利範圍第1 2項之磷化硼系半導體發光 元件之製造方法’其中’將位於設置台座電極之前記第1 -8- (6) (6)200417062 領域之導電性磷化硼系半導體結晶層予以去除的同時，一 倂將位於用來個別裁斷、分離發光元件之切斷線之設置領 域的導電性磷化硼系半導體結晶層予以去除，以使下方之 磷化硼系半導體非晶質層的表面露出。 【實施方式】 所謂構成非晶質及導電性之結晶層的磷化硼系半導體 ，係含硼（B )和磷（P )，例如，Β α A1 a Ga r In! _ n r Pi_<5As5(0<6K SI ’ 0 ^ /3 <C 1 5 y 〈1 ， 0< ‘1 ’ 0‘ 5 <1)。或例如 BaAl^Garlni.aj.^P卜 5N5(0< 1)。更具體爲，單體的磷化硼（B P )或磷化硼·鎵·銦（ 組成式 BaGarIni-a-rP: 0<a SI，0$ 7" <1)，氮化磷 硼（組成式B P h Ν 5 : 0 $ 5 < 1 )，砷化磷硼（組成式 B« Pi」Ah )等多數的V族元素之混晶。尤其是，單體的 磷化硼爲磷化硼系半導體層的基材。若以室溫下之禁帶寬 爲2.8〜3.4電子伏特（ev)之寬禁帶之b P基材，則可 以形成寬禁帶的磷化硼系非晶質體或結晶層。可以從將禁 帶寬做成3 · OeV的磷化硼系結晶層，良好地形成關於禁帶 寬例如做成爲2.7eV的III族氮化物半導體所成的發光層 之障壁層或可將發光往外透過的窗（wind〇w)層。 磷化硼系半導體非晶質層或結晶層，例如，可以鹵素 (halogen)法（參考「日本結晶成長學會誌」，ν〇1·24,200417062 (1) (ii) Description of the invention [Technical field to which the invention belongs] The present invention relates to a boron phosphide-based semiconductor device having a boron phosphide-based semiconductor layer having a wide forbidden bandwidth at room temperature, and a method for manufacturing the same. [Prior technology] In recent years, a technology of forming a light emitting element such as a light emitting diode (LED) or a laser diode (LD) using a boron phosphide (chemical formula: BP) layer, which is one of the III-V group compounds, has been used. It has been disclosed (for example, refer to Patent Document 1). In a boron semiconductor, since a hole has a smaller effective mass than an electron, a p-shaped conductive layer is easily obtained (for example, refer to Patent Document 2). Recently, a p-shaped boron phosphide has been known as a light-emitting element provided as an electrode formation layer (contact layer) for forming an ohmic electrode (for example, refer to Patent Document 3). For example, a previous P-shaped electrode provided to contact a contact layer made of a P-shaped boron phosphide provided on a light-emitting layer made of a group III nitride semiconductor layer is made of gold (Au) / zinc. The (Zn) alloy is composed of a single layer (see Patent Document 2 above). It is common practice to provide a boron phosphide-based semiconductor light-emitting device having an electrode on the boron phosphide layer that also serves as a pedestal electrode for wire bonding, and contact it with a P-shaped or n-shaped boron phosphide surface (for example, (See Patent Document 3). [Patent Document 1] US Patent No. 6,069,02 [Patent Document 2] -4- (2) (2) 200417062 Japanese Patent Laid-open No. 2-2 8 8 3 8 8 [Patent Document 3] Japanese Patent Kaiping 1 0-2425 67 [Summary of the Invention] However, at the same time, the bottom part of the electrode was brought into contact with the correct surface of the conductive r-shaped or p-shaped boron phosphide layer, and the structure was set to drive light. The problem that the current (element drive current) supplied by the element flows to the lower layer with a short circuit than the bottom surface of the electrode is always unavoidable. Therefore, for example, in the case of a LED with a boron phosphide crystal layer for providing an electrode above the light-emitting layer, light emission is taken out to the outside. Therefore, if the light-emitting field is to be expanded to increase the light-emitting intensity of a boron phosphide-based semiconductor light-emitting device, the current situation will encounter obstacles. In order to overcome the disadvantages of the prior art, the present invention aims to provide a structure of a wide-range pedestal electrode capable of effectively diffusing element driving current to the light-emitting field, and to provide a boron phosphide-based semiconductor light emitting device having such a pedestal electrode. Element, and a method for manufacturing the boron phosphide-based semiconductor light emitting element. That is, in order to achieve the above object, the present invention provides the following: (1) A boron phosphide-based semiconductor light-emitting element, characterized in that a semiconductor layer containing a light-emitting layer is formed on a crystalline substrate as a base layer; the semiconductor layer A boron phosphide-based semiconductor amorphous layer is formed on the first field of the semiconductor; the boron phosphide-based semiconductor amorphous layer contains a high-impedance boron phosphide-based semiconductor -5- (3) (3) 200417062 bulk A crystalline layer; a high-resistance boron-based semiconductor amorphous layer is formed with a pedestal electrode for wiring; a pre-recorded semiconductor layer as a base layer; a second field other than the first field of the pre-recorded semiconductor layer; conductive phosphorus The boron-based crystal layer is formed so as to arbitrarily extend to a part of the amorphous layer of the former boron phosphide semiconductor; the former pedestal electrode system is in contact with the former boron phosphide-based semiconductor crystal layer from the bottom surface to the upper portion. (2) A boron phosphide-based semiconductor light-emitting device, characterized in that a semiconductor layer containing a light-emitting layer is formed on a crystalline substrate as a base layer; a boron phosphide-based semiconductor non-conductive layer is formed on a first area of the semiconductor layer; Crystalline layer; the boron phosphide-based semiconductor amorphous layer contains a conductive boron phosphide-based semiconductor amorphous layer that is opposite to the semiconductor layer previously described as the base layer; the high-impedance boron-based semiconductor amorphous A base electrode for a junction is formed on the base layer. In the second field other than the first field in the first field, the conductive boron phosphide-based crystal layer is formed to extend arbitrarily in the first field. The boron phosphide-based semiconductor amorphous layer is only a part of the former boron phosphide-based semiconductor crystal layer from the bottom surface to the upper portion. (3) The boron phosphide-based semiconductor light-emitting device described in item 1 or 2 of the scope of the patent application, wherein the boron phosphide-based semiconductor amorphous layer described above is formed so as to be connected to the former description as A boron phosphide-based semiconductor amorphous layer having a semiconductor layer in front of the base layer and having a conductive shape opposite to the semiconductor layer previously described in the base layer, and an amorphous layer of the boron phosphide-based semiconductor having the opposite conductive shape. High-impedance boron phosphide-based semiconductor amorphous layer. -6-(4) (4) 200417062 (4) The boron phosphide-based semiconductor light-emitting device described in item 1 or 2 of the scope of application for a patent, wherein the boron phosphide-based semiconductor amorphous layer described above is composed of Non-doped boron phosphide semiconductor. (5) The boron phosphide-based semiconductor light-emitting device according to item 3 of the scope of the patent application, wherein the two layers of boron phosphide-based semiconductor amorphous that constitute the previously described boron phosphide-based semiconductor amorphous layer and the superimposed laminated structure are described above. The bulk layer is composed of an undoped boron phosphide-based semiconductor. (6) The boron phosphide-based semiconductor light-emitting device described in item 1 or 2 of the scope of the patent application, wherein the contact portion of the sum of the preceding pedestal electrode and the preceding conductive boron-based phosphide semiconductor crystal layer is formed by and This material is made of ohmic contact when the conductive boron phosphide-based crystal layer is in contact. (7) The boron phosphide-based semiconductor light-emitting device described in item 6 of the scope of the patent application, wherein the pre-stage pedestal electrode is formed by a material that is in ohmic contact with the pre-conducting boron-based phosphide semiconductor crystal layer, It is extended on the aforementioned conductive boron phosphide-based semiconductor crystal layer. (8) If the boron phosphide-based semiconductor light-emitting element described in item 1 or item 2 of the scope of the patent application is used, the bottom part of the preposition pedestal electrode is made of Made of ohmic contact generating material. (9) The boron phosphide-based semiconductor light-emitting element described in item 1 or 2 of the scope of the patent application, wherein the pre-stage electrode has a bottom surface located on the amorphous layer of the boron phosphide-based semiconductor amorphous layer. The part and the ohmic electrode part formed on the bottom surface, and the shape center is the center of the planar shape corresponding to the bottom surface part. (5) (5) 200417062 (1 0) The boron phosphide-based semiconductor light-emitting element described in item 9 of the scope of the patent application, wherein the pre-position ohmic electrode portion of the pre-position electrode is a portion having a bottom surface exceeding the pre-position electrode. Flat area. (11) The boron phosphide-based semiconductor light-emitting element described in Item 10 of the scope of the patent application, wherein the pre-position ohmic electrode portion of the pre-position electrode extends to the surface of the pre-conductive boron phosphide-based semiconductor crystal layer. . (12) A method for manufacturing a boron phosphide-based semiconductor light-emitting element, characterized in that a semiconductor layer containing a light-emitting layer is formed on a crystalline substrate by a vapor phase growth method; the semiconductor layer is used as a base layer and the crystalline substrate is The temperature is 250 ° C above 120 (TC below the vapor phase growth method, the base layer and the opposite conductive or high resistance boron phosphide semiconductor amorphous layer are stacked; the boron phosphide based selective removal The semiconductor amorphous layer is such that the boron phosphide-based semiconductor amorphous layer is left in the first field and the semiconductor layer is exposed before the first field is used as the base layer in the second field; As a base layer, the semiconductor boron phosphide-based semiconductor amorphous layer and the boron phosphide-based semiconductor amorphous layer described above are used to deposit a conductive boron phosphide-based crystal layer by a vapor phase growth method in which the temperature of the crystalline substrate is 750C to 1200C; The conductive boron phosphide-based crystalline layer in the first field of the foregoing is removed to expose the amorphous boron phosphide-based semiconductor amorphous layer; the pedestal electrode for the wiring is formed on the exposed boron phosphide-based semiconductor. On the substrate and connected to the boron phosphide-based crystal layer described above; after that, the individual light-emitting elements are cut. (1) If the method of manufacturing a boron-phosphide-based semiconductor light-emitting element according to item 12 of the patent application scope is 'wherein' The conductive boron phosphide-based semiconductor crystalline layer in the field No. 1-8 (6) (6) 200417062, which is located before the mounting of the pedestal electrode, is removed, and the cuts used to individually cut and separate the light-emitting element are simultaneously removed. The conductive boron phosphide-based semiconductor crystal layer in the field where the wire is provided is removed so that the surface of the underlying boron phosphide-based semiconductor amorphous layer is exposed. [Embodiment] The so-called amorphous and conductive crystalline layer Boron phosphide-based semiconductors containing boron (B) and phosphorus (P), for example, β α A1 a Gar In! _ Nr Pi_ < 5As5 (0 < 6K SI '0 ^ / 3 < C 1 5 y 〈 1, 0 < '1' 0 '5 < 1). Or, for example, BaAl ^ Garlni.aj. ^ P 5N5 (0 < 1). More specifically, the monomer boron phosphide (BP) or boron phosphide · Gallium · Indium (composition BaGarIni-a-rP: 0 < a SI, 0 $ 7 " < 1), phosphorus boron nitride (composition BP h Ν 5: 0 $ 5 < 1), mixed crystals of most Group V elements such as boron arsenide (composition B «Pi" Ah). In particular, the boron phosphide of the monomer is the base material of the boron phosphide-based semiconductor layer. At room temperature, the forbidden bandwidth is 2.8 ~ 3.4 electron volts (ev) and the wide-gap b P substrate can form a boron phosphide-based amorphous body or crystalline layer with a wide forbidden band. A boron phosphide-based crystal layer of 3 · OeV forms a barrier layer with good forbidden bandwidth, such as a light-emitting layer made of a 2.7eV III-nitride semiconductor, or a window (window) through which light can be transmitted outward. Floor. The boron phosphide-based semiconductor amorphous layer or crystalline layer may be, for example, a halogen method (refer to "Journal of the Japan Society for Crystal Growth", ν〇1 · 24,
No.2 ( 1 99 7)5p. 150)、氮化法（參考 j.Crystal Growth， (7) (7)200417062 24/25 ( 1 974)，ρ·1 93 - 1 9 6 )分子束磊晶法（參考 j.Solid Satate Chem” 1 3 3 ( 1 99 7)，p.269-272 )、有機金屬化學氣相 堆積（MOCVD)法（參考 Inst.Phys.Conf.Ser·，Νο.129(ΙΟΡ Publishing Ltd.(UK，1993)，ρ·157-162)等氣相成長法爲適當 。尤其是’ M0CVD法係以三甲基硼（（c2H5 ) 3Β )等易 分解性物質爲硼源，因此可以比較低溫使非晶質層氣相成 長，是有效的成長手段。若依照這些氣相成長手段，當由 磷化硼系半導體所成之非晶質層形成之際，120 (TC以下爲 合適。在超過1200 °C的高溫下，會導致Β13Ρ2等之硼多量 體之發生，會阻礙以單體之磷化硼（Β Ρ )爲基材之磷化 硼系半導體的成長。另一方面，可以氣相成長領域將構成 非晶質之磷化硼系半導體之元素（構成元素）之原料充分 予以熱分解，以可促進成膜的25 0°C以上爲合適。一般而 言，若氣相成長溫度爲超過1 0 0 0 °C的高溫，則可容易 獲得呈現P形傳導的非晶質層或結晶質層。η形傳導之非 晶質層或結晶質層，係在1 〇〇〇 t未滿的溫度下形成而獲 得。 在利用上記手段以使磷化硼系非晶質層的有效率地氣 相成長中，所謂的ν/ΙΙΙ比率要設定在0.2〜50之範圍是 很重要的。「V/III比率」係’意指磷等第V族構成元素 之合計濃度比率對於供應給磷化硼系半導體層之成長實施 領域（成長領域）的第I11族構成元素之合計濃度的比率 。若該v /111比率爲〇 · 2未滿之極端的低比率’則富含硼 之球體會多發，而無法穩定獲得平坦表面之非晶質層’造 -10- (8) (8)200417062 成不良。超過50的V/III比率，會導致多晶層之形成， 對於要穩定獲得非晶質層來說並非合適。本發明中所謂結 晶層，係指單晶所成之層、非晶質和早晶所成之多晶層、 配向性互異之單晶所成之多晶層中之任何一者。磷化硼系 結晶層，在V/III比率爲100以上，更理想爲5 00以上 2000以下，就可穩定形成。在超過2 0 0 0的高比率時 時，會產含磷等之第V族元素的析出物，導致較難獲得平 坦表面之磷化硼系半導體結晶層，是爲不良。非晶質、多 晶或單晶，一般可以X線繞射或電子線繞射技法來判別。 將氣相成長而成的半導體層當作基底層而設置之磷化 硼系半導體非晶質層，理想爲，由傳導性異於（相反於） 基底層之半導體層的非晶質層，或此等層之重疊層積構造 所構成。高阻抗之磷化硼系半導體非晶質層之阻抗率理想 爲室溫下爲1 〇 Ω · cm以上，較理想爲102 Ω · cm以上。 和基底層相反的傳導形，例如，當基底層爲η形層時，所 指則爲 Ρ形。非晶質層，例如，氮化銦鎵（組成式 GaxIni_xN : OS XS 1 )所成之發光層，或氮化鎵鋁（組成 式AlxGa】_xN: 0SXS1)所成之包覆（clad)障壁層，理 想爲當作基底層而形成。爲了方便起見，將高阻抗之非晶 質層稱爲「高阻抗非晶質層」，將傳導性和基底層相反的 非晶質層稱爲「相反導電形非晶質層」，重點是，配置在 發光層或障壁層上之台座電極的底面下，亦即，台座電極 之投影領域中，要設置高阻抗非晶質層或相反導電形非晶 質層之其中一者。將台座電極之底面設在高阻抗非晶質層 -11 - (9) (9)200417062 上的構成中，高阻抗非晶質層係發揮阻礙元件驅動電流 由台座電極底面往下方之發光層之短路流通的阻抗體之作 用。又，將台座電極之底面設在傳導性和基底層相反之非 晶質層上的構成當中，導電性非晶質層係和基底層形成 Pn接合構造，而具有阻礙元件驅動電流從台座電極底面 往下方之發光層的短路流通之作用。高阻抗非晶質層或相 反導電形非晶質層的形成領域（第1領域）並無必要是和 台座電極底面的形成領域（第3領域）相同，只要是包含 台座電極底面（台座電極之投影領域）之至少一部份的領 域就有效果。可是，構成不讓元件驅動電流通過之pn接 合構造的相反導電形非晶質層或高阻抗非晶質層，理想爲 ，限定在台座電極投影領域及其周圍而設置。高阻抗非晶 質層或相反導電形非晶質層若被形成在台座電極的投影領 域，則可防止元件驅動電流從台座電極底面往下方之發光 層的短路流通，而可防止被台座電極遮光之發光層領域處 的發光產生，另一方面，爲了使元件驅動電流完全充分地 通過基底層，上記第1領域以外之領域（第2領域）中所 形成之導電性結晶層，理想爲，和基底半導體層的接觸面 積爲廣。若在台座電極的投影領域以外之領域（第2領域 )中形成寬廣的高阻抗非晶質層或相反導電形非晶質層， 例如在發光層上全面設置，就可使元件驅動電流完全充分 地通過基底層，抑制高發光強度之L E D之不良的產生。 甚至，若將高阻抗非晶質層，和傳導性相反於基底層 之導電性非晶質層予以層積來構成磷化硼系半導體非晶質 -12- (10) (10)200417062 層，則可更有效地防止上述之元件驅動電流的短路流通。 先於基底層上設置相反導電形非晶質層，再於其上層積高 阻抗非晶質層者爲理想。藉由使高阻抗非晶質層爲隔著而 存在，可使得流往形成pn接合之相反導電形非晶質層與 基底層之接合部的元件驅動電流更加減少而提升效果。 高阻抗非晶質層的層厚，在設置台座電極之底面部位 領域中，能將基底層表面均勻地覆蓋上2nm以上爲合適 。相反導電形非晶質層，則以不讓穿隧效應所致之載子往 基底層通過之5 Onm以上爲合適。高阻抗非晶質層或相反 導電形非晶質層之層厚若超過200nm，則後述之歐姆電極 與磷化硼系半導體結晶層之表面的落差會增加，對於要形 成和磷化硼系半導體結晶層之間的密著性優良的電極來說 會是障礙，而非理想。 在形成底面是接觸至相反導電形或高阻抗之非晶質層 的台座電極時，首先，令相反導電形非晶質層或高阻抗非 晶質層在基底層上成長後，將包含台座電極形成領域之第 1領域所在之相反導電形或高阻抗非晶質層予以選擇性地 去除’接者’令導電性之憐化砸系結晶層成長後，將存在 於台座電極形成領域的導電性磷化硼系結晶層去除，讓相 反導電形或高阻抗非晶質層的表面露出。然後，在露出之 非晶質層表面上，只要能覆蓋上適合構成台座電極底面的 材料就能形成。磷化硼系非晶質層及磷化硼系結晶層，例 如，以公知的氯（C1 )系電漿鈾刻手法等進行蝕刻則可予 以去除。若要使反導電形或高阻抗非晶質層在台座電極下 -13- (11) (11)200417062 之領域中選擇性地殘留，則使用光微影技術即可。只要是 設置台座電極的平面領域，在設置台座電極之底面時，利 用公知技術的光微影技術的選擇性圖案化技術者爲理想。 無論是將台座電極底面設置在反導電形或高阻抗之任何非 晶質層表面上之情況，都可藉由底面部位，而可阻礙元件 驅動電流往其投影領域所在下方的發光層之短路性流通。 甚至，由於可使元件驅動電流優先供給至遮蔽對外部發光 之台座電極投影領域以外的發光領域，因此，例如可對獲 得高發光強度之L E D有所貢獻。 若在非晶質層中，故意不添加不純物，而成爲所謂非 摻雜（undope)構成，則對防止基底層的發光層或障壁層在 電氣上或結晶上的變質是具有效果的。於先前之將故意添 加（doping)鎂（Mg)的氮化鎵（GaN)層設在η形發光層上 而成的層積構造中，Ρ形不純物的鎂的熱擴散導致的發光 層之高阻抗化，或於量子阱構造的發光層中，可避免障壁 (barrier)層和眺（well)層之異質接合界面之雜亂化。在磷 化硼系半導體所成之非晶質層中，其傳導度，只要能夠調 整其氣相成長的溫度（成長溫度）及上記V/III比率就可 控制。成長溫度爲越低溫，且V/III比率設定得越低，則 可獲得越高阻抗的非晶質層。以高溫、高V/III比率來令 其氣相成長則可形成低阻抗的非晶質層。作爲評判磷化硼 系半導體非晶質層的導電性之尺度的阻抗率，通常可藉由 電洞效應測定法來計測。 除了反對導電形或高阻抗之非晶質層所致之防止元件 -14- (12) (12)200417062 驅動電流短路流通的機目^ ’右以相封於憐化硼系半導體爲 非歐姆接觸性之材料來構成台座電極的底面部位，則更能 提升元件驅動電流的短路流通阻止效果。所謂非歐姆接觸 性，是指類似蕭特基（Schottky )接合而呈整流性的接觸 。本發明中，尤其，亦包含接觸阻抗爲超過1 X 1〇_3 Ω · cm之接觸。台座電極的底面部位之材料，是隨著磷化硼 系半導體非晶質層之傳導形而不同。對於高阻抗且爲p形 磷化硼系半導體非晶質層，底面部位是由例如，金（Au) · 鍺（Ge)、金（Au) ·錫（Sn)、金（Au) ·銦（In)等之金合金所 構成。對於η形磷化硼系半導體非晶質層，則底面部位是 由例如，金（An) ·鋅（Ζη)、金（Au) ·鈹（Be)等之金合金所 構成。又，不論非晶質層的傳導形，都可由過渡金屬構成 具有整流性之底面部位。呈現蕭特基整流性的材料中，可 例舉的有：鈦（Ti)、鉬（Mo)、釩（V)、鉅（Ta)、給（Hf)及 鎢（W)等。 構成接觸磷化硼系半導體非晶質層之表面而設置之底 面部位的被膜上，設有由磷化硼系半導體結晶層呈歐姆接 觸之材料所構成的歐姆電極。構成歐姆電極的材料，是視 磷化硼系半導體結晶層的傳導形而選擇。對於P形磷化硼 系半導體結晶層來說，可用金•鋅、金•鈹等之金合金來 構成。對於η形磷化硼系半導體結晶層來說，可用金·鍺 、金·錫、金·銦等之金合金來構成。只要是設置台座電 極之底面部位的磷化硼系半導體非晶質層，和設置歐姆電 極的磷化硼系半導體結晶層，彼此互爲相反之傳導層，台 -15- (13) (13)200417062 座電極底面部位和底面部位上之歐姆電極就可用同一材料 來構成。□例如，令底面部位接觸至P形磷化硼系半導體 非晶質層，令歐姆電極接觸至η形磷化硼系結晶層所構成 的台座電極之情況下，底面部位和歐姆電極都可一倂使用 金·鍺合金來構成。以鈮（Nb)、鉻（Cr)及上記之過渡金屬 皆不適合用來構成蕭特基整流性與歐姆電極兩者。 若令平面積超過台座電極底面部位的底面積，且令賦 予超過底面積之平面積的部位延展至磷化硼系半導體結晶 層表面爲止並和其相接而配置，則可形成密著於磷化硼系 半導體結晶層表面的歐姆電極。在含有接觸至憐化硼系半 導體非晶質層而設置之底面的底面部位形成後，將構成歐 姆電極的材料披覆以使其接觸底面部位且亦接觸磷化硼系 半導體結晶層，例如若爲圓形底面則成爲直徑較大之圓形 電極，利用公知的光微影技術來加工歐姆電極材料就可形 成。此時，將位於底面部位之圓形領域更外緣的歐姆電極 部位，和磷化硼系半導體結晶層表面予以密著。底面部位 的平面形狀，和歐姆電極的平面形狀，並不需要一定爲相 似形。例如，令底面部位的平面形狀爲圓形，而歐姆電極 的平面形狀卻爲正方形。可是，底面部位的平面形狀的中 心和歐姆電極的平面形狀的中心通常爲一致，而形成和磷 化硼系半導體結晶層以平面等方強度密著之台座電極者， 尤其理想。 若將歐姆電極配置成和密著於磷化硼系半導體結晶層 而設置的歐姆電極呈電性導通，且，在磷化硼系半導體結 -16- (14) (14)200417062 晶層表面延展，則因可將元件驅動電流分配至台座電極投 影領域以外的發光領域，故爲理想。亦即，在讓發光穿透 磷化硼系半導體結晶層而往外部取出之方式的LED中， 不會被台座電極遮光，而可使元件驅動電流，平面地擴散 至適合將發光取出至外部的發光領域。此種延展存在的歐 姆電極，具有使存在於其投影領域中之被台座電極阻礙了 往發光層短路流通的元件驅動電流，往發光領域呈廣範圍 擴散之作用，而對製造高發光強度LED上可有貢獻。在 磷化硼系半導體結晶層表面延展設置的歐姆電極，亦可以 異於構成台座電極之歐姆電極之材料來構成。例如，台座 電極之歐姆電極是由金·鍺合金構成時，延展之歐姆電極 可由金•錫合金來構成。延展之歐姆電極，就與磷化硼系 半導體結晶層的密著性良好而言，與其使用第III族元素 之鎵（G a)或銦（I η)等，更可使用第IV族元素的錫（S η)、鍺 (G e)等來理想構成。若能使台座電極和延展之歐姆電極以 同一材料構成，則可同時構成兩者，而可簡化工程就能獲 得磷化硼系半導體發光元件。 延展之歐姆電極，以遍佈台座電極的投影領域以外的 發光領域，可均勻地分配元件驅動電流而配置者爲理想。 亦即’能夠使電位均等分布於於磷化硼系半導體結晶層表 面上，甚至發光層表面上的配置者，較爲理想。延展之歐 姆電極，可以由能和台座電極呈電性導通的帶狀、圓盤狀 、或框狀電極來構成。此外，可以將這些帶狀電極或框狀 電極等予以組合而彼此導通來構成。構成帶狀、圓盤狀或 -17- (15) (15)200417062 框狀等電極之線狀電極，考慮在即使流通之元件驅動電流 增加的情況下也不會斷線，線寬通常在1 0 // m以上，更 理想爲20 // m以上者爲理想。若是利用公知的光微影技 術與圖案化技術和選擇蝕刻技術，則可將所望形狀及線寬 之線狀電極，敷設於磷化硼系半導體結晶層的表面上。 磷化硼系半導體發光元件，係在台座電極或附屬於台 座電極的歐姆電極形成後，將元件個別裁斷而製造。個別 元件之切斷，通常，是利用在基板上沿著結晶劈開方向設 置裁斷線，一般稱爲切割道 （scribe line)或裁斷線（dicing line)的直現狀溝而實施。本發明中，因爲如上記將台座電 極底面部位設置成接觸至磷化硼系半導體非晶質層，因此 需要去除設置底面部位之領域所在的磷化硼系半導體結晶 層。如與此同時地形成用來裁斷個別元件的裁斷線之溝， 則可以簡略的工程來獲得磷化硼系半導體發光元件。因此 ，在本發明中，在台座電極底面部位形成領域上令非晶質 層表面露出的同時，於裁斷線設置領域上令磷化硼系半導 體非晶質層表面露出而形成裁斷用途的溝。該裁斷用途的 溝，例如，以立方晶閃鋅礦型結晶爲基板時，若設置在與 劈開方向呈垂直的< 11 〇>結晶方位上則爲理想。裁斷用途 之溝（裁斷線）之寬度，考慮裁斷用器具的刀刃接觸不致 造成溝側面的磷化硼系半導體結晶層太大損傷，以充分的 寬度爲合適。一般而言，以40 μηι以上70//m以下者爲 合適。若超過7〇 V m，則溝的寬度會有多餘，因此裁斷器 具的刀鋒走向會在一個範圍內游移。因爲刀鋒的游移而無 -18- (16) 200417062 法直線行走，故裁斷後很難獲得斷面平 【作用】 配置在台座電極之底面下的高阻抗 導電形之磷化硼系半導體非晶質層，具 上之台座電極之底面而供給之元件驅動 電極下方之發光層的短路性流入之作用 相對於磷化硼系半導體呈非歐姆接 台座電極之底面，具有迴避透過台座電 電流往下方之磷化硼系半導體非晶質層 用。 接觸於台座電極之一部份的底面部 於底面部位之底面積的平面積，接觸於 晶層表面而設置的歐姆電極，具有和磷 密著性極佳之台座電極的作用。 令構成台座電極之一'部份的歐姆電 延展至磷化硼系半導體結晶層表面而設 有將元件驅動電流廣範圍地分配至發光 (第1實施例） 茲以構成具備了具有與高阻抗之磷 面相接之底面的台座電極的發光二極體 例，具體說明本發明所涉之磷化硼系半 1係將用以製作雙異質（DH)接合構造之 的個別元件。 或與基底層爲相反 有防止透過設於其 電流，往位於台座 〇 觸之材料所構成的 極供給之元件驅動 的短路性流通之作 位而設置，具有大 磷化硼系半導體結 化硼系半導體層的 極呈電性導通，且 置之歐姆電極，具 領域之作用。 化硼系非晶質層表 (LED)之情形爲 導體發光元件。圖 .LED10所使用之 (17) (17)200417062 層積構造體1 1的剖面構造模式圖。No. 2 (1 99 7) 5p. 150), nitriding method (refer to j. Crystal Growth, (7) (7) 200417062 24/25 (1 974), ρ · 1 93-1 9 6) Crystal method (refer to j.Solid Satate Chem "1 3 3 (1 99 7), p.269-272), organometallic chemical vapor deposition (MOCVD) method (refer to Inst.Phys.Conf.Ser ·, No.129 (IOP Publishing Ltd. (UK, 1993), ρ157-162) and other vapor growth methods are suitable. In particular, the M0CVD method uses trimethylboron ((c2H5) 3B) as a source of boron Therefore, it is an effective growth method to vapor-phase grow an amorphous layer at a relatively low temperature. According to these vapor-phase growth methods, when an amorphous layer formed of a boron phosphide-based semiconductor is formed, the temperature is 120 (TC or less). It is suitable. At a high temperature exceeding 1200 ° C, it will cause the occurrence of boron multimers such as B13P2, which will hinder the growth of boron phosphide-based semiconductors based on monomeric boron phosphide (B P). On the other hand, in the field of vapor phase growth, raw materials constituting amorphous boron phosphide-based semiconductors (constituting elements) are sufficiently thermally decomposed to promote film formation at 25 ° C. The above is suitable. In general, if the vapor phase growth temperature is a high temperature exceeding 100 ° C, an amorphous layer or a crystalline layer exhibiting P-type conduction can be easily obtained. An n-type conducting amorphous layer Or a crystalline layer is formed at a temperature of less than 1,000 t. The so-called ν / ΙΙΙ ratio is used to efficiently vapor-phase grow a boron phosphide-based amorphous layer using the method described above. It is important to set it within the range of 0.2 to 50. "V / III ratio" means' total concentration ratio of Group V constituent elements such as phosphorus to the growth implementation field (growth field) for the supply of boron phosphide-based semiconductor layers. ) Is the ratio of the total concentration of the group I11 constituent elements. If the v / 111 ratio is an extremely low ratio of less than 0.2, then boron-rich spheres will occur frequently, and amorphous surfaces with flat surfaces cannot be obtained stably. The formation of the layer is not good (-10-) (8) 200417062. A V / III ratio of more than 50 will result in the formation of a polycrystalline layer, which is not suitable for obtaining an amorphous layer stably. The so-called crystal in the present invention Layer, refers to the layer made of single crystal, amorphous and early crystal Any one of the polycrystalline layers made of single crystals with different orientations. The boron phosphide-based crystalline layer can be formed stably at a V / III ratio of 100 or more, more preferably 5 or more and 2000 or less. When the ratio exceeds 2000, a precipitate of a Group V element containing phosphorus or the like is produced, which makes it difficult to obtain a boron phosphide-based semiconductor crystal layer having a flat surface, which is a disadvantage. Amorphous, polycrystalline or single crystal can usually be identified by X-ray diffraction or electron diffraction. A boron phosphide-based semiconductor amorphous layer provided with a semiconductor layer formed by vapor phase growth as a base layer is preferably an amorphous layer having a conductivity different from (opposite to) the semiconductor layer of the base layer, or These layers are composed of overlapping laminated structures. The resistivity of the high-impedance boron phosphide-based semiconductor amorphous layer is preferably 10 Ω · cm or more at room temperature, and more preferably 102 Ω · cm or more. The conductive shape is opposite to the base layer. For example, when the base layer is an n-shaped layer, it refers to a P-shape. An amorphous layer, for example, a light-emitting layer made of indium gallium nitride (compositional formula GaxIni_xN: OS XS 1), or a clad barrier layer made of aluminum gallium nitride (compositional formula AlxGa] _xN: 0SXS1) Ideally formed as a base layer. For the sake of convenience, the high-resistance amorphous layer is referred to as a "high-resistance amorphous layer", and the amorphous layer having the opposite conductivity to the base layer is referred to as the "opposite conductive amorphous layer". The main point is Under the bottom surface of the pedestal electrode disposed on the light-emitting layer or the barrier layer, that is, in the projection area of the pedestal electrode, one of a high-resistance amorphous layer or an opposite conductive amorphous layer should be provided. In the structure in which the bottom surface of the pedestal electrode is provided on the high-resistance amorphous layer -11-(9) (9) 200417062, the high-resistance amorphous layer functions as a light-emitting layer that blocks the drive current of the element from the bottom surface of the pedestal electrode. The role of the short-circuit resistance body. In addition, in a configuration in which the bottom surface of the pedestal electrode is provided on an amorphous layer having an opposite conductivity to the base layer, the conductive amorphous layer system and the base layer form a Pn junction structure, and it has a function of preventing element driving current from flowing from the bottom surface of the pedestal electrode. The short-circuit flow of the light-emitting layer downward. The formation area of the high-resistance amorphous layer or the opposite conductive amorphous layer (the first area) is not necessarily the same as the formation area of the bottom surface of the pedestal electrode (the third area), as long as it includes the bottom surface of the pedestal electrode (the area of the pedestal electrode). Projection field) at least part of the field is effective. However, the opposite conductive amorphous layer or the high-resistance amorphous layer that constitutes a pn junction structure that does not allow element drive current to pass therethrough is ideally provided in the area of the projection of the pedestal electrode and its surroundings. If the high-impedance amorphous layer or the opposite conductive amorphous layer is formed in the projection area of the pedestal electrode, it can prevent the short-circuit flow of the element driving current from the bottom surface of the pedestal electrode to the light-emitting layer below, and can prevent light from being blocked by the pedestal electrode. On the other hand, in order to allow the element driving current to fully pass through the base layer, the conductive crystal layer formed in a field other than the first field (second field) is preferably, and The contact area of the base semiconductor layer is wide. If a wide high-impedance amorphous layer or an oppositely conductive amorphous layer is formed in a field other than the projection field of the pedestal electrode (second field), for example, if the light-emitting layer is provided in its entirety, the device driving current can be fully sufficient. Through the ground layer, the occurrence of LED defects with high luminous intensity is suppressed. Furthermore, if a high-impedance amorphous layer and a conductive amorphous layer having a conductivity opposite to that of the base layer are laminated to form a boron phosphide-based semiconductor amorphous -12- (10) (10) 200417062 layer, It is possible to more effectively prevent the short-circuit flow of the above-mentioned element driving current. It is desirable that an opposite conductive amorphous layer is provided on the base layer, and then a high-resistance amorphous layer is laminated thereon. The existence of the high-resistance amorphous layer in a spaced relationship can further reduce the element driving current flowing to the junction of the opposite conductive amorphous layer and the base layer forming the pn junction, thereby improving the effect. The thickness of the high-resistance amorphous layer is suitable for uniformly covering the surface of the base layer with a thickness of 2 nm or more in the area where the bottom surface of the pedestal electrode is provided. On the other hand, the conductive amorphous layer is preferably 5 nm or more, which does not allow carriers caused by the tunneling effect to pass through the base layer. If the thickness of the high-resistance amorphous layer or the oppositely conductive amorphous layer exceeds 200 nm, the difference between the surface of the ohmic electrode and the boron phosphide-based semiconductor crystal layer described later will increase. An electrode with excellent adhesion between the crystal layers is an obstacle, but is not ideal. When forming a pedestal electrode whose bottom surface is in contact with an amorphous layer of opposite conductivity or high impedance, first, the opposite conductive amorphous layer or high impedance amorphous layer is grown on the base layer, and then the pedestal electrode is included. In the first field of the formation field, the opposite conductive or high-resistance amorphous layer is selectively removed, and the "conductor" is selectively removed to make the conductive crystal layer grow, and the conductivity existing in the pedestal electrode formation field The boron phosphide-based crystal layer is removed, and the surface of the opposite conductive or high-resistance amorphous layer is exposed. Then, the surface of the exposed amorphous layer can be formed as long as it can be covered with a material suitable for forming the bottom surface of the pedestal electrode. The boron phosphide-based amorphous layer and the boron phosphide-based crystal layer can be removed by, for example, etching using a known chlorine (C1) -based plasma uranium engraving method or the like. If the anti-conductivity or high-resistance amorphous layer is selectively left in the field under the pedestal electrode, a photolithography technique can be used. As long as it is a flat area where the pedestal electrode is provided, when the bottom surface of the pedestal electrode is provided, a selective patterning technique using a photolithography technique of a known technique is desirable. Regardless of whether the bottom surface of the pedestal electrode is arranged on the surface of any amorphous layer of anti-conductivity or high resistance, the short-circuit property of the light-emitting layer under the projection area of the element can be prevented by the bottom surface portion. Circulation. In addition, since the element driving current can be preferentially supplied to a light-emitting area other than the projection area of the pedestal electrode that shields external light, for example, it can contribute to obtaining a LED with a high light-emitting intensity. If an impurity is intentionally added to the amorphous layer and a so-called undope structure is formed, it is effective to prevent the light-emitting layer or the barrier layer of the base layer from being electrically or crystallinely altered. In the previous laminated structure in which a gallium nitride (GaN) layer intentionally doped with magnesium (Mg) was provided on the n-shaped light emitting layer, the light emitting layer caused by thermal diffusion of magnesium in the P-shaped impurity was high. Impedance or the light emitting layer of the quantum well structure can avoid the disorder of the heterojunction interface between the barrier layer and the well layer. The conductivity of an amorphous layer formed of a boron phosphide-based semiconductor can be controlled as long as the vapor phase growth temperature (growth temperature) and the above-mentioned V / III ratio can be adjusted. The lower the growth temperature and the lower the V / III ratio, the higher the resistance of the amorphous layer can be obtained. A low-impedance amorphous layer can be formed by vapor-phase growth at a high temperature and a high V / III ratio. The resistivity, which is a measure of the conductivity of the boron phosphide-based semiconductor amorphous layer, is usually measured by a hole effect measurement method. Except for preventing the conductive element or the high-resistance amorphous layer from preventing the element -14- (12) (12) 200417062 The driving current is short-circuited. ^ 'Right side is sealed with a boron-based semiconductor as a non-ohmic contact. The bottom part of the base electrode is made of a material made of a flexible material, which can further improve the short-circuit prevention effect of the device driving current. The so-called non-ohmic contact refers to a rectifying contact similar to a Schottky junction. In the present invention, in particular, a contact having a contact resistance exceeding 1 X 10-3 Ω · cm is also included. The material of the bottom surface portion of the pedestal electrode differs according to the conductive shape of the boron phosphide-based semiconductor amorphous layer. For a high-impedance p-type boron phosphide-based semiconductor amorphous layer, the bottom surface portion is made of, for example, gold (Au) · germanium (Ge), gold (Au) · tin (Sn), gold (Au) · indium ( In) and other gold alloys. For an n-type boron phosphide-based semiconductor amorphous layer, the bottom surface portion is made of, for example, a gold alloy such as gold (An) · zinc (Zη), gold (Au) · beryllium (Be). Regardless of the conductive shape of the amorphous layer, the bottom surface portion having a rectifying property may be formed of a transition metal. Among the materials exhibiting Schottky rectification, titanium (Ti), molybdenum (Mo), vanadium (V), giant (Ta), donor (Hf), and tungsten (W) can be exemplified. An ohmic electrode made of a material that makes the crystalline layer of the boron phosphide-based semiconductor to be in ohmic contact is provided on the film constituting the bottom surface portion provided in contact with the surface of the amorphous layer of the boron phosphide-based semiconductor. The material constituting the ohmic electrode is selected depending on the conductive shape of the boron phosphide-based semiconductor crystal layer. For a P-shaped boron phosphide-based semiconductor crystal layer, a gold alloy such as gold, zinc, gold, or beryllium can be used. The n-shaped boron phosphide-based semiconductor crystal layer can be made of a gold alloy such as gold · germanium, gold · tin, gold · indium, or the like. As long as it is a boron phosphide-based semiconductor amorphous layer provided with a bottom surface portion of a pedestal electrode and a boron phosphide-based semiconductor crystal layer provided with an ohmic electrode, the conductive layers are opposite to each other. -15- (13) (13) 200417062 The bottom surface of the base electrode and the ohmic electrode on the bottom surface can be made of the same material. □ For example, when the bottom surface part is in contact with a P-shaped boron phosphide-based semiconductor amorphous layer and the ohmic electrode is in contact with a pedestal electrode composed of an η-shaped boron phosphide-based crystal layer, both the bottom surface part and the ohmic electrode may be Rhenium is made of a gold-germanium alloy. Niobium (Nb), chromium (Cr) and the transition metals described above are not suitable for forming both Schottky rectification and ohmic electrodes. If the flat area exceeds the bottom area of the bottom surface portion of the pedestal electrode, and the portion provided with the flat area exceeding the bottom area extends to the surface of the boron phosphide-based semiconductor crystal layer and is disposed in contact with the surface, it can form close adhesion to phosphorous. An ohmic electrode on the surface of a boron-based semiconductor crystal layer. After the bottom surface portion containing the bottom surface provided in contact with the boron-based semiconductor amorphous layer is formed, cover the material constituting the ohmic electrode so that it contacts the bottom surface portion and also contacts the boron phosphide-based semiconductor crystal layer. For example, if The circular bottom surface becomes a circular electrode with a larger diameter, which can be formed by processing the ohmic electrode material using a known photolithography technique. At this time, the ohmic electrode portion located at the outer edge of the circular area on the bottom surface portion is adhered to the surface of the boron phosphide-based semiconductor crystal layer. The planar shape of the bottom surface part and the planar shape of the ohmic electrode need not necessarily be similar. For example, the planar shape of the bottom surface portion is circular, while the planar shape of the ohmic electrode is square. However, the center of the planar shape of the bottom surface portion and the center of the planar shape of the ohmic electrode are usually the same, and it is particularly preferable to form a pedestal electrode that is in close contact with the boron phosphide-based semiconductor crystal layer with a plane equal strength. If the ohmic electrode is arranged so as to be electrically conductive with the ohmic electrode provided in close contact with the boron phosphide-based semiconductor crystal layer, and the surface of the boron phosphide-based semiconductor junction -16- (14) (14) 200417062 is extended , Since the element driving current can be distributed to a light emitting area other than the projection area of the pedestal electrode, it is ideal. That is, in an LED that emits light through a boron phosphide-based semiconductor crystal layer and extracts it to the outside, the LED is not shielded by the pedestal electrode, and the element driving current can be spread to a plane suitable for extracting the light to the outside. Glowing sphere. Such an extended ohmic electrode has a device driving current that is blocked by a pedestal electrode in the projection field and short-circuited to the light-emitting layer, and has a wide-range diffusion effect in the light-emitting field. Can contribute. The ohmic electrode extended on the surface of the boron phosphide-based semiconductor crystal layer may be made of a material different from the ohmic electrode constituting the base electrode. For example, when the ohmic electrode of the pedestal electrode is made of gold-germanium alloy, the extended ohmic electrode may be made of gold-tin alloy. The extended ohmic electrode has good adhesion to the boron phosphide-based semiconductor crystal layer. Instead of using a group III element such as gallium (G a) or indium (I η), a group IV element can be used. Tin (S η), germanium (G e), and the like are ideally constituted. If the pedestal electrode and the extended ohmic electrode can be made of the same material, both can be formed at the same time, and the boron phosphide-based semiconductor light-emitting element can be obtained by simplifying the process. The extended ohmic electrode is ideally arranged in a light-emitting area other than the projection area of the pedestal electrode, and can evenly distribute the element drive current. That is, it is preferable to arrange the potential evenly on the surface of the boron phosphide-based semiconductor crystal layer and even on the surface of the light emitting layer. The extended ohmic electrode may be composed of a band-shaped, disc-shaped, or frame-shaped electrode that can be electrically connected to the pedestal electrode. In addition, these band electrodes, frame electrodes, and the like may be combined to be electrically connected to each other. Line electrodes that form a strip, disc, or -17- (15) (15) 200417062 frame-shaped electrodes. It is considered that the wire will not be disconnected even if the driving current of the flowing component increases. The line width is usually 1 0 // m or more, more preferably 20 // m or more is ideal. By using a known photolithography technique, patterning technique, and selective etching technique, a linear electrode having a desired shape and line width can be laid on the surface of a boron phosphide-based semiconductor crystal layer. The boron phosphide-based semiconductor light-emitting element is manufactured after the base electrode or an ohmic electrode attached to the base electrode is formed, and the element is individually cut. The cutting of individual components is usually carried out by using a straight groove in which a cutting line, which is generally called a scribe line or a dicing line, is provided on the substrate along the direction of cleavage of crystals. In the present invention, since the base electrode portion of the pedestal electrode is provided in contact with the boron phosphide-based semiconductor amorphous layer as described above, it is necessary to remove the boron phosphide-based semiconductor crystal layer in the region where the base electrode portion is provided. If grooves for cutting lines for cutting individual elements are formed at the same time, a simple process can be used to obtain a boron phosphide-based semiconductor light-emitting element. Therefore, in the present invention, while the surface of the amorphous layer is exposed in the formation area of the bottom surface of the pedestal electrode, the surface of the amorphous layer of the boron phosphide-based semiconductor is exposed in the cutting line installation area to form a groove for cutting. For this cutting groove, for example, when a cubic sphalerite crystal is used as a substrate, it is preferable to provide the groove in a < 11 〇 > crystal orientation perpendicular to the cleavage direction. The width of the groove (cut line) used for cutting is considered to be sufficient because the contact of the cutting edge of the cutting tool will not cause too much damage to the boron phosphide-based semiconductor crystal layer on the side of the groove. In general, a value of 40 μm to 70 // m is suitable. If it exceeds 70 V m, the width of the groove will be excessive, so the cutting edge of the cutting tool will move within a range. Because of the blade's movement without -18- (16) 200417062 straight walking, it is difficult to obtain a flat cross-section after cutting. [Action] High-impedance conductive boron phosphide-based semiconductor amorphous placed under the base of the pedestal electrode Layer, the short-term inflow of the light-emitting layer below the element driving electrode supplied from the bottom surface of the base electrode is relatively non-ohmic to the bottom surface of the base electrode relative to the boron phosphide-based semiconductor, and has the ability to avoid the electrical current passing through the base to go down For boron phosphide semiconductor amorphous layer. An ohmic electrode provided in contact with the bottom surface of a portion of the pedestal electrode, a flat area of the bottom surface portion, and in contact with the surface of the crystal layer, serves as a pedestal electrode with excellent adhesion to phosphorus. The ohmic electricity constituting one of the pedestal electrodes is extended to the surface of the boron phosphide-based semiconductor crystal layer, and a wide range of element driving current is distributed to light emission (first embodiment). An example of a light-emitting diode of a pedestal electrode with a phosphorous surface on the bottom surface will specifically describe an individual element of the boron phosphide-based semi-first system according to the present invention to be used to fabricate a double heterogeneous (DH) junction structure. Or it is set opposite to the base layer to prevent short-circuit flow driven by the device provided by the current provided on the base and made of material that is contacted with the base. It has a large boron phosphide-based semiconductor and a boron-based semiconductor. The electrodes of the semiconductor layer are electrically conductive, and the ohmic electrode is placed in the field, which has a role in the field. In the case of a boron-based amorphous layer surface (LED), it is a conductive light emitting element. Fig. (17) (17) 200417062 The cross-sectional structure pattern of the laminated structure 11 used in LED10.
基板1 0 1上，使用了摻磷（P ) η形砂（S i)單晶。基板 1 0 1的表面上，利用常壓（略大氣壓）有機金屬氣相磊晶 (MOVPE )手段，堆積n形之磷化硼（BP)所成之下部包層 102。下部包層102，係以三甲基硼（（C2H5) 3Β)爲硼 源，以膦（ΡΗ3 )爲磷源，在95 0 °C加以堆積。構成下部 包層102之非摻雜且爲n形之BP層的載子濃度爲1 X 1 019cnT3，層厚爲 420nm。 η形下部包層 102上，由 η型氮化鎵·銦（ Gao.9oIno.ioN)所成之發光層103，在825 °C下形成。構成 阱層1 0 3的上記氮化鎵·銦層，是由不同銦組成所構成之 複數相（phase)而構成的多相構造而構成，其平均銦組成爲 0·10(=10%)。阱層103的層厚爲10nm。發光層103上， 藉由三甲基鎵（（CH3) 3Ga) /三甲基銦（（CH3) 3In) /H2反應系統常壓MOCVD法，於8 2 5 t下令摻矽（Si)n形 氮化鎵（GaN)層104接合而設置。GaN層104的層厚設爲 2 0nm。該GaN層104，係爲了在接合界面附近的發光層 1 〇3之內部領域中，形成傳導帶及價電子帶之褶曲帶 (band)構造而設置。 在η形GaN層104上，設置非摻雜之磷化硼（B P )所成之非晶質層1 05。磷化硼所成之非晶質層1 05，係 藉由（C2H5)3B/PH3/H2反應系統常壓MOCVD手段而設置 。非晶質層 105，係在 5 5 0 °C下，且 V/III比率（= PH3/(C2H5)3B)設爲10而令其氣相成長，因此在室溫下 (18) (18)200417062 ，會成爲電阻率爲1 〇 Ω · cm的高阻抗層。非摻雜之磷化 硼非晶質層1 〇 5的層厚爲1 5nm。接著，利用公知的選擇 性圖案化技術與電漿蝕刻技術，讓非晶質層1 0 5僅殘留設 置在台座電極1 〇7預定形成領域。非晶質層1 〇5的殘留領 域爲直徑1 2 0 // m的圓形領域。殘留領域以外的領域，非 晶質層105會被飩刻而除去，讓η形GaN層104的表面 露出。 接著，使用和上記相同之（（C2H5 ) 3B ) /PH3/H2反 應系統常壓MO CVD手段與氣相成長裝置，設置p形磷化 硼結晶層1 〇 6而接合至殘留的非晶質層1 〇 5及上記露出之 G a N層1 0 4的表面。P形磷化硼結晶層1 〇 6，是在局於非 晶質層105的高溫的l〇25t下設置。因爲氣相成長時的 V/III比率設爲1 3 00，故P形磷化硼結晶層106的載子濃 度爲2 X 1 019cm_3，層厚爲5 8 0nm。又，磷化硼結晶層106 在室溫下的禁止帶寬爲3· 2eV，因此磷化硼結晶層106是 被當成兼任讓發光透過至外部的窗層之P形上部包層而利 用。 構成P形上部包層的磷化硼結晶層1 〇 6的表面中央的 台座電極1 07設置領域’利用公知的光微影技術，選擇性 圖案化成圓形的平面形狀。同時，裁斷用溝孔設置領域 1 〇 8亦被選擇性圖案化成帶狀的平面形狀。然後，藉由利 用了氬（A〇/甲烷（CH4)/H2混合氣體的電漿蝕刻手法，限 定於上記施以圖案化的領域內，將非晶質層1 05的上部所 在之磷化硼結晶層1 〇6選擇性地蝕刻去除。藉此，於台座 -21 - (19) (19)200417062 電極1 0 7設置的直徑1 0 〇 μ m的圓形平面領域中，讓磷化 硼非晶質層1 〇 5的表面露出。又，於做爲裁斷線的寬度 5 Ο μ m之帶狀領域1 〇 8中，令磷化硼結晶層i 〇 5的表面同 時露出。裁斷線用途之帶狀領域1 〇 8，係平行設置在垂直 於基板101之Si單晶之劈開方向的<1 1〇>結晶方位上。 接者’僅在台座電極1 0 7設置領域使其開口般地，施 以選擇性圖案化的光阻材料做爲遮罩（mask)，將構成台座 電極107的底面部位l〇7a的金•鍺（Au95重量％，Ge5 重量％ )合金膜以一般的真空蒸著手法令其覆著。之後， 將遮罩材料從磷化硼結晶層1 06表面剝離去除，而一倂去 除附著在遮罩材表面的Au · Ge膜。僅在台座電極1〇7之 領域中殘存的，構成底面部位之 Au · Ge覆膜，膜厚爲 1 5 Onm。接著，將磷化硼結晶層1〇6表面以光阻材料覆蓋 後’藉由選擇性圖案化技術，僅在台座電極1 07之歐姆電 極1 0 7 b設置領域中，設置直徑爲1 5 0 // m的圓形開口部 。令此次開口部的中心，和上記底面部位1 0 7 a的平面形 狀一致。接著，以一般的真空蒸著手法，形成金·鈹（ Au9 9重量％，B e 1重量％ )合金膜，形成和p形磷化硼結 晶層106呈歐姆接觸之歐姆電極l〇7b。歐姆電極107b的 厚度爲800nm。用以構成台座電極107之歐姆電極107b 以外之遮罩材表面上所在之Au · Be合金膜，係和遮罩材 一倂剝離去除。藉此，平面積大於底面部位1 〇7a，且構 成接觸至p形磷化硼結晶層1 0 6表面的台座電極1 0 7之上 部部位的歐姆電極1 07b便被形成。 (20) (20)200417062 接著，在矽單晶基板101的背面，設置由鋁（Al) ·銻 (S b )合金所成之η形歐姆電極1 〇 9。藉由將磷化硼結晶層 1 0 6之中央用來設置台座電極1 〇 7的遮罩材料剝離，使之 前形成之裁斷用途之帶狀領域1 0 8的磷化硼非晶質層1 〇 5 露出。該裁斷用途之帶狀領域1 0 8，即，可令鑽石刀沿著 裁斷線而在磷化硼非晶質層1 05表面上直線行走。藉此， 可分割成邊長（=鄰接之裁斷線1 0 8之中心線間之距離） 爲3 00 // m的正方形之個別LED10。由於裁斷線108的寬 度爲刀刃寬度（約2 0 // m )的約2 · 5倍寬，因此個別分割 成的LED 1 0的側面都爲平坦。 以一般的斷面TEM (穿透式電子顯微鏡）技法觀察 的結果，來自磷化硼非晶質層1 05的限制視野電子線繞射 像爲暈（halo)狀。另一方面，磷化硼結晶層1〇6的電子線 繞射像，是表示在繞射環上發生有多於單晶層時之繞射點 (spot)的多晶層。 本發明中，由於是將大於底面部位1 0 7 a之平面積的 歐姆電極107b之頂部接觸至P形磷化硼結晶層106的表 面而設置，故即使在結線時，也未曾發現台座電極1 07之 剝離。在密著性佳的台座電極1 07及η形歐姆電極1 09之 間，確認了在順方向上流通20mA之元件驅動電流的發光 特性。從LED 10放射出中心波長爲44 Onm的藍色帶光。 發光光譜的半値寬爲2 8 0eV (電子伏特）。利用一般之積 分球測定之樹脂模封以前的晶片（chip)狀態下的亮度爲 7mcd。另外，因爲是將p形歐姆電極107b下方之底面部 (21) (21)200417062 位l〇7a接觸至高阻抗之磷化硼非晶質層105表面而設置 ’且可將元件驅動電流廣範圍地分配至發光層1 0 3之構成 ’因此，台座電極1 07之投影領域以外的發光領域也以大 略全面地均等強度發光。又，順方向電流爲2 0mA之際的 順方向電壓爲 3 · 5 V。逆方向電流爲1 0 // A之際的逆方向 電壓爲8.2V。 (第2實施例） 茲以構成具備了具有和做成層積構造之磷化硼系非晶 質層表面接觸之底面的台座電極之雙重異質接合（D Η ) 構造型發光二極體（L E D )時爲例，具體說明本發明所 論磷化硼系半導體發光元件。 圖2係本第2實施例所論之L E D 1 2的平面構造模 式圖。又，圖3係沿著圖2虛線Α-Α’之LED 12的剖面構 造模式圖。於圖2及圖3中，和圖1相同之構成要素則以 同一符號標示。 如上記第1實施例所記載般形成之η型GaN發光層 1 〇4上，首先，形成非摻雜且爲p形之磷化硼非晶質層 2〇1。p形磷化硼非晶質層201的載子濃度爲8 X 1 018cnT3 ’層厚爲12nm。p形磷化硼非晶質層201上，層積有非 摻雜且爲高阻抗的磷化硼非晶質層1 0 5。高阻抗之磷化硼 非晶質層105的室溫下阻抗率爲1〇 Ω · cm，層厚爲12nm 。將P形磷化硼非晶質層2 0 1及高阻抗之磷化硼非晶質層 1 〇5，利用公知的光微影技術，限定在台座電極丨07預定 -24- (22) (22)200417062 設置的領域內，令P形及高阻抗之非晶質層1 05、20 1殘 存下來。P形及高阻抗之非晶質層1 0 5、2 0 1 ’係中心爲同 一，直徑共同爲1 2 〇 μ Π1的平面視圓形之形狀而殘留。接 著，高阻抗的磷化硼非晶質層1 0 5上，堆積第1實施例所 記載之非摻雜之P形磷化硼結晶層1 〇6。 接著，利用電漿蝕刻技法，限定在台座電極1 0 7設置 領域及裁斷線1 〇 8設置領域內，將p形磷化硼結晶層1 0 6 選擇性地去除，讓高阻抗之磷化硼非晶質層1 05的表面露 出。去除了 P形磷化硼結晶層1 06的平面領域，是直徑爲 1 5 0 // m的圓形。該圓形領域之中心是和上記殘留之高阻 抗之磷化硼非晶質層1 05的圓形平面的中心一致。接著， 將接觸至高阻抗之磷化硼非晶質層1 05之表面的底面部位 l〇7a爲鉬（Mo)，其上部部位之歐姆電極107b爲金•鈹 (Au · Be )的台座電極107予以形成。鉬（Mo )覆膜厚 度爲10 nm，Au· Be覆膜的厚度爲700 nm。構成台座電極 107之頂部的Au· Be歐姆電極107b中，設有如圖3所示 之和其呈電性導通之圓環電極和線狀電極做爲附帶歐姆電 極 1 0 7 c 〇 如第1實施例所記載，沿著基板101之Si單晶之{0.-1 . 〇 }及{-1 · -1 · 0 }結晶方位上平行設置之裁斷線1 0 8，將個 別之LED12予以分離、裁斷。邊長3 5 0 //m之正方形 LED 12中’通過20mA之順方向電流之際的發光中心波長 ，係和第1實施例所記載之LED10略同爲440nm。利用 一般的積分球所測定之晶片狀態的亮度爲9mcd，是爲較 -25- (23) (23)200417062 第1實施例之LED10更高之發光強度的LED。又，根據 近視野發光像，確認到來自台座電極1 0 7以外之發光領域 是有均勻強度的發光。我們認爲，這是因爲將位於上部部 位之P形歐姆電極1 0 7 b之下方的底面部位1 0 7 a，設置在 P形及高阻抗之磷化硼非晶質層1 0 5、2 0 1所成之層疊構 造上，而可將元件驅動電流廣範圍地分配至發光層1 〇 3的 構成所發揮的效果。順方向電流爲2 OmA之際的順方向電 壓爲3.4V，逆方向電流爲10//A之際的逆方向電壓爲 8.3V。 【發明的效果】 右根據本發明’隔者憐化棚系半導體非晶質層而設置 磷化硼系半導體結晶層，且，令底面部接觸至該當磷化硼 系半導體非晶質層之表面，也接觸至磷化硼系半導體結晶 層的表面，而設置台座電極，因此，和磷化硼系半導體結 晶層的密著性佳，且元件驅動電流，例如，可完全分配至 不被台座電極遮光的發光領域中，因此，可以提供發光領 域爲廣發光強度之發光二極體等之磷化硼系半導體發光元 件。 【圖式簡單說明】 〔圖1〕第1實施例所記載之L E D之剖面構造模 式圖。 〔圖2〕第2實施例所記載之L E D之剖面構造模 -26- (24) 200417062 式圖。 〔圖3〕第2實施例所記載之L E D之剖面構造模 式圖。 【符號說明】 1 0、1 2 LED 11 層積構造體 10 1 矽單晶基板 1 02 η形磷化硼層 1 03 η形氮化鎵銦層發光層 1 04 η形氮化鎵層 105 非晶質層 106 磷化硼結晶層 1 07 台座電極 107a 台座電極底面部位 107b 構成台座電極上部部位之歐姆電極 107c 附帶歐姆電極 108 裁斷用途之溝（裁斷線） 109 η形歐姆電極 20 1 Ρ形磷化硼非晶質層On the substrate 101, a phosphorus-doped (P) n-shaped sand (S i) single crystal was used. On the surface of the substrate 101, an n-shaped boron phosphide (BP) formed by a lower cladding layer 102 is deposited by using atmospheric pressure (slightly atmospheric pressure) organic metal vapor phase epitaxy (MOVPE). The lower cladding layer 102 is stacked at 95 ° C with trimethylboron ((C2H5) 3B) as a boron source and phosphine (P3) as a phosphorus source. The carrier concentration of the non-doped and n-shaped BP layer constituting the lower cladding layer 102 is 1 × 1 019cnT3, and the layer thickness is 420 nm. On the n-type lower cladding layer 102, a light-emitting layer 103 made of n-type gallium nitride · indium (Gao.9oIno.ioN) is formed at 825 ° C. The above-mentioned gallium nitride · indium layer constituting the well layer 103 is a multi-phase structure composed of a plurality of phases composed of different indium compositions. The average indium composition is 0 · 10 (= 10%). . The layer thickness of the well layer 103 is 10 nm. On the light-emitting layer 103, a silicon (Si) n-doped silicon (Si) n-shape was ordered at 8 2 5 t by a trimethylgallium ((CH3) 3Ga) / trimethylindium ((CH3) 3In) / H2 reaction system atmospheric pressure MOCVD method. A gallium nitride (GaN) layer 104 is provided by bonding. The layer thickness of the GaN layer 104 is set to 20 nm. The GaN layer 104 is provided in order to form a band structure of a conduction band and a valence band in the internal area of the light emitting layer 103 near the bonding interface. On the n-shaped GaN layer 104, an amorphous layer 105 made of undoped boron phosphide (B P) is provided. The amorphous layer 105 formed by boron phosphide is provided by (C2H5) 3B / PH3 / H2 reaction system atmospheric pressure MOCVD method. The amorphous layer 105 is grown at 5 5 0 ° C and the V / III ratio (= PH3 / (C2H5) 3B) is set to 10 to grow the gas phase, so at room temperature (18) (18) 200417062, will become a high-resistance layer with a resistivity of 10 Ω · cm. The undoped boron phosphide amorphous layer 105 has a layer thickness of 15 nm. Next, using a known selective patterning technique and plasma etching technique, the amorphous layer 105 is only left in the predetermined formation region of the pedestal electrode 107. The residual area of the amorphous layer 105 is a circular area with a diameter of 1 2 0 // m. In areas other than the residual area, the amorphous layer 105 is etched and removed, leaving the surface of the n-shaped GaN layer 104 exposed. Next, using the ((C2H5) 3B) / PH3 / H2 reaction system atmospheric pressure MO CVD method and a vapor phase growth apparatus, a p-shaped boron phosphide crystal layer 106 was set and bonded to the remaining amorphous layer. 105 and the surface of the exposed G a N layer 104. The P-shaped boron phosphide crystal layer 106 is provided at a temperature of 1025 t which is localized to the high temperature of the amorphous layer 105. Since the V / III ratio during vapor phase growth is set to 1 3 00, the carrier concentration of the P-shaped boron phosphide crystal layer 106 is 2 × 1 019 cm_3, and the layer thickness is 5 8 0 nm. The forbidden bandwidth of the boron phosphide crystal layer 106 at room temperature is 3.2 eV. Therefore, the boron phosphide crystal layer 106 is used as a P-shaped upper cladding layer that also emits light to the outside window layer. The pedestal electrode 107 in the center of the surface of the boron phosphide crystal layer 106 that constitutes the P-shaped upper cladding layer is selectively patterned into a circular planar shape using a known photolithography technique. At the same time, the cutting groove setting area 108 is also selectively patterned into a strip-shaped planar shape. Then, by using a plasma etching method using an argon (A0 / methane (CH4) / H2 mixed gas), the boron phosphide where the upper part of the amorphous layer 105 is located is limited to the patterned area described above. The crystal layer 10 is selectively etched and removed. As a result, boron phosphide is allowed to be non-circular in a circular planar area of a diameter of 100 μm provided on the pedestal -21-(19) (19) 200417062 electrode 10. The surface of the crystalline layer 105 is exposed. Also, in the strip-shaped region 10 with a width of 50 μm as a cutting line, the surface of the boron phosphide crystal layer i 05 is simultaneously exposed. The strip-shaped area 108 is arranged in parallel with the < 1 1〇 > crystal orientation perpendicular to the cleavage direction of the Si single crystal of the substrate 101. The receiver is provided only in the area of the pedestal electrode 107 to make it open. Ground, a selectively patterned photoresist material is applied as a mask, and a gold-germanium (Au95% by weight, Ge5% by weight) alloy film constituting the bottom surface portion 107a of the pedestal electrode 107 is applied with a general vacuum. It was covered by steaming. After that, the masking material was peeled off from the surface of the boron phosphide crystal layer 106, and Except for the Au · Ge film attached to the surface of the masking material. The Au · Ge film constituting the bottom surface, which remains only in the area of the pedestal electrode 107, has a film thickness of 15 Onm. Next, boron phosphide is crystallized After the surface of the layer 106 is covered with a photoresist material, through the selective patterning technology, only a circular opening with a diameter of 1 5 0 // m is set in the setting field of the ohmic electrode 1 0 7 b of the pedestal electrode 107. Make the center of the opening this time consistent with the plane shape of the bottom surface part 107a of the above note. Next, gold and beryllium (Au9 9% by weight, Be 1 1% by weight) alloy was formed by a general vacuum evaporation method. Film to form an ohmic electrode 107b that is in ohmic contact with the p-shaped boron phosphide crystal layer 106. The thickness of the ohmic electrode 107b is 800 nm. The Au on the surface of the masking material other than the ohmic electrode 107b of the pedestal electrode 107 is formed. · Be alloy film, system and masking material are peeled and removed at once. Thereby, the flat area is larger than the bottom surface portion 107a, and constitutes the upper part of the pedestal electrode 107 which contacts the surface of the p-shaped boron phosphide crystal layer 106. The ohmic electrode 107b is formed at the part. (20) (20) 200417062 Next On the back of the silicon single crystal substrate 101, an η-shaped ohmic electrode 10 formed of an aluminum (Al) · antimony (S b) alloy is provided. The center of the boron phosphide crystal layer 106 is used for setting The mask material of the pedestal electrode 107 is peeled off, exposing the previously formed boron phosphide amorphous layer 10 of the strip-shaped area 108 of the cutting application. The strip-shaped area 108 of the cutting application, ie, The diamond knife can be made to travel straight on the surface of the boron phosphide amorphous layer 105 along the cutting line. With this, it can be divided into individual LEDs 10 with a side length (= the distance between the center lines of adjacent cutting lines 1 0 8) of 3 00 // m. Since the width of the cutting line 108 is approximately 2 · 5 times the width of the blade edge (approximately 2 // // m), the sides of the individually divided LEDs 10 are flat. As a result of observation with a general cross-sectional TEM (transmission electron microscope) technique, the diffraction-limited electron beam diffraction image from the boron phosphide amorphous layer 105 was halo-shaped. On the other hand, the electron beam diffraction image of the boron phosphide crystal layer 106 is a polycrystalline layer that indicates that there are more diffraction spots in the diffraction ring than in a single crystal layer. In the present invention, since the top of the ohmic electrode 107b, which is larger than the flat area of the bottom surface portion 107a, is provided in contact with the surface of the P-shaped boron phosphide crystal layer 106, the pedestal electrode 1 is not found even at the time of wiring. 07 peeling. The light-emitting characteristics of the device driving current of 20 mA flowing in the forward direction were confirmed between the pedestal electrode 107 and the n-shaped ohmic electrode 10 09 with good adhesion. From the LED 10, a blue band light having a center wavelength of 44 Onm is emitted. The half-width of the emission spectrum is 280 eV (electron volts). The brightness before chip molding of the resin measured with a general integrating sphere was 7mcd. In addition, because the bottom surface (21) (21) 200417062 bit 107a under the p-shaped ohmic electrode 107b is placed in contact with the surface of the high-impedance boron phosphide amorphous layer 105, and the device driving current can be wide-ranged. The structure assigned to the light-emitting layer 103 is, therefore, a light-emitting area other than the projection area of the pedestal electrode 107 also emits light at a substantially full and uniform intensity. When the forward current is 20 mA, the forward voltage is 3 · 5 V. When the reverse current is 1 0 // A, the reverse voltage is 8.2V. (Second embodiment) A double heterojunction (D)) structure type light emitting diode (LED) having a pedestal electrode having a bottom surface in contact with the surface of a boron phosphide amorphous layer having a laminated structure is constructed. ) As an example to specifically explain the boron phosphide-based semiconductor light-emitting device according to the present invention. Fig. 2 is a plan view of a planar structure of L E D 12 according to the second embodiment. FIG. 3 is a schematic view of the cross-sectional structure of the LED 12 along the dotted line A-A 'in FIG. 2. In Figs. 2 and 3, the same components as those in Fig. 1 are denoted by the same symbols. On the n-type GaN light-emitting layer 104 formed as described in the first embodiment above, first, an undoped and p-shaped boron phosphide amorphous layer 201 is formed. The carrier concentration of the p-shaped boron phosphide amorphous layer 201 is 8 X 1 018cnT3 'and the layer thickness is 12 nm. On the p-shaped boron phosphide amorphous layer 201, an undoped and high-impedance boron phosphide amorphous layer 105 is laminated. The high-resistance boron phosphide amorphous layer 105 has a resistivity of 10 Ω · cm at room temperature and a layer thickness of 12 nm. The P-shaped boron phosphide amorphous layer 201 and the high-resistance boron phosphide amorphous layer 105 are limited to the pedestal electrode using a well-known photolithography technique. 07 07-24 (22) ( 22) In the area where 200417062 is installed, the P-shaped and high-resistance amorphous layers 105 and 201 remain. The P-shaped and high-resistance amorphous layers 105, 2 01 'have the same center, and a plane having a diameter of 12 μm in common remains as a circular shape. Next, the undoped P-shaped boron phosphide crystal layer 106 described in the first embodiment is deposited on the high-resistance boron phosphide amorphous layer 105. Next, the plasma etching technique is used to selectively remove the p-shaped boron phosphide crystal layer 106 from the pedestal electrode 107 setting area and the cutting line 108 setting area, so that the high-impedance boron phosphide is removed. The surface of the amorphous layer 105 is exposed. The plane area of the P-shaped boron phosphide crystal layer 106 is removed, and the circle is a circle with a diameter of 15 0 // m. The center of the circular area coincides with the center of the circular plane of the high-resistance boron phosphide amorphous layer 105 which is mentioned above. Next, the bottom surface portion 107a of the surface contacting the high-impedance boron phosphide amorphous layer 105 is molybdenum (Mo), and the ohmic electrode 107b at the upper portion thereof is a pedestal electrode 107 of gold and beryllium (Au · Be). Be formed. The thickness of the molybdenum (Mo) coating is 10 nm, and the thickness of the Au · Be coating is 700 nm. The Au · Be ohmic electrode 107b constituting the top of the pedestal electrode 107 is provided with a ring electrode and a linear electrode which are electrically conductive as shown in FIG. 3 as an attached ohmic electrode 1 0 7 c 〇 implemented as the first As described in the example, the individual LEDs 12 are separated along the cutting lines 108 arranged parallel to the {0.-1. 〇} and {-1 · -1 · 0} crystal orientations of the Si single crystal of the substrate 101, Ruling. In the square LED 12 with a side length of 3 5 0 / m, the center wavelength of light emission when a current in the forward direction of 20 mA passes is approximately the same as that of the LED 10 described in the first embodiment at 440 nm. The brightness of the wafer state measured by a general integrating sphere is 9mcd, which is an LED having a higher luminous intensity than the LED10 of the first embodiment of -25- (23) (23) 200417062. Further, it was confirmed from the near-field emission image that light having a uniform intensity was emitted from a light-emitting area other than the pedestal electrode 107. We believe that this is because the bottom surface portion 1 0 a located below the P-shaped ohmic electrode 1 0 7 b at the upper portion is disposed on the P-shaped and high-resistance boron phosphide amorphous layer 1 5 and 2 In the multilayer structure formed by 0.1, the element driving current can be widely distributed to the light-emitting layer 1 0 3. When the forward current is 2 OmA, the forward voltage is 3.4V, and when the reverse current is 10 / A, the reverse voltage is 8.3V. [Effects of the Invention] According to the present invention, a boron phosphide-based semiconductor crystal layer is provided according to the present invention, and a boron phosphide-based semiconductor crystal layer is provided, and the bottom surface portion is brought into contact with the surface of the boron phosphide-based semiconductor amorphous layer. Since the base electrode is also in contact with the surface of the boron phosphide-based semiconductor crystal layer, it has good adhesion to the boron phosphide-based semiconductor crystal layer and the element drive current can be completely distributed to the non-base electrode, for example. In the light-emitting light-shielding field, a boron phosphide-based semiconductor light-emitting element such as a light-emitting diode having a wide light-emitting intensity can be provided. [Brief description of the drawings] [Fig. 1] A sectional structural model diagram of L E D described in the first embodiment. [Fig. 2] A sectional structural model of LD described in the second embodiment. [Fig. 3] A sectional structural model diagram of L E D described in the second embodiment. [Description of symbols] 10, 1 2 LED 11 laminated structure 10 1 silicon single crystal substrate 1 02 η-shaped boron phosphide layer 1 03 η-shaped gallium indium layer light-emitting layer 1 04 η-shaped gallium nitride layer 105 non Crystal layer 106 Boron phosphide crystal layer 1 07 Pedestal electrode 107a Pedestal electrode bottom surface part 107b Ohm electrode 107c forming the upper part of the base electrode 107c With ohmic electrode 108 Groove for cutting purpose (cut line) 109 η-shaped ohmic electrode 20 1 P-shaped phosphor Boron amorphous layer
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