JP3939251B2

JP3939251B2 - Boron phosphide-based semiconductor light-emitting device and method for manufacturing the same

Info

Publication number: JP3939251B2
Application number: JP2003000442A
Authority: JP
Inventors: 隆宇田川
Original assignee: Showa Denko KK
Current assignee: Showa Denko KK
Priority date: 2003-01-06
Filing date: 2003-01-06
Publication date: 2007-07-04
Anticipated expiration: 2023-01-06
Also published as: JP2004214455A; KR20050095603A; KR100638148B1; TWI231999B; CN1735975A; TW200417062A; CN100380692C

Description

【０００１】
【発明の属する技術分野】
本発明は、発光領域を拡張するに効果を奏する構成から成る台座電極を具備する高発光強度のリン化硼素系半導体発光素子、及びその製造方法に関する。
【０００２】
【従来の技術】
近年、III −Ｖ族化合物半導体の一種であるリン化硼素（化学式：ＢＰ）層を利用して、発光ダイオード（英略称：ＬＥＤ）或いはレーザダイオード（英略称：ＬＤ）等の発光素子を構成する技術が開示されている（例えば、特許文献１参照）。リン化硼素半導体では、電子に比較して、正孔（ｈｏｌｅ）の有効質量が小さいため、ｐ形の伝導層が得られ易いとされている（例えば、特許文献２参照）。最近では、ｐ形のリン化硼素層をオーミック電極を形成するための電極形成層（コンタクト層）として備えた発光素子が知れている（例えば、特許文献３参照）。
【０００３】
例えば、III 族窒化物半導体からなる発光層上に設けられたｐ形リン化硼素から成るコンタクト（ｃｏｎｔａｃｔ）層に接触させて設けられる従来のｐ形電極は、金（元素記号：Ａｕ）・亜鉛（元素記号：Ｚｎ）合金の単一層から構成されている（上記の特許文献２参照）。結線用途の台座（ｐａｄ）電極を兼ねる電極をリン化硼素層上に備えた従来のリン化硼素系半導体発光素子にあっては、ｐ形またはｎ形のリン化硼素層の表面に接触させて設けられるのが通例となっている（例えば、特許文献３参照）。
【０００４】
【特許文献１】
米国特許第６，０６９，０２１号公報明細書
【特許文献２】
特開平２−２８８３８８号公報
【特許文献３】
特開平１０−２４２５６７号公報
【０００５】
【発明が解決しようとする課題】
しかしながら、電極の底面部位を導電性のｎ形またはｐ形リン化硼素層の正しく表面に接触させて設ける従来の構成では、発光素子を駆動させるために供給する電流（素子駆動電流）が電極の底面部位より短絡的に下層へと流通してしまう問題を充分に回避出来ていない。このため、例えば、発光層の上方に設けた電極を設置するためのリン化硼素結晶層を介して外部へ発光を取り出す方式のＬＥＤにあっては、発光領域に万遍なく素子駆動電流を拡散できない不都合が発生する。従って、発光領域を拡張させて、リン化硼素系半導体発光素子の発光強度を増加させるに支障を来しているのが現状である。
【０００６】
本発明は、従来技術の欠点を克服すべく、素子駆動電流を発光領域の広範囲に拡散させるに効果を奏する台座電極の構成を提示すると共に、そのような台座電極を備えたリン化硼素系半導体発光素子、及びそのリン化硼素系半導体発光素子を製造するための製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
即ち、本発明は、上記目的を達成するために、下記を提供する。
（１）結晶基板上に発光層を含む半導体層が下地層として形成され、該半導体層上の第１の領域上にリン化硼素系半導体非晶質層が形成され、該リン化硼素系半導体非晶質層は高抵抗のリン化硼素系半導体非晶質層を含み、該高抵抗リン化硼素系半導体非晶質層上に結線用の台座電極が形成され、前記下地層としての前記半導体層上の前記第１の領域以外の第２の領域上に導電性リン化硼素系結晶層が任意に前記リン化硼素系半導体非晶質層上の一部まで延在して形成され、前記台座電極は底面より上部で前記リン化硼素系半導体結晶層と接していることを特徴とするリン化硼素系半導体発光素子。
（２）結晶基板上に発光層を含む半導体層が下地層として形成され、該半導体層上の第１の領域上にリン化硼素系半導体非晶質層が形成され、該リン化硼素系半導体非晶質層は前記下地層としての前記半導体層とは反対の伝導形のリン化硼素系半導体非晶質層を含み、該反対伝導形リン化硼素系半導体非晶質層上に結線用の台座電極が形成され、前記下地層としての前記半導体層上の前記第１の領域以外の第２の領域上に導電性リン化硼素系結晶層が任意に前記リン化硼素系半導体非晶質層上の一部まで延在して形成され、前記台座電極は底面より上部で前記リン化硼素系半導体結晶層と接していることを特徴とするリン化硼素系半導体発光素子。
（３）前記リン化硼素系半導体非晶質層が、前記下地層としての前記半導体層に接して形成された前記下地層としての前記半導体層とは反対の伝導形を有するリン化硼素系半導体非晶質層と、当該反対伝導形リン化硼素系半導体非晶質層上に形成された高抵抗のリン化硼素系半導体非晶質層との重層構造を有することを特徴とする上記（１）または（２）に記載のリン化硼素系半導体発光素子。
（４）前記リン化硼素系半導体非晶質層が、アンドープのリン化硼素系半導体から構成されていることを特徴とする上記（１）〜（３）の何れか１項に記載のリン化硼素系半導体発光素子。
（５）前記リン化硼素系半導体非晶質層の前記重層構造を構成する２層のリン化硼素系半導体非晶質層が、いずれもアンドープのリン化硼素系半導体から構成されていることを特徴とする上記（３）に記載のリン化硼素系半導体発光素子。
（６）前記台座電極の前記導電性リン化硼素系半導体結晶層と接する部分が、当該導電性リン化硼素結晶層とオーミック接触をなす材料から構成されていることを特徴とする上記（１）〜（５）の何れか１項に記載のリン化硼素系半導体発光素子。
（７）前記台座電極の前記導電性リン化硼素系半導体結晶層とオーミック接触をなす材料から構成された部分が、前記導電性リン化硼素系半導体結晶層上に延在していることを特徴とする上記（６）に記載のリン化硼素系半導体発光素子。
（８）前記台座電極の底面部位が前記リン化硼素系半導体非晶質層に対し非オーミック接触をなす材料から構成されていることを特徴とする上記（６）または（７）に記載のリン化硼素系半導体発光素子。
（９）前記台座電極が、前記リン化硼素系半導体非晶質層上にある底面部位と、該底面部位上に形成され当該底面部位の平面形状の中心と形状中心が一致しているオーミック電極部位とを有することを特徴とする上記（１）〜（８）の何れか１項に記載のリン化硼素系半導体発光素子。
（１０）前記台座電極の前記オーミック電極部位が、前記台座電極の前記底面部位の平面積を超える平面積を有することを特徴とする上記（９）に記載のリン化硼素系半導体発光素子。
（１１）前記台座電極の前記オーミック電極部位が、前記導電性リン化硼素系半導体結晶層表面上まで延在することを特徴とする上記（１０）に記載のリン化硼素系半導体発光素子。
（１２）結晶基板上に発光層を含む半導体層を気相成長法により形成し、該半導体層を下地層としかつ結晶基板の温度を２５０℃以上で１２００℃以下とした気相成長法で該下地層と反対導電形または高抵抗のリン化硼素系半導体非晶質層を堆積し、該リン化硼素系半導体非晶質層を選択的に除去して第１の領域に当該リン化硼素系半導体非晶質層を残しそれ以外の第２の領域では前記下地層としての前記半導体層を露出させ、当該露出した前記下地層としての前記半導体層上及び前記リン化硼素系半導体非晶質層上に結晶基板の温度を７５０℃以上１２００℃以下の温度とした気相成長法で導電性リン化硼素系半導体結晶層を堆積し、前記第１の領域の該導電性リン化硼素系半導体結晶層を選択的に除去して前記リン化硼素系半導体非晶質層を露出させ、当該露出したリン化硼素系半導体非晶質層上にかつ前記リン化硼素結晶層に接するように結線用の台座電極を形成し、その後、個別の発光素子に裁断することを特徴とするリン化硼素系半導体発光素子の製造方法。
（１３）台座電極を設ける前記第１の領域に在る導電性リン化硼素系半導体結晶層を除去すると同時に、個別の発光素子に裁断、分離するための帯状の切断線を設ける領域に在る導電性のリン化硼素系半導体結晶層を除去して、下方の前記下地層の表面を露出させることを特徴とする上記（１２）に記載のリン化硼素系半導体発光素子の製造方法。
【０００８】
【発明の実施の形態】
非晶質及び導電性の結晶層を成すリン化硼素系半導体とは、硼素（元素記号：Ｂ）とリン（元素記号：Ｐ）とを含む例えば、Ｂ_αＡｌ_βＧａ_γＩｎ_{１−α−β−γ}Ｐ_１−δＡｓ_δ（０＜α≦１、０≦β＜１、０≦γ＜１、０＜α＋β＋γ≦１、０≦δ＜１である。また、例えば、Ｂ_αＡｌ_βＧａ_γＩｎ_{１−α−β−γ}Ｐ_１−δＮ_δ（０＜α≦１、０≦β＜１、０≦γ＜１、０＜α＋β＋γ≦１、０≦δ＜１）である。より具体的には、単量体のリン化硼素（ＢＰ）、リン化硼素・ガリウム・インジウム（組成式Ｂ_αＧａ_γＩｎ_{１−α−γ}Ｐ：０＜α≦１、０≦γ＜１）、また、窒化リン化硼素（組成式ＢＰ_１−δＮ_δ：０≦δ＜１）や砒化リン化硼素（組成式Ｂ_αＰ_１−δＡｓ_δ）等の複数のＶ族元素を含む混晶である。特に、単量体のリン化硼素（ＢＰ）はリン化硼素系半導体混晶の基材である。室温での禁止帯幅を２．８〜３．４エレクトロンボルト（単位：ｅＶ）とする広禁止帯幅のＢＰを基材とすれば、禁止帯幅の広いリン化硼素系非晶質層または結晶層を形成することができる。禁止帯幅を３．０ｅＶとするリン化硼素系結晶層からは、禁止帯幅を例えば、２．７ｅＶとするIII 族窒化物半導体からなる発光層についての障壁層或いは発光を外部へ透過できる窓（ｗｉｎｄｏｗ）層を好適に形成できる。
【０００９】
リン化硼素系半導体非晶質層または結晶層は、例えば、ハロゲン（ｈａｌｏｇｅｎ）法（「日本結晶成長学会誌」、Ｖｏｌ．２４，Ｎｏ．２（１９９７）、１５０頁参照）、ハイドライド法（Ｊ．ＣｒｙｓｔａｌＧｒｏｗｔｈ，２４／２５（１９７４）、１９３〜１９６頁参照）、並びに分子線エピタキシャル法（Ｊ．ＳｏｌｉｄＳｔａｔｅＣｈｅｍ．，１３３（１９９７）、２６９〜２７２頁参照）等の気相成長手段に依り形成できる。また、有機金属化学的気相堆積（ＭＯＣＶＤ）法（Ｉｎｓｔ．Ｐｈｙｓ．Ｃｏｎｆ．Ｓｅｒ．，Ｎｏ．１２９（ＩＯＰＰｕｂｌｉｓｈｉｎｇＬｔｄ．（ＵＫ、１９９３）、１５７〜１６２頁参照）に依り気相成長できる。特に、ＭＯＣＶＤ法はトリエチル硼素（分子式：（Ｃ_２Ｈ_５）_３Ｂ）等の易分解性の物質を硼素源としているため、より低温で非晶質層を気相成長させるに有利な成長手段となる。これらの気相成長手段に依り、リン化硼素系半導体から成る非晶質層を形成する際には、１２００℃以下が適する。１２００℃を超える高温では、Ｂ_１３Ｐ_２等の硼素多量体の発生に因り、単量体のリン化硼素（ＢＰ）を基材とするリン化硼素系半導体層の成長が阻害される。一方で、非晶質のリン化硼素系半導体層を構成する元素（構成元素）の原料を気相成長領域で充分に熱分解でき、成膜を進行させることができる２５０℃以上とするのが適する。一般に、気相成長温度を１０００℃を超える高温とすると、ｐ形の伝導を呈する非晶質層または結晶層が得られ易くなる。ｎ形の伝導性の非晶質層または結晶層は、１０００℃未満の温度で形成され得る。
【００１０】
上記の手段を利用してリン化硼素系非晶質層を効率的に気相成長させるには、所謂、Ｖ／III 比率を０．２〜５０の範囲に設定するのが重要である。Ｖ／III 比率は、リン化硼素系半導体層の成長を実施する領域（成長領域）に供給される第III 族構成元素の合計の濃度に対する、第Ｖ族構成元素の合計の濃度の比率で表せる。このＶ／III 比率を０．２未満の極端に低比率とすると、硼素を富裕とする球体が多く発生し、平坦な表面の非晶質層が安定して得られず不都合となる。５０を超えるＶ／III 比率は、多結晶層の形成を招き、非晶質層を安定して得るに好適とはならない。本発明において結晶層とは、単結晶からなる層、非晶質と単結晶からなる多結晶層、配向性が相違する単結晶からなる多結晶層をいずれをもいう。リン化硼素系結晶層は、Ｖ／III 比率を１００以上、更に望ましくは５００以上で２０００以下として安定して形成できる。２０００を超える高いＶ／III 比率では、リン等の第Ｖ族元素を含む析出物が発生し、平坦な表面のリン化硼素系半導体結晶層を得るに難を来し、不都合である。非晶質、多結晶或いは単結晶は、一般のＸ線回折或いは電子線回折技法により判別できる。
【００１１】
気相成長された半導体層を下地層として設けるリン化硼素系半導体非晶質層は、抵抗率が大きい高抵抗の非晶質層、下地層を成す半導体層とは反対（逆）の伝導形を有する非晶質層、または、これらの層を重層させた重層構造から構成するのが好ましい。高抵抗の非晶質層の抵抗率は室温で望ましくは１０Ω・ｃｍ以上、より望ましくは１０^２Ω・ｃｍ以上である。下地層とは反対伝導形とは、例えば、下地層がｎ形層で或る場合、ｐ形であることを指す。非晶質層は、例えば、窒化ガリウム・インジウム（組成式Ｇａ_ＸＩｎ_１−ＸＮ：０≦Ｘ≦１）から成る発光層、或いは窒化アルミニウム・ガリウム（組成式Ａｌ_ＸＧａ_１−ＸＮ：０≦Ｘ≦１）から成るクラッド（ｃｌａｄ）障壁層を下地層として形成するのが好ましい。便宣上、高抵抗の非晶質層を「高抵抗非晶質層」と、また下地層とは反対伝導形の非晶質層を「反対導電形非晶質層」と呼称すると、肝要なのは、発光層或いは障壁層上に配置する台座電極の底面の下に、即ち、台座電極の射影領域に、高抵抗非晶質層または反対導電形非晶質層の何れかを設けることにある。台座電極の底面を高抵抗非晶質層上に設ける構成では、高抵抗非晶質層は素子駆動電流が台座電極の底面から下方の発光層へ短絡的に流通することを阻害する抵抗体として作用する。また、台座電極の底面を下地層とは反対伝導形の非晶質層上に設ける構成では、導電性非晶質層は下地層とｐｎ接合構造を形成し、素子駆動電流が台座電極の底面から下方の発光層へ短絡的に流通するのを阻害する作用を有する。高抵抗非晶質層または反対導電形非晶質層を形成する領域（第１の領域）は台座電極の底面を形成する領域（第３の領域）と同一である必要はなく、台座電極の底面（台座電極の射影領域）の少なくとも一部を含む領域であれば効果がある。しかし、素子駆動電流を通流させないｐｎ接合構造を構成する反対導電形非晶質層あるいは高抵抗非晶質層は、台座電極の射影領域及びその周囲に限定して設けることが好ましい。高抵抗非晶質層または反対導電形非晶質層は台座電極の射影領域に形成すれば、素子駆動電流が台座電極の底面から下方の発光層へ短絡的に流通することを防止して、台座電極で遮光される発光層の領域で発光が起きることを防止できる一方、素子駆動電流を下地層に充分に満遍なく通流させるためには、上記第１の領域以外の領域（第２の領域）に形成される導電性結晶層が下地半導体層と広い面積で接触していることが望ましいからである。台座電極の射影領域以外の領域（第２の領域）に広く高抵抗非晶質層または反対導電形非晶質層を形成すると、例えば発光層の全面に設けてしまうと、素子駆動電流を下地層に充分に万遍なく通流できす、高発光強度のＬＥＤを得るに不都合が生ずる。
【００１２】
更に、高抵抗非晶質層と、下地層とは反対伝導形の非晶質層とを重層させてリン化硼素系半導体非晶質層を構成することとすると、上記の素子駆動電流の短絡的な流通を防止する上でより効果的となる。下地層上に反対導電形非晶質層を設けてから、次にその上に高抵抗非晶質層を重層させるのが好適である。高抵抗非晶質層を介在させることに依り、ｐｎ接合をなす反対導電形非晶質層と下地層との接合部へ流入する素子駆動電流をそもそも減少させるに効果を上げられるからである。
高抵抗非晶質層の層厚としては、台座電極の底面部位を設ける領域にあって、下地層の表面を均等に被覆できる２ｎｍ以上であるのが適する。反対導電形非晶質層は、トンネル（ｔｕｎｎｅｌ）効果に依りキャリアの下地層へ通過させない５０ｎｍ以上とするのが望ましい。高抵抗非晶質層または反対導電形非晶質層の層厚を２００ｎｍを超えて大とすると、後述するオーミック電極とリン化硼素系半導体結晶層の表面との段差が増し、リン化硼素系半導体結晶層との密着性に優れる電極を形成するに支障を来すため好ましくはない。
【００１３】
底面を反対導電形或いは高抵抗の非晶質層に接触する台座電極を形成するには、先ず、下地層上に反対導電形或いは高抵抗非晶質層を成長させた後、台座電極を形成する領域を含む第１の領域に在る反対導電形或いは高抵抗非結晶層を選択的に除去してから、次に、導電性のリン硼素結晶層を成長させた後、台座電極を形成する領域に在る導電性のリン化硼素系結晶層を除去し、反対導電形或いは高抵抗の非晶質層の表面を露出させる。然る後、露出させた非晶質層の表面に、台座電極の底面を構成するのに好都合な材料を被着させれば形成できる。リン化硼素系非結晶層及びリン化硼素系結晶層は、例えば、公知の塩素（元素記号：Ｃｌ）系プラズマエッチング手法等によりエッチングすれば除去できる。反対導電形或いは高抵抗の非晶質層を台座電極下に選択的領域に残すには公知のフォトリソグラフィー技術を使用すればよい。台座電極を設ける平面領域に限り、台座電極の底面を設けるにあたっては、公知のフォトリソグラフィー技術を利用した選択パターニング技術を応用するのが好適である。台座電極の底面を反対導電形或いは高抵抗の何れの非晶質層の表面上に設けた場合でも、素子駆動電流が底面部位より、その射影領域に在る下方の発光層への短絡的な流通を阻害できる。ひいては、外部に対し発光が遮蔽される台座電極の射影領域以外の発光領域に素子駆動電流を優先して供給できることとなるため、例えば、高発光強度のＬＥＤを得るに貢献できる。
【００１４】
非晶質層を、不純物を故意に添加しない、所謂、アンドープ（ｕｎｄｏｐｅ）層から構成すると、下地層の発光層或いは障壁層を電気的或いは結晶的に変質するのを防止する上で効果がある。従来のマグネシウム（元素記号：Ｍｇ）を故意に添加（ｄｏｐｉｎｇ）した窒化ガリウム（ＧａＮ）層をｎ形発光層上に設けた積層構造に於いて、ｐ形不純物であるマグネシウム（Ｍｇ）の熱的拡散に因る発光層の高抵抗化、或いは量子井戸構造の発光層にあっては、障壁（ｂａｒｒｉｅｒ）層と井戸（ｗｅｌｌ）層とのヘテロ接合界面の乱雑化を回避できる。リン化硼素系半導体からなる非晶質層にあって、その伝導度は、それを気相成長させる温度（成長温度）及び上記のＶ／III 比率を調整すれば制御できる。成長温度が低温であり、且つ、Ｖ／III 比率を低く設定する程、より高抵抗の非晶質層を得ることができる。高温で、高いＶ／III 族比率で気相成長させるとより低抵抗の非晶質層を形成できる。リン化硼素系半導体非晶質層の導電性の尺度となる抵抗率は、通常のホール（Ｈａｌｌ）効果測定法により計測できる。
【００１５】
反対導電形または高抵抗の非晶質層に依る素子動作電流の短絡的流通の阻止機能に加えて、台座電極の底面部位をリン化硼素系半導体に対し、非オーミック接触性の材料から構成すると、尚更、素子駆動電流の短絡的流通を阻止するに効果を上げられる。非オーミック接触性とは、ショットキー（Ｓｃｈｏｔｔｋｙ）接合に見られる様に整流性を呈する接触である。本発明では、特に、接触抵抗を１×１０^−３Ω・ｃｍを超えて大とする接触も含めることとする。台座電極の底面部位の材料は、リン化硼素系半導体非晶質層の伝導形に依って異にする。高抵抗であれｐ形のリン化硼素系半導体非晶質層に対しては、例えば、金（元素記号：Ａｕ）・ゲルマニウム（元素記号：Ｇｅ）、金（Ａｕ）・錫（元素記号：Ｓｎ）、金（Ａｕ）・インジウム（元素記号：Ｉｎ）等の金合金から底面部位を構成する。ｎ形リン化硼素系半導体非晶質層については、金（Ａｕ）・亜鉛（元素記号：Ｚｎ）、金（Ａｕ）・ベリリウム（元素記号：Ｂｅ）等の金合金から底面部位を構成する。また、非晶質層の伝導形に拘わらず、遷移金属から整流性のある底面部位を構成できる。ショットキー整流性を呈する材料には、チタン（元素記号：Ｔｉ）、モリブデン（元素記号：Ｍｏ）、バナジウム（元素記号：Ｖ）、タンタル（元素記号：Ｔａ）、ハフニウム（元素記号：Ｈｆ）及びタンググテン（元素記号：Ｗ）等を例示できる。
【００１６】
リン化硼素系半導体非晶質層の表面に接触して設けた底面部位を構成する被膜上には、リン化硼素系半導体結晶層とオーミック接触を成す材料から構成した、オーミック電極を設ける。オーミック電極を構成する材料は、リン化硼素系半導体結晶層の伝導形に鑑みて選択する。ｐ形のリン化硼素系半導体結晶層については、金・亜鉛、金・ベリリウム等の金合金から構成できる。ｎ形のリン化硼素系半導体結晶層については、例えば、金・ゲルマニウム、金・錫、金・インジウム等の金合金から構成できる。台座電極の底面部位を設けるリン化硼素系半導体非晶質層と、オーミック電極を設けるリン化硼素系半導体結晶層とが、互いに反対の伝導層であれば、台座電極の底面部位と底面部位上のオーミック電極とは同一の材料から構成できる。例えば、ｐ形のリン化硼素系半導体非晶質層に底面部位を、ｎ形リン化硼素系結晶層にオーミック電極を接触させた台座電極を構成する場合に、底面部位とオーミック電極とを共に金・ゲルマニウム合金から構成する例が挙げられる。ニオブ（元素記号：Ｎｂ）、クロム（元素記号：Ｃｒ）及び上記の遷移金属からショットキー整流性とオーミック電極の両方を構成することは好適ではない。
【００１７】
平面積が台座電極の底面部位の底面積を超えるものとし、且つ底面積に比較して超過する平面積を与える部位をリン化硼素系半導体結晶層の表面まで延在させてそれに接する様に配置すると、リン化硼素系半導体結晶層の表面に密着するオーミック電極を形成できる。リン化硼素系半導体非晶質層に接して設けられた底面を含む底面部位を形成した後、底面部位に接し尚且リン化硼素系半導体結晶層にも接する様にオーミック電極を構成する材料を被着させてから、例えば円形の底面であればより直径の大きな円形の電極となる様に、公知のフォトリソグラフィー技術を利用してオーミック電極材料を加工すれば形成できる。この場合、底面部位の円形領域より外縁に在るオーミック電極の部位をリン化硼素系半導体結晶層の表面と密着させる。底面部位の平面形状と、オーミック電極の平面形状とを相似形とする必要は必ずしも無い。例えば、底面部位の平面形状を円形とし、オーミック電極の平面形状を正方形とする例が上げられる。しかし、底面部位の平面形状の中心とオーミック電極の平面形状の中心とは通常は一致させるのが、リン化硼素系半導体結晶層と平面的に等方的な強度で密着する台座電極を形成する上で特に、望ましい。
【００１８】
リン化硼素系半導体結晶層に密着する様に設けたオーミック電極と電気的に導通させて、更に、リン化硼素系半導体結晶層の表面に延在させてオーミック電極を配置すると、台座電極の射影領域以外の発光領域に素子駆動電流を分配できるので好ましい。即ち、リン化硼素系半導体結晶層を透過させて発光を外部へ取り出す方式のＬＥＤにあって、台座電極に依って遮光されない、外部に発光を取り出すに好都合となる発光領域に、素子駆動電流を平面的に拡散できる。この様に延在させたオーミック電極は、台座電極の底面に依ってその射影領域に在る発光層への短絡的な流通を阻害された素子駆動電流を、発光領域に広範囲に拡散させる作用を有し、高発光強度のＬＥＤを製造するに貢献できる。リン化硼素系半導体結晶層の表面に延在させて設けるオーミック電極は、台座電極を成すオーミック電極とは異なる材料からも構成できる。例えば、台座電極のオーミック電極を金・ゲルマニウム合金から構成し、延在させるオーミック電極を金・錫合金から構成する例がある。延在させるオーミック電極は、リン化硼素系半導体結晶層との密着性の良さからして、第III 族元素であるガリウム（元素記号：Ｇａ）やインジウム（元素記号：Ｉｎ）等よりも、第IV族元素の錫（Ｓｎ）、ゲルマニウム（Ｇｅ）を含む合金からより好適に構成できる。台座電極と延在させるオーミック電極とを共に同一の材料から構成すると、それらを同時に構成でき、工程的に簡便にリン化硼素系半導体発光素子を得る寄与できる。
【００１９】
延在させるオーミック電極は、台座電極の射影領域以外の発光領域に万遍なく、均等に素子駆動電流を分配できる様に配置するのが望ましい。即ち、リン化硼素系半導体結晶層の表面、ひいては発光層の表面に於いて、均等な電位分布が帰結される様に配置するのが好適である。延在させるオーミック電極は、台座電極と電気的導通させた帯状、円環状、或いは、枠状などの電極から構成できる。また、これらの帯状電極や枠状電極などを組合わせかつ互いに導通させて構成することができる。帯状、円環状或いは枠状などの電極を構成する線状の電極は、通流する素子駆動電流が増加した場合に於いても断線することの無い様に、通常は１０μｍ以上、更に望ましくは２０μｍ以上の線幅を有するのが望ましい。公知のフォトリソグラフィー技術とパターニング技術と選択エッチング技術を利用すれば、所望の形状及び線幅の線状電極を、リン化硼素系半導体結晶層の表面上に敷設できる。
【００２０】
リン化硼素系半導体発光素子は、台座電極或いは台座電極に付属させてオーミック電極を形成した後、個別の素子に裁断して製造する。個別の素子への切断は、通常、基板を成す結晶の劈開方向に沿って設けられる、一般に、裁断線、スクライブライン或いはダイシングラインと呼称される直線状の溝を利用して実施される。本発明では、上記の如くリン化硼素系半導体非晶質層に接して台座電極の底面部位を設けるために、底面部位を設ける領域に在るリン化硼素系半導体結晶層を除去する必要がある。これと同時に個別の素子に裁断線とする溝を形成するとリン化硼素系半導体発光素子を得るにあたっての工程を簡略とすることができる。従って、本発明では、台座電極の底面部位を形成する領域で非晶質層の表面を露出させると同時に、裁断線を設ける領域に於いて前記下地層の表面を露出させて裁断用途の溝を形成する。この裁断用途の溝は、例えば、立方晶閃亜鉛鉱型の結晶を基板としている場合は、劈開方向である互いに直交する＜１１０＞結晶方位に設けるのが得策である。裁断用途の溝（裁断線）の幅は、裁断用器具の刃先の接触に因り、溝の側面を成すリン化硼素系半導体結晶層を大きく損傷させることの無い様に、充分な幅とするのが好適である。一般には、４０μｍ以上で７０μｍ以下とするのが好適である。７０μｍを超える幅とすると、却って、溝の幅が不必要に広くなるため、裁断器具の刃先の走行の範囲に猶予ができる。このため、刃先の”ぶれ”のため直線的に走行しなくなるため、裁断後の断面を平滑とする個別素子が得られ難くなる。
【００２１】
【作用】
台座電極の底面の下に配置した高抵抗または下地層と反対導電形のリン化硼素系半導体非晶質層は、その上に設ける台座電極の底面を通じて供給される素子駆動電流が、台座電極の下方に位置する発光層へ短絡的に流入するのを防止する作用を有する。
【００２２】
リン化硼素系半導体に対して非オーミック接触を呈する材料から構成した台座電極の底面は、台座電極を介して供給される素子駆動電流が、下のリン化硼素系半導体非晶質層に短絡的に流通するのを回避する作用を有する。
【００２３】
台座電極の一部を成す底面部位に接して設けられ、底面部位の底面積よりも大きな平面積を有し、リン化硼素系半導体結晶層の表面に接して設けるオーミック電極は、リン化硼素系半導体層との密着性に優れる台座電極をもたらす作用を有する。
【００２４】
台座電極の一部を成すオーミック電極に電気的に導通させて、且つリン化硼素系半導体結晶層の表面に延在させて設けたオーミック電極は、素子駆動電流を発光領域に広範囲に分配する作用を有する。
【００２５】
（第１実施例）
高抵抗のリン化硼素非晶質層の表面と接した底面を有する台座電極を備えた発光ダイオード（ＬＥＤ）を構成する場合を例にして本発明に係わるリン化硼素系半導体発光素子を具体的に説明する。図１にダブルヘテロ（ＤＨ）接合構造のＬＥＤ１０を作製するために使用した積層構造体１１の断面構造を模式的に示す。
【００２６】
基板１０１には、リン（Ｐ）ドープｎ形珪素（Ｓｉ）単結晶を使用した。基板１０１の表面上には、常圧（略大気圧）有機金属気相エピタキシー（ＭＯＶＰＥ）手段を利用して、ｎ形のリン化硼素（ＢＰ）からなる下部クラッド層１０２を堆積させた。下部クラッド層１０２は、トリエチル硼素（分子式：（Ｃ_２Ｈ_５）_３Ｂ）を硼素（Ｂ）源とし、また、ホスフィン（分子式：ＰＨ_３）をリン源として、９５０℃で堆積した。下部クラッド層１０２をなすアンドープでｎ形のＢＰ層のキャリア濃度は１×１０^１９ｃｍ^−３であり、層厚は４２０ｎｍとした。
【００２７】
ｎ形下部クラッド層１０２上には、常圧ＭＯＣＶＤ法に依り気相成長させたｎ形窒化ガリウム・インジウム（Ｇａ_０．９０Ｉｎ_０．１０Ｎ）から成る発光層１０３を、８２５℃で形成した。井戸層１０３を構成する上記の窒化ガリウム・インジウム層は、インジウム組成を相違する複数の相（ｐｈａｓｅ）から構成される多相構造から構成し、その平均的なインジウム組成は０．１０（＝１０％）であった。井戸層１０３の層厚は１０ｎｍとした。発光層１０３上には、トリメチルガリウム（分子式：（ＣＨ_３）_３Ｇａ）／ＮＨ_３／Ｈ_２反応系常圧ＭＯＣＶＤ手段により、８２５℃で珪素（Ｓｉ）ドープｎ形窒化ガリウム（ＧａＮ）層１０４を接合させて設けた。ＧａＮ層１０４の層厚は、２０ｎｍとした。このｎ形ＧａＮ層１０４は、接合界面近傍の発光層１０３の内部領域に、伝導帯及び価電子帯の曲折したバンド（ｂａｎｄ）構造を形成するために設けた。
【００２８】
ｎ形ＧａＮ層１０４上には、アンドープのリン化硼素（ＢＰ）からなる非晶質層１０５を設けた。リン化硼素からなる非晶質層１０５は、（Ｃ_２Ｈ_５）_３Ｂ／ＰＨ_３／Ｈ_２反応系常圧ＭＯＣＶＤ手段に依り設けた。非晶質層１０５は、５５０℃で、且つＶ／III 比率（＝ＰＨ_３／Ｃ_２Ｈ_５）_３Ｂ）を１０として気相成長させたため、室温では、抵抗率を１０Ω・ｃｍとする高抵抗層となった。アンドープのリン化硼素非晶質層１０５の層厚は１５ｎｍとした。次に、公知の選択パターニング技術とプラズマエッチング技術とを利用して、台座電極１０７を形成する予定の領域に限り、非晶質層１０５を残置させた。非晶質層１０５を残置させた領域は直径１２０μｍの円形領域とした。残置させたその外の領域では、非晶質層１０５をエッチングにより除去して、ｎ形ＧａＮ層１０４の表面を露出させた。
【００２９】
次に、上記と同一の（Ｃ_２Ｈ_５）_３Ｂ／ＰＨ_２／Ｈ_２反応系常圧ＭＯＣＶＤ手段と気相成長装置を使用し、残置させた非晶質層１０５及び上記の露出させたｎ形ＧａＮ層１０４の表面に接合させて、ｐ形のリン化硼素結晶層１０６を設けた。アンドープのリン化硼素結晶層１０６は、非晶質層１０５よりも高温の１０２５℃で設けた。気相成長時のＶ／III 比率は１３００としたため、リン化硼素結晶層１０６のキャリア濃度は２×１０^１９ｃｍ^−３となり、層厚は５８０ｎｍとした。また、リン化硼素結晶層１０６の室温での禁止帯幅は３．２ｅＶであったため、リン化硼素結晶層１０６は、発光を外部へ透過するための窓層を兼用するｐ形の上部クラッド層として利用した。
【００３０】
ｐ形上部クラッド層をなすリン化硼素結晶層１０６の表面の中央の台座電極１０７を設ける領域を、公知のフォトリソグラフィー技術を利用して、円形の平面形状に選択的にパターニングを施した。同時に、裁断用の溝孔を設ける領域１０８にも帯状の平面形状に選択的パターニングを施した。然る後、アルゴン（Ａｒ）／メタン（分子式：ＣＨ₄）／Ｈ₂混合ガスを利用したプラズマエッチング手法に依り、上記のパターニングを施した領域に限定して、非晶質層１０５の上部に在るリン化硼素結晶層１０６を選択的にエッチングで除去した。これより、台座電極１０７を設ける直径１００μｍの円形の平面領域に於いて、リン化硼素非晶質層１０５の表面を露出させた。また、裁断線とする幅を５０μｍとする帯状の領域１０８に於いて、ｎ形ＧａＮ層１０４の表面を同時に露出させておいた。裁断線用途の帯状の領域１０８は、基板１０１のＳｉ単結晶の劈開方向である互いに直交する＜１１０＞結晶方位に平行に設けた。
【００３１】
次に、台座電極１０７を設ける領域に限り開口する様に選択パターニングを施したフォトレシスト材料をマスク（ｍａｓｋ：被覆）材として、台座電極１０７の底面部位１０７ａをなす金・ゲルマニウム（Ａｕ９５重量％・Ｇｅ５重量％）合金膜を一般の真空蒸着手法に依り被着させた。その後、マスク材料をリン化硼素結晶層１０６の表面から剥離して取り除くに併せて、マスク材の表面に被着させたＡｕ・Ｇｅ被膜を除去した。台座電極１０７の領域にのみ残存させた、底面部位をなすＡｕ・Ｇｅ被膜の層厚は１５０ｎｍとした。次に、リン化硼素結晶層１０６の表面をフォトレジスト材料で被覆した後、選択パターニング技術に依り、台座電極１０７のオーミック電極１０７ｂを設ける領域に限り、直径を１５０μｍとする円形の開口部を設けた。今回の開口部の中心と、上記の底面部位１０７ａの平面形状とは一致させた。次に、金・ベリリウム（Ａｕ９９重量％・Ｂｅ１重量％）合金膜を一般の真空蒸着法に依り形成して、ｐ形リン化硼素結晶層１０６とオーミック接触をなすオーミック電極１０７ｂを形成した。オーミック電極１０７ｂの厚さは８００ｎｍとした。台座電極１０７を構成するためのオーミック電極１０７ｂ以外のマスク材表面上に在るＡｕ・Ｂｅ合金膜はマスク材を剥離すると共に除去した。これより、底面部位１０７ａに比べて平面積を大とし、ｐ形リン化硼素結晶層１０６の表面に接する台座電極１０７の上部部位をなすオーミック電極１０７ｂを形成した。
【００３２】
次に、珪素単結晶基板１０１の裏面に、アルミニウム（Ａｌ）・アンチモン（Ｓｂ）合金からなるｎ形オーミック電極１０９を設けた。リン化硼素結晶層１０６の中央に台座電極１０７を設けるためのマスク材料を剥離したことにより、前もって形成しておいた裁断用途の帯状の領域１０８の、ｎ形ＧａＮ層１０４を露呈させた。この裁断用途の帯状の領域１０８、即ち、裁断線に沿って、ダイヤモンドブレードをｎ形ＧａＮ層１０４の表面に直線的に走行させた。これより、一辺の長さ（＝隣接する裁断線１０８の中心線間の距離）を３００μｍとする正方形の個別のＬＥＤ１０に分割した。裁断線１０８の幅をブレードの幅（約２０μｍ）に比較して、約２．５倍の広さとしたため、個別に分割されたＬＥＤ１０の側面は平坦であった。
【００３３】
一般的な断面ＴＥＭ技法に依る観察では、リン化硼素非晶質層１０５からの制限視野電子線回折像はハローなものとなった。一方、リン化硼素結晶層１０６の電子線回折像は、回折環上に単結晶層の場合よりも多くの多点の回折点（ｓｐｏｔ）を発生させる多結晶層を示すものとなった。
【００３４】
本発明では、底面部位１０７ａより大きな平面積のオーミック電極１０７ｂの天井部をｐ形リン化硼素結晶層１０６の表面に接触させて設けたため、結線時に於いても、台座電極１０７の剥離は認められなかった。密着性に優れた台座電極１０７及びｎ形のオーミック電極１０９の間に、順方向に２０ｍＡの素子駆動電流を流通し発光特性を確認した。ＬＥＤ１０からは中心の波長を４４０ｎｍとする青色帯光が放射された。発光スペクトルの半値幅は２８０ミリエレクトロンボルト（単位：ｍｅＶ）であった。一般的な積分球を利用して測定される樹脂モールド以前のチップ（ｃｈｉｐ）状態での輝度は７ミリカンデラ（ｍｃｄ）であった。また、ｐ形オーミック電極１０７ｂの下方の底面部位１０７ａを高抵抗のリン化硼素非晶質層１０５の表面に接触させて設け、素子駆動電流を発光層１０３に広範囲に分配できる構成としたため、台座電極１０７の射影領域以外の発光領域の略全面から均等な強度の発光がもたらされた。また、順方向電流を２０ｍＡとした際の順方向電圧は３．５Ｖであった。逆方向電流を１０μＡとした際の逆方向電圧は８．２Ｖであった。
【００３５】
（第２実施例）
重層構造としたリン化硼素非晶質層の表面と接した底面を有する台座電極を備えた２重異種接合（ＤＨ）構造型の発光ダイオード（ＬＥＤ）を構成する場合を例にして本発明に係わるリン化硼素系半導体発光素子を具体的に説明する。
【００３６】
図２に、本第２実施例に係わるＬＥＤ１２の平面構造を模式的に示す。また、図３には、図２に示した破線Ａ−Ａ’に沿ったＬＥＤ１２の断面構造を模式的に示す。図２及び図３に於いて、図１に掲示したと同様の構成要素については同一の符号を付して示すこととする。
【００３７】
上記の第１実施例に記載の如く形成されたｎ形ＧａＮ発光層１０４上に、先ず、アンドープでｐ形のリン化硼素非晶質層２０１を形成した。ｐ形リン化硼素非晶質層２０１のキャリア濃度は８×１０^１８ｃｍ^−３とし、層厚は１２ｎｍとした。ｐ形リン化硼素非晶質層２０１上には、アンドープで高抵抗のリン化硼素非晶質層１０５を積層させた。高抵抗のリン化硼素非晶質層１０５の室温での抵抗率は１０Ω・ｃｍとし、層厚は１２ｎｍとした。ｐ形リン化硼素非晶質層２０１及び高抵抗のリン化硼素非晶質層１０５を、公知のフォトリソグラフィー技術を利用して、台座電極１０７を設ける予定の領域に限定して、ｐ形及び高抵抗の非晶質層１０５，２０１を残存させた。ｐ形及び高抵抗の非晶質層１０５，２０１は、中心を同一とした、共に直径を１２０μｍとする平面視円形の形状に残置させた。次に、高抵抗のリン化硼素非晶質層１０５上に、第１実施例に記載のアンドープのｐ形リン化硼素結晶層１０６を堆積させた。
【００３８】
次に、プラズマエッチング技法を利用して、台座電極１０７を設ける領域及び裁断線１０８を設ける領域に限定して、ｐ形リン化硼素結晶層１０６を選択的に除去して、高抵抗のリン化硼素非晶質層１０５の表面を露出させた。ｐ形リン化硼素結晶層１０６を除去した平面領域は、直径１５０μｍの円形とした。この円形領域の中心と上記の残置させた高抵抗のリン化硼素非晶質層１０５の円形平面の中心と一致させた。次に、高抵抗のリン化硼素非晶質層１０５の表面に接する底面部位１０７ａをモリブデン（Ｍｏ）とし、その上部部位のオーミック電極１０７ｂを金・ベリリウム（Ａｕ・Ｂｅ）とする台座電極１０７を形成した。モリブデン（Ｍｏ）被膜の厚さは１０ｎｍとし、Ａｕ・Ｂｅ被膜の厚さは７００ｎｍとした。台座電極１０７の天井部をなすＡｕ・Ｂｅオーミック電極１０７ｂには、それと電気的に導通させて図３に示す如くの円環電極と線状電極とを付帯オーミック電極１０７ｃとして設けた。
【００３９】
第１実施例に記載の如く、基板１０１のＳｉ単結晶の｛１．−１．０｝及び｛−１．−１．０｝結晶方位に平行に設けた裁断線１０８に沿って、個別のＬＥＤ１２に分離、裁断した。一辺を３５０μｍとする正方形のＬＥＤ１２に、２０ｍＡの順方向電流を通流した際の発光中心波長は、第１実施例に記載のＬＥＤ１０と略同一の４４０ｎｍであった。一般の積分球を利用して測定されるチップ状態での輝度は９ｍｃｄであり、第１実施例のＬＥＤ１０に比較してより高い発光強度のＬＥＤがもたらされた。また、近視野発光像に依れば、台座電極１０７以外の発光領域からの均一な強度の発光がもたらされているのが確認された。これは、上部部位であるｐ形オーミック電極１０７ｂの下方の底面部位１０７ａを、ｐ形及び高抵抗のリン化硼素非晶質層１０５，２０１から成る重層構造上に設け、素子駆動電流を発光層１０３に広範囲に分配できる構成とした効果であると認められた。順方向電流を２０ｍＡとした際の順方向電圧は３．４Ｖであり、逆方向電流を１０μＡとした際の逆方向電圧は８．３Ｖとなった。
【００４０】
【発明の効果】
本発明に依れば、リン化硼素系半導体非晶質層を介してリン化硼素系半導体結晶層を設け、且つ、当該リン化硼素系半導体非晶質層の表面に底面部を接触し、リン化硼素系半導体結晶層の表面にも接触する様に台座電極を設けることにしたので、リン化硼素系半導体結晶層との密着性に優れ、且つ、素子駆動電流を例えば、台座電極に遮光されない発光領域に万遍なく分配でき、従って、発光領域の広い高い発光強度の発光ダイオード等のリン化硼素系半導体発光素子を提供できる。
【図面の簡単な説明】
【図１】第１実施例に記載のＬＥＤの断面構造を示す模式図である。
【図２】第２実施例に記載のＬＥＤの平面構造を示す模式図である。
【図３】第２実施例に記載のＬＥＤの断面構造を示す模式図である。
【符号の説明】
１０、１２…ＬＥＤ
１１…積層構造体
１０１…珪素単結晶基板
１０２…ｎ形リン化硼素層
１０３…ｎ形窒化ガリウム・インジウム発光層
１０４…ｎ形窒化ガリウム層
１０５…高抵抗のリン化硼素非晶質層
１０６…ｐ形リン化硼素結晶層
１０７…台座電極
１０７ａ…台座電極の底面部位
１０７ｂ…台座電極の上部部位をなすオーミック電極
１０７ｃ…付帯オーミック電極
１０８…裁断用途の溝（裁断線）
１０９…ｎ形オーミック電極
２０１…ｐ形リン化硼素非晶質層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a boron phosphide-based semiconductor light-emitting device having a high light emission intensity, and a method for manufacturing the same, including a pedestal electrode having a structure effective for expanding a light-emitting region.
[0002]
[Prior art]
In recent years, a light-emitting element such as a light-emitting diode (abbreviation: LED) or a laser diode (abbreviation: LD) is formed using a boron phosphide (chemical formula: BP) layer which is a type of III-V group compound semiconductor. A technique is disclosed (for example, see Patent Document 1). In boron phosphide semiconductors, it is said that a p-type conductive layer is easily obtained because the effective mass of holes is smaller than electrons (see, for example, Patent Document 2). Recently, a light-emitting element including a p-type boron phosphide layer as an electrode formation layer (contact layer) for forming an ohmic electrode is known (see, for example, Patent Document 3).
[0003]
For example, a conventional p-type electrode provided in contact with a contact layer made of p-type boron phosphide provided on a light-emitting layer made of a group III nitride semiconductor is gold (element symbol: Au) / zinc (Element symbol: Zn) It is comprised from the single layer of an alloy (refer said patent document 2). In a conventional boron phosphide-based semiconductor light-emitting device provided with an electrode that also serves as a pedestal (pad) electrode for wire connection on a boron phosphide layer, it is brought into contact with the surface of the p-type or n-type boron phosphide layer. It is customarily provided (see, for example, Patent Document 3).
[0004]
[Patent Document 1]
US Pat. No. 6,069,021
[Patent Document 2]
JP-A-2-288388
[Patent Document 3]
Japanese Patent Laid-Open No. 10-242567
[0005]
[Problems to be solved by the invention]
However, in the conventional configuration in which the bottom surface portion of the electrode is provided in contact with the correct surface of the conductive n-type or p-type boron phosphide layer, the current supplied to drive the light emitting element (element driving current) is The problem of short-circuiting from the bottom part to the lower layer cannot be sufficiently avoided. For this reason, for example, in an LED that takes out light emission through a boron phosphide crystal layer for installing an electrode provided above the light emitting layer, the device driving current is diffused uniformly in the light emitting region. Inconvenience that can not be generated. Accordingly, the current situation is that the emission region is expanded to increase the emission intensity of the boron phosphide-based semiconductor light-emitting device.
[0006]
In order to overcome the disadvantages of the prior art, the present invention presents a structure of a pedestal electrode that is effective in diffusing element driving current over a wide area of a light emitting region, and a boron phosphide-based semiconductor having such a pedestal electrode. It is an object of the present invention to provide a light emitting device and a manufacturing method for manufacturing the boron phosphide-based semiconductor light emitting device.
[0007]
[Means for Solving the Problems]
That is, this invention provides the following in order to achieve the said objective.
(1) A semiconductor layer including a light-emitting layer is formed as a base layer on a crystal substrate, a boron phosphide-based semiconductor amorphous layer is formed on a first region on the semiconductor layer, and the boron phosphide-based semiconductor The amorphous layer includes a high-resistance boron phosphide-based semiconductor amorphous layer, a pedestal electrode for connection is formed on the high-resistance boron phosphide-based semiconductor amorphous layer, and the semiconductor as the base layer A conductive boron phosphide-based crystal layer arbitrarily extending to a part of the boron phosphide-based semiconductor amorphous layer on a second region other than the first region on the layer; 2. A boron phosphide-based semiconductor light-emitting element, wherein the pedestal electrode is in contact with the boron phosphide-based semiconductor crystal layer above the bottom surface.
(2) A semiconductor layer including a light emitting layer is formed as a base layer on a crystal substrate, a boron phosphide-based semiconductor amorphous layer is formed on a first region on the semiconductor layer, and the boron phosphide-based semiconductor The amorphous layer includes a boron phosphide-based semiconductor amorphous layer having a conductivity type opposite to that of the semiconductor layer as the underlayer, and is connected to the opposite conductivity-type boron phosphide-based semiconductor amorphous layer. A base electrode is formed, and a conductive boron phosphide-based crystal layer is optionally formed on the second region other than the first region on the semiconductor layer as the base layer. A boron phosphide-based semiconductor light-emitting element formed to extend up to a part above and in contact with the boron phosphide-based semiconductor crystal layer above the bottom surface.
(3) The boron phosphide-based semiconductor in which the boron phosphide-based semiconductor amorphous layer has a conductivity type opposite to that of the semiconductor layer as the underlayer formed in contact with the semiconductor layer as the underlayer. The above (1), characterized in that it has a multilayer structure of an amorphous layer and a high-resistance boron phosphide-based semiconductor amorphous layer formed on the opposite conductivity type boron phosphide-based semiconductor amorphous layer. Or a boron phosphide-based semiconductor light-emitting device according to (2).
(4) The phosphide described in any one of (1) to (3) above, wherein the boron phosphide-based semiconductor amorphous layer is composed of an undoped boron phosphide-based semiconductor. Boron semiconductor light emitting device.
(5) The two boron phosphide-based semiconductor amorphous layers constituting the multilayer structure of the boron phosphide-based semiconductor amorphous layer are both composed of an undoped boron phosphide-based semiconductor. The boron phosphide-based semiconductor light-emitting device described in (3) above.
(6) The part of the pedestal electrode in contact with the conductive boron phosphide-based semiconductor crystal layer is made of a material that makes ohmic contact with the conductive boron phosphide crystal layer. The boron phosphide-based semiconductor light-emitting device according to any one of to (5).
(7) The portion of the base electrode made of a material that makes ohmic contact with the conductive boron phosphide-based semiconductor crystal layer extends on the conductive boron phosphide-based semiconductor crystal layer. The boron phosphide-based semiconductor light-emitting device according to (6) above.
(8) The phosphorus according to (6) or (7), wherein a bottom surface portion of the pedestal electrode is made of a material that makes non-ohmic contact with the boron phosphide-based semiconductor amorphous layer. Boron-based semiconductor light emitting device.
(9) The pedestal electrode has a bottom surface portion on the boron phosphide-based semiconductor amorphous layer, and an ohmic electrode formed on the bottom surface portion and having a planar center and a shape center coincide with each other. The boron phosphide-based semiconductor light-emitting element according to any one of (1) to (8) above, wherein the boron phosphide-based semiconductor light-emitting element has a region.
(10) The boron phosphide-based semiconductor light-emitting element according to (9) above, wherein the ohmic electrode portion of the pedestal electrode has a plane area that exceeds a plane area of the bottom surface portion of the pedestal electrode.
(11) The boron phosphide-based semiconductor light-emitting device according to (10), wherein the ohmic electrode portion of the pedestal electrode extends to the surface of the conductive boron phosphide-based semiconductor crystal layer.
(12) A semiconductor layer including a light emitting layer is formed on a crystal substrate by a vapor deposition method, the vapor deposition method using the semiconductor layer as an underlayer and a crystal substrate temperature of 250 ° C. or more and 1200 ° C. or less. A boron phosphide-based semiconductor amorphous layer having a conductivity type or high resistance opposite to that of the base layer is deposited, and the boron phosphide-based semiconductor amorphous layer is selectively removed to form the boron phosphide-based semiconductor in the first region. In the second region other than the semiconductor amorphous layer, the semiconductor layer as the underlayer is exposed, and the exposed semiconductor layer as the underlayer and the boron phosphide-based semiconductor amorphous layer are exposed. A conductive boron phosphide-based semiconductor crystal layer is deposited on the crystal substrate by vapor phase epitaxy at a temperature of 750 ° C. to 1200 ° C., and the conductive boron phosphide-based semiconductor crystal in the first region is deposited. The boron phosphide-based semiconductor amorphous by selectively removing the layer A pedestal electrode for connection is formed on the exposed boron phosphide-based semiconductor amorphous layer so as to be in contact with the boron phosphide crystal layer, and then cut into individual light emitting elements. A method for producing a boron phosphide-based semiconductor light-emitting device.
(13) The conductive boron phosphide-based semiconductor crystal layer in the first region where the pedestal electrode is provided is removed, and at the same time, the band-shaped cutting line for cutting and separating the individual light emitting elements is provided. Remove the conductive boron phosphide-based semiconductor crystal layer The underlayer The method for producing a boron phosphide-based semiconductor light-emitting device according to the above (12), wherein the surface is exposed.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The boron phosphide-based semiconductor forming the amorphous and conductive crystal layer includes boron (element symbol: B) and phosphorus (element symbol: P), for example, B _α Al _β Ga _γ In _1-α-β-γ P _1-δ As _δ (0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ <1, 0 <α + β + γ ≦ 1, 0 ≦ δ <1. For example, B _α Al _β Ga _γ In _1-α-β-γ P _1-δ N _δ (0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ <1, 0 <α + β + γ ≦ 1, 0 ≦ δ <1). More specifically, monomeric boron phosphide (BP), boron phosphide / gallium / indium (composition formula B _α Ga _γ In _1-α-γ P: 0 <α ≦ 1, 0 ≦ γ <1) and boron nitride phosphide (composition formula BP _1-δ N _δ : 0 ≦ δ <1) and boron arsenide phosphide (composition formula B _α P _1-δ As _δ ) And the like. In particular, monomeric boron phosphide (BP) is a base material for boron phosphide-based semiconductor mixed crystals. If a BP having a wide forbidden band width of 2.8 to 3.4 electron volts (unit: eV) at room temperature is used as a base material, a boron phosphide-based amorphous layer having a wide forbidden band width or A crystalline layer can be formed. From the boron phosphide-based crystal layer having a forbidden band width of 3.0 eV, a barrier layer for a light emitting layer made of a group III nitride semiconductor having a forbidden band width of, for example, 2.7 eV, or a window capable of transmitting light to the outside A (window) layer can be suitably formed.
[0009]
The boron phosphide-based semiconductor amorphous layer or crystal layer may be formed by, for example, a halogen method (see “Journal of Japanese Society for Crystal Growth”, Vol. 24, No. 2 (1997), page 150), hydride method (J , Crystal Growth, 24/25 (1974), pages 193 to 196), and molecular beam epitaxy (see J. Solid State Chem., 133 (1997), pages 269 to 272). Can be formed. Further, vapor phase growth can be performed by a metal organic chemical vapor deposition (MOCVD) method (Inst. Phys. Conf. Ser., No. 129 (see IOP Publishing Ltd. (UK, 1993), pages 157 to 162)). In particular, the MOCVD method uses triethylboron (molecular formula: (C ₂ H ₅ ) ₃ Since an easily decomposable substance such as B) is used as a boron source, it is an advantageous growth means for vapor-phase growth of an amorphous layer at a lower temperature. When forming an amorphous layer made of a boron phosphide-based semiconductor depending on these vapor phase growth means, a temperature of 1200 ° C. or lower is suitable. At high temperatures above 1200 ° C, B ₁₃ P ₂ As a result, the growth of a boron phosphide-based semiconductor layer based on monomeric boron phosphide (BP) is inhibited. On the other hand, the element (constituent element) constituting the amorphous boron phosphide-based semiconductor layer can be sufficiently thermally decomposed in the vapor phase growth region, and the film formation can proceed to 250 ° C. or higher. Suitable. In general, when the vapor phase growth temperature is higher than 1000 ° C., an amorphous layer or a crystal layer exhibiting p-type conduction is easily obtained. The n-type conductive amorphous or crystalline layer can be formed at a temperature below 1000 ° C.
[0010]
In order to efficiently vapor-phase grow the boron phosphide-based amorphous layer using the above means, it is important to set the so-called V / III ratio in the range of 0.2 to 50. The V / III ratio can be expressed as a ratio of the total concentration of the Group V constituent elements to the total concentration of the Group III constituent elements supplied to the region (growth region) where the boron phosphide-based semiconductor layer is grown. . If this V / III ratio is extremely low, less than 0.2, many spheres rich in boron are generated, and an amorphous layer having a flat surface cannot be stably obtained, which is inconvenient. A V / III ratio exceeding 50 leads to formation of a polycrystalline layer and is not suitable for stably obtaining an amorphous layer. In the present invention, the term “crystal layer” refers to any of a single crystal layer, an amorphous and single crystal polycrystalline layer, and a single crystal having a different orientation. The boron phosphide-based crystal layer can be stably formed with a V / III ratio of 100 or more, more preferably 500 or more and 2000 or less. At a high V / III ratio exceeding 2000, precipitates containing Group V elements such as phosphorus are generated, which makes it difficult to obtain a flat surface boron phosphide-based semiconductor crystal layer, which is inconvenient. Amorphous, polycrystalline or single crystal can be distinguished by general X-ray diffraction or electron beam diffraction techniques.
[0011]
A boron phosphide-based semiconductor amorphous layer in which a vapor-deposited semiconductor layer is provided as an underlayer is a high-resistance amorphous layer having a high resistivity and a conductivity type opposite (reverse) to the semiconductor layer forming the underlayer It is preferable to form an amorphous layer having a multi-layer structure or a multilayer structure in which these layers are stacked. The resistivity of the high resistance amorphous layer is preferably 10 Ω · cm or more, more preferably 10 at room temperature. ² Ω · cm or more. For example, when the underlayer is an n-type layer, the conductivity type opposite to that of the underlayer indicates a p-type. The amorphous layer is formed of, for example, gallium nitride indium (composition formula Ga _X In _1-X N: 0 ≦ X ≦ 1), or aluminum nitride / gallium nitride (composition formula Al) _X Ga _1-X It is preferable to form a clad barrier layer made of N: 0 ≦ X ≦ 1) as an underlayer. For convenience, it is important to call a high-resistance amorphous layer as a “high-resistance amorphous layer” and an amorphous layer with the opposite conductivity type to the underlayer as an “opposite-conduction amorphous layer”. The reason is that either a high-resistance amorphous layer or an opposite-conductivity-type amorphous layer is provided under the bottom surface of the pedestal electrode disposed on the light emitting layer or the barrier layer, that is, in the projected region of the pedestal electrode. . In the configuration in which the bottom surface of the pedestal electrode is provided on the high-resistance amorphous layer, the high-resistance amorphous layer serves as a resistor that inhibits the element drive current from short-circuiting from the bottom surface of the pedestal electrode to the light emitting layer below. Works. In the configuration in which the bottom surface of the pedestal electrode is provided on an amorphous layer having a conductivity type opposite to that of the base layer, the conductive amorphous layer forms a pn junction structure with the base layer, and the element driving current is reduced to the bottom surface of the base electrode. It has the effect | action which inhibits distribute | circulating in a short circuit to the light emitting layer below. The region for forming the high-resistance amorphous layer or the opposite conductivity type amorphous layer (first region) need not be the same as the region for forming the bottom surface of the pedestal electrode (third region). Any region including at least a part of the bottom surface (projection region of the base electrode) is effective. However, it is preferable that the opposite conductivity type amorphous layer or the high resistance amorphous layer constituting the pn junction structure that does not allow the element driving current to flow be provided only in the projection region of the base electrode and its periphery. If the high resistance amorphous layer or the opposite conductivity type amorphous layer is formed in the projecting region of the pedestal electrode, the device driving current is prevented from flowing in a short circuit from the bottom surface of the pedestal electrode to the lower light emitting layer, In order to prevent light emission from occurring in the region of the light emitting layer that is shielded by the pedestal electrode, in order to allow the element driving current to flow through the underlayer sufficiently evenly, regions other than the first region (second region) This is because it is desirable that the conductive crystal layer formed in (1) is in contact with the base semiconductor layer over a wide area. If a high-resistance amorphous layer or an opposite conductivity type amorphous layer is formed widely in a region (second region) other than the projection region of the pedestal electrode, for example, if it is provided on the entire surface of the light emitting layer, the device driving current is reduced. Inconvenience arises in obtaining an LED with high emission intensity that can flow through the formation sufficiently evenly.
[0012]
Furthermore, when the boron phosphide-based semiconductor amorphous layer is formed by stacking a high-resistance amorphous layer and an amorphous layer having a conductivity type opposite to that of the base layer, the above-described element drive current short circuit is achieved. It is more effective in preventing general distribution. It is preferable to provide an opposite conductivity type amorphous layer on the underlayer, and then overlay a high resistance amorphous layer thereon. This is because, by interposing the high-resistance amorphous layer, the effect of reducing the element driving current flowing into the junction between the opposite conductivity type amorphous layer forming the pn junction and the underlying layer can be improved.
The thickness of the high-resistance amorphous layer is preferably 2 nm or more in the region where the bottom surface portion of the pedestal electrode is provided so that the surface of the underlayer can be uniformly coated. It is desirable that the opposite conductivity type amorphous layer has a thickness of 50 nm or more so as not to allow the carrier to pass through the underlying layer due to the tunnel effect. If the thickness of the high resistance amorphous layer or the opposite conductivity type amorphous layer exceeds 200 nm, the level difference between the ohmic electrode described later and the surface of the boron phosphide-based semiconductor crystal layer increases, and the boron phosphide-based layer is increased. This is not preferable because it hinders the formation of an electrode having excellent adhesion to the semiconductor crystal layer.
[0013]
In order to form a pedestal electrode whose bottom surface is in contact with an amorphous layer of opposite conductivity type or high resistance, first, the pedestal electrode is formed after growing the opposite conductivity type or high resistance amorphous layer on the underlying layer. After selectively removing the opposite conductivity type or high-resistance amorphous layer in the first region including the region to be formed, a conductive phosphoboron crystal layer is grown, and then a pedestal electrode is formed. The conductive boron phosphide-based crystal layer in the region is removed, and the surface of the amorphous layer having the opposite conductivity type or high resistance is exposed. Thereafter, a material convenient for constituting the bottom surface of the pedestal electrode is deposited on the surface of the exposed amorphous layer. The boron phosphide-based amorphous layer and the boron phosphide-based crystal layer can be removed by etching using, for example, a known chlorine (element symbol: Cl) plasma etching method. A known photolithography technique may be used to leave an amorphous layer of opposite conductivity type or high resistance in a selective region under the pedestal electrode. In providing the bottom surface of the pedestal electrode only in the plane region where the pedestal electrode is provided, it is preferable to apply a selective patterning technique using a known photolithography technique. Even when the bottom surface of the pedestal electrode is provided on the surface of an amorphous layer of opposite conductivity type or high resistance, the element driving current is short-circuited from the bottom surface portion to the lower light emitting layer in the projection region. Distribution can be hindered. As a result, the element driving current can be preferentially supplied to the light emitting region other than the projection region of the pedestal electrode where the light emission is shielded from the outside, which can contribute to, for example, obtaining an LED having a high light emission intensity.
[0014]
When the amorphous layer is constituted by a so-called undoped layer in which impurities are not intentionally added, it is effective in preventing the light emitting layer or the barrier layer of the base layer from being altered electrically or crystallinely. . In a laminated structure in which a conventional gallium nitride (GaN) layer intentionally doped with magnesium (element symbol: Mg) is provided on an n-type light emitting layer, the thermal effect of magnesium (Mg) as a p-type impurity In the case of a light emitting layer having a high resistance due to diffusion or a light emitting layer having a quantum well structure, the heterojunction interface between the barrier layer and the well layer can be avoided. In an amorphous layer made of a boron phosphide-based semiconductor, its conductivity can be controlled by adjusting the temperature (growth temperature) at which it is vapor-phase grown and the above V / III ratio. As the growth temperature is lower and the V / III ratio is set lower, an amorphous layer with higher resistance can be obtained. When vapor phase growth is performed at a high temperature and a high V / III group ratio, an amorphous layer having a lower resistance can be formed. The resistivity, which is a measure of the conductivity of the boron phosphide-based semiconductor amorphous layer, can be measured by a normal Hall effect measurement method.
[0015]
In addition to the function of preventing the short circuit flow of device operating current due to the opposite conductivity type or the high resistance amorphous layer, the bottom portion of the pedestal electrode is made of a non-ohmic contact material with respect to the boron phosphide-based semiconductor. Furthermore, it is effective in preventing the short circuit flow of the element driving current. Non-ohmic contact is contact that exhibits rectifying properties as seen in a Schottky junction. In the present invention, in particular, the contact resistance is 1 × 10 ^-3 Include contact that exceeds Ω · cm and increases. The material of the bottom portion of the pedestal electrode differs depending on the conductivity type of the boron phosphide-based semiconductor amorphous layer. For a p-type boron phosphide-based semiconductor amorphous layer, even if it has a high resistance, for example, gold (element symbol: Au) / germanium (element symbol: Ge), gold (Au) / tin (element symbol: Sn) ), Gold (Au) / indium (element symbol: In), and the like, the bottom surface portion is formed. For the n-type boron phosphide-based semiconductor amorphous layer, the bottom surface portion is made of a gold alloy such as gold (Au) / zinc (element symbol: Zn), gold (Au) / beryllium (element symbol: Be). Further, regardless of the conductivity type of the amorphous layer, a bottom portion having a rectifying property can be formed from the transition metal. Materials exhibiting Schottky rectification include titanium (element symbol: Ti), molybdenum (element symbol: Mo), vanadium (element symbol: V), tantalum (element symbol: Ta), hafnium (element symbol: Hf), and the like. Examples include tongue gutene (element symbol: W).
[0016]
An ohmic electrode made of a material that is in ohmic contact with the boron phosphide-based semiconductor crystal layer is provided on the coating that forms the bottom surface portion provided in contact with the surface of the boron phosphide-based semiconductor amorphous layer. The material constituting the ohmic electrode is selected in view of the conductivity type of the boron phosphide-based semiconductor crystal layer. The p-type boron phosphide-based semiconductor crystal layer can be made of a gold alloy such as gold / zinc or gold / beryllium. The n-type boron phosphide-based semiconductor crystal layer can be composed of, for example, a gold alloy such as gold / germanium, gold / tin, or gold / indium. If the boron phosphide-based semiconductor amorphous layer that provides the bottom portion of the pedestal electrode and the boron phosphide-based semiconductor crystal layer that provides the ohmic electrode are conductive layers opposite to each other, the bottom portion and the bottom portion of the pedestal electrode are provided. These ohmic electrodes can be made of the same material. For example, when forming a base electrode in which a p-type boron phosphide-based semiconductor amorphous layer is in contact with a bottom surface portion and an n-type boron phosphide-based crystal layer is in contact with an ohmic electrode, the bottom surface portion and the ohmic electrode are both An example is made of a gold / germanium alloy. It is not preferable to form both a Schottky rectifying property and an ohmic electrode from niobium (element symbol: Nb), chromium (element symbol: Cr), and the above transition metal.
[0017]
The flat area shall exceed the bottom area of the bottom part of the pedestal electrode, and the part which gives a flat area exceeding the bottom area will be extended to the surface of the boron phosphide-based semiconductor crystal layer and placed in contact therewith Then, an ohmic electrode can be formed that is in close contact with the surface of the boron phosphide-based semiconductor crystal layer. After forming the bottom surface portion including the bottom surface provided in contact with the boron phosphide-based semiconductor amorphous layer, the material constituting the ohmic electrode is coated so as to be in contact with the bottom surface portion and also in contact with the boron phosphide-based semiconductor crystal layer. After the deposition, for example, a circular bottom surface can be formed by processing an ohmic electrode material using a known photolithography technique so that a circular electrode having a larger diameter is obtained. In this case, the region of the ohmic electrode located on the outer edge from the circular region of the bottom surface region is brought into close contact with the surface of the boron phosphide-based semiconductor crystal layer. The planar shape of the bottom portion and the planar shape of the ohmic electrode are not necessarily similar. For example, an example in which the planar shape of the bottom portion is a circle and the planar shape of the ohmic electrode is a square can be given. However, the center of the planar shape of the bottom surface portion and the center of the planar shape of the ohmic electrode are usually matched to form a pedestal electrode that is in close contact with the boron phosphide-based semiconductor crystal layer with isotropic strength in a plane. Especially desirable above.
[0018]
When the ohmic electrode is placed in electrical conduction with an ohmic electrode provided so as to be in close contact with the boron phosphide-based semiconductor crystal layer and further extended on the surface of the boron phosphide-based semiconductor crystal layer, the projection of the pedestal electrode is obtained. This is preferable because the element driving current can be distributed to the light emitting region other than the region. That is, in an LED having a method of extracting light emitted to the outside by transmitting through a boron phosphide-based semiconductor crystal layer, an element driving current is applied to a light emitting region that is not shielded by the pedestal electrode and is convenient for extracting light emitted to the outside. Can diffuse in a plane. The ohmic electrode extended in this manner has a function of diffusing the element driving current, which is obstructed by the bottom surface of the pedestal electrode, from being short-circuited to the light emitting layer in the projection region, in a wide range in the light emitting region. It can contribute to manufacture LED with high luminous intensity. The ohmic electrode provided to extend on the surface of the boron phosphide-based semiconductor crystal layer can be composed of a material different from that of the ohmic electrode forming the base electrode. For example, there is an example in which the ohmic electrode of the pedestal electrode is made of gold / germanium alloy and the extended ohmic electrode is made of gold / tin alloy. The extended ohmic electrode has better adhesion to the boron phosphide-based semiconductor crystal layer than the group III element gallium (element symbol: Ga) or indium (element symbol: In). It can be more preferably composed of an alloy containing group IV elements tin (Sn) and germanium (Ge). If both the base electrode and the extended ohmic electrode are made of the same material, they can be formed at the same time, and it is possible to contribute to obtaining a boron phosphide-based semiconductor light-emitting device easily in the process.
[0019]
The extended ohmic electrode is desirably arranged so that the element driving current can be evenly distributed uniformly in the light emitting region other than the projection region of the base electrode. In other words, it is preferable to arrange them so that a uniform potential distribution is obtained on the surface of the boron phosphide-based semiconductor crystal layer and thus on the surface of the light emitting layer. The extended ohmic electrode can be composed of a strip-like, annular, or frame-like electrode electrically connected to the pedestal electrode. Further, these band electrodes and frame electrodes can be combined and made conductive. The linear electrodes constituting the strip-like, annular, or frame-like electrodes are usually 10 μm or more, more preferably 20 μm so that they will not be disconnected even when the element driving current that flows is increased. It is desirable to have the above line width. By using a known photolithography technique, patterning technique, and selective etching technique, a linear electrode having a desired shape and line width can be laid on the surface of the boron phosphide-based semiconductor crystal layer.
[0020]
The boron phosphide-based semiconductor light emitting device is manufactured by forming an ohmic electrode attached to the pedestal electrode or the pedestal electrode and then cutting the individual device. The cutting into individual elements is usually performed by using a linear groove called a cutting line, a scribe line or a dicing line provided along the cleavage direction of the crystal forming the substrate. In the present invention, in order to provide the bottom portion of the pedestal electrode in contact with the boron phosphide-based semiconductor amorphous layer as described above, it is necessary to remove the boron phosphide-based semiconductor crystal layer in the region where the bottom portion is provided. . At the same time, if a groove for cutting lines is formed in an individual element, a process for obtaining a boron phosphide-based semiconductor light emitting element can be simplified. Therefore, in the present invention, the surface of the amorphous layer is exposed in the region where the bottom surface portion of the base electrode is formed, and at the same time, the region where the cutting line is provided. The underlayer The surface of the substrate is exposed to form a groove for cutting. For example, when a cubic zinc blende type crystal is used as the substrate, it is advantageous to provide the grooves for cutting in the <110> crystal orientations that are orthogonal to each other. The width of the groove for cutting (cutting line) depends on the contact of the cutting edge of the cutting tool, and the boron phosphide-based semiconductor crystal layer that forms the side of the groove big It is preferable to have a sufficient width so as not to be damaged. In general, the thickness is preferably 40 μm or more and 70 μm or less. If the width exceeds 70 μm, the width of the groove becomes unnecessarily wide. of There is a grace period. For this reason, it travels linearly due to the “blurring” of the cutting edge. No longer For this reason, it becomes difficult to obtain an individual element having a smooth cross section after cutting.
[0021]
[Action]
A boron phosphide-based semiconductor amorphous layer having a high resistance or a conductivity opposite to that of the base layer disposed below the bottom surface of the pedestal electrode has an element driving current supplied through the bottom surface of the pedestal electrode provided thereon, It has the effect of preventing a short circuit from flowing into the light emitting layer located below.
[0022]
The bottom surface of the pedestal electrode made of a material that exhibits non-ohmic contact with the boron phosphide-based semiconductor allows the element drive current supplied through the pedestal electrode to be short-circuited to the underlying boron phosphide-based semiconductor amorphous layer. It has the effect of avoiding circulation.
[0023]
The ohmic electrode provided in contact with the bottom surface part forming part of the base electrode, having a plane area larger than the bottom area of the bottom surface part, and in contact with the surface of the boron phosphide-based semiconductor crystal layer is boron phosphide-based. It has the effect | action which brings about the base electrode which is excellent in adhesiveness with a semiconductor layer.
[0024]
The ohmic electrode, which is electrically connected to the ohmic electrode that forms part of the pedestal electrode and extends to the surface of the boron phosphide-based semiconductor crystal layer, distributes the device driving current over a wide range to the light emitting region. Have
[0025]
(First embodiment)
The boron phosphide-based semiconductor light emitting device according to the present invention is specifically exemplified by the case where a light emitting diode (LED) having a pedestal electrode having a bottom surface in contact with the surface of the high resistance boron phosphide amorphous layer is constructed. Explained. FIG. 1 schematically shows a cross-sectional structure of a laminated structure 11 used for manufacturing an LED 10 having a double hetero (DH) junction structure.
[0026]
As the substrate 101, phosphorus (P) -doped n-type silicon (Si) single crystal was used. On the surface of the substrate 101, a lower clad layer 102 made of n-type boron phosphide (BP) was deposited using an atmospheric pressure (substantially atmospheric pressure) metal organic vapor phase epitaxy (MOVPE) means. The lower cladding layer 102 is made of triethyl boron (molecular formula: (C ₂ H ₅ ) ₃ B) is a boron (B) source, and phosphine (molecular formula: PH ₃ ) As a phosphorus source. The carrier concentration of the undoped n-type BP layer forming the lower cladding layer 102 is 1 × 10 ¹⁹ cm ^-3 The layer thickness was 420 nm.
[0027]
On the n-type lower clad layer 102, an n-type gallium nitride indium (Ga) grown by vapor deposition by an atmospheric pressure MOCVD method is used. _0.90 In _0.10 The light emitting layer 103 made of N) was formed at 825 ° C. The gallium nitride / indium layer constituting the well layer 103 is composed of a multi-phase structure composed of a plurality of phases having different indium compositions, and the average indium composition is 0.10 (= 10 %)Met. The layer thickness of the well layer 103 was 10 nm. On the light-emitting layer 103, trimethylgallium (molecular formula: (CH ₃ ) ₃ Ga) / NH ₃ / H ₂ A silicon (Si) -doped n-type gallium nitride (GaN) layer 104 was bonded at 825 ° C. by a reactive atmospheric pressure MOCVD means. The layer thickness of the GaN layer 104 was 20 nm. This n-type GaN layer 104 is provided in order to form a band structure having a bent conduction band and valence band in the inner region of the light emitting layer 103 in the vicinity of the junction interface.
[0028]
An amorphous layer 105 made of undoped boron phosphide (BP) was provided on the n-type GaN layer 104. The amorphous layer 105 made of boron phosphide is composed of (C ₂ H ₅ ) ₃ B / PH ₃ / H ₂ It was provided depending on the reaction system atmospheric pressure MOCVD means. The amorphous layer 105 has a V / III ratio (= PH) at 550 ° C. ₃ / C ₂ H ₅ ) ₃ Since B) was vapor phase-grown at 10, a high resistance layer having a resistivity of 10 Ω · cm was obtained at room temperature. The layer thickness of the undoped boron phosphide amorphous layer 105 was 15 nm. Next, the amorphous layer 105 was left only in a region where the pedestal electrode 107 was to be formed by using a known selective patterning technique and plasma etching technique. The region where the amorphous layer 105 was left was a circular region having a diameter of 120 μm. In the remaining area, the amorphous layer 105 was removed by etching to expose the surface of the n-type GaN layer 104.
[0029]
Next, (C ₂ H ₅ ) ₃ B / PH ₂ / H ₂ A p-type boron phosphide crystal layer 106 is bonded to the surface of the remaining amorphous layer 105 and the exposed n-type GaN layer 104 using a reactive atmospheric pressure MOCVD means and a vapor phase growth apparatus. Was established. The undoped boron phosphide crystal layer 106 was provided at 1025 ° C., which is higher than that of the amorphous layer 105. Since the V / III ratio during vapor phase growth was 1300, the carrier concentration of the boron phosphide crystal layer 106 was 2 × 10. ¹⁹ cm ^-3 Thus, the layer thickness was set to 580 nm. In addition, since the forbidden band width at room temperature of the boron phosphide crystal layer 106 is 3.2 eV, the boron phosphide crystal layer 106 is a p-type upper cladding layer that also serves as a window layer for transmitting light emission to the outside. Used as.
[0030]
A region where the central pedestal electrode 107 on the surface of the boron phosphide crystal layer 106 forming the p-type upper cladding layer is selectively patterned into a circular planar shape using a known photolithography technique. At the same time, the pattern 108 was also selectively patterned into a band-like planar shape in the region 108 where the cutting groove was provided. Thereafter, argon (Ar) / methane (molecular formula: CH _Four ) / H ₂ The boron phosphide crystal layer 106 overlying the amorphous layer 105 was selectively removed by etching, limited to the region subjected to the above patterning, by a plasma etching method using a mixed gas. Thus, the surface of the boron phosphide amorphous layer 105 was exposed in a circular plane region having a diameter of 100 μm where the pedestal electrode 107 was provided. In the band-like region 108 having a width of 50 μm as a cutting line, n-type GaN layer 104 The surface of was exposed at the same time. The strip-shaped region 108 for use as a cutting line was provided in parallel to the <110> crystal orientations orthogonal to each other, which is the cleavage direction of the Si single crystal of the substrate 101.
[0031]
Next, gold / germanium (Au 95 wt.%) Forming the bottom surface portion 107a of the pedestal electrode 107 is formed using a photoresist material that has been subjected to selective patterning so as to open only in the region where the pedestal electrode 107 is provided as a mask. Ge 5 wt%) alloy film was deposited by a general vacuum deposition technique. Thereafter, the Au / Ge film deposited on the surface of the mask material was removed as the mask material was peeled off and removed from the surface of the boron phosphide crystal layer 106. The layer thickness of the Au / Ge film forming the bottom surface portion that was left only in the region of the base electrode 107 was 150 nm. Next, after the surface of the boron phosphide crystal layer 106 is coated with a photoresist material, a circular opening having a diameter of 150 μm is provided only in a region where the ohmic electrode 107b of the pedestal electrode 107 is provided by a selective patterning technique. It was. The center of the opening this time was matched with the planar shape of the bottom surface portion 107a. Next, a gold / beryllium (Au 99 wt% / Be 1 wt%) alloy film was formed by a general vacuum vapor deposition method to form an ohmic electrode 107 b in ohmic contact with the p-type boron phosphide crystal layer 106. The thickness of the ohmic electrode 107b was 800 nm. The Au / Be alloy film on the surface of the mask material other than the ohmic electrode 107b for constituting the base electrode 107 was removed while removing the mask material. As a result, the ohmic electrode 107b having a larger area than the bottom surface portion 107a and forming the upper portion of the pedestal electrode 107 in contact with the surface of the p-type boron phosphide crystal layer 106 was formed.
[0032]
Next, an n-type ohmic electrode 109 made of an aluminum (Al) / antimony (Sb) alloy was provided on the back surface of the silicon single crystal substrate 101. By stripping the mask material for providing the pedestal electrode 107 in the center of the boron phosphide crystal layer 106, the band-shaped region 108 for cutting use, which has been formed in advance, n-type GaN layer 104 Was exposed. Along the cutting band 108, ie the cutting line, the diamond blade is n-type GaN layer 104 It was made to run linearly on the surface. From this, it divided | segmented into square individual LED10 whose length of one side (= distance between the centerline of the adjacent cutting line 108) is 300 micrometers. Since the width of the cutting line 108 was about 2.5 times wider than the width of the blade (about 20 μm), the side surfaces of the individually divided LEDs 10 were flat.
[0033]
In observation by a general cross-sectional TEM technique, the limited-field electron diffraction image from the boron phosphide amorphous layer 105 was halo. On the other hand, the electron diffraction pattern of the boron phosphide crystal layer 106 shows a polycrystalline layer that generates a larger number of diffraction spots on the diffraction ring than in the case of the single crystal layer.
[0034]
In the present invention, since the ceiling portion of the ohmic electrode 107b having a larger planar area than the bottom surface portion 107a is provided in contact with the surface of the p-type boron phosphide crystal layer 106, peeling of the pedestal electrode 107 is recognized even during connection. There wasn't. Between the base electrode 107 and the n-type ohmic electrode 109 having excellent adhesion, a device drive current of 20 mA was passed in the forward direction to confirm the light emission characteristics. LED 10 emitted blue band light having a central wavelength of 440 nm. The half width of the emission spectrum was 280 millielectron volts (unit: meV). The luminance in a chip state before the resin mold measured using a general integrating sphere was 7 millicandelas (mcd). Further, since the bottom surface portion 107a below the p-type ohmic electrode 107b is provided in contact with the surface of the high resistance boron phosphide amorphous layer 105, the element driving current can be distributed over a wide range to the light emitting layer 103. Light emission with uniform intensity was brought about from substantially the entire light emitting region other than the projected region of the electrode 107. The forward voltage was 3.5 V when the forward current was 20 mA. The reverse voltage when the reverse current was 10 μA was 8.2V.
[0035]
(Second embodiment)
In the present invention, a double heterojunction (DH) structure type light emitting diode (LED) having a base electrode having a bottom surface in contact with the surface of a boron phosphide amorphous layer having a multilayer structure is taken as an example. The boron phosphide-based semiconductor light emitting device will be specifically described.
[0036]
FIG. 2 schematically shows a planar structure of the LED 12 according to the second embodiment. FIG. 3 schematically shows the cross-sectional structure of the LED 12 taken along the broken line AA ′ shown in FIG. 2 and 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals.
[0037]
First, an undoped p-type boron phosphide amorphous layer 201 was formed on the n-type GaN light emitting layer 104 formed as described in the first embodiment. The carrier concentration of the p-type boron phosphide amorphous layer 201 is 8 × 10 ¹⁸ cm ^-3 The layer thickness was 12 nm. On the p-type boron phosphide amorphous layer 201, an undoped and high resistance boron phosphide amorphous layer 105 was laminated. The resistivity of the high-resistance boron phosphide amorphous layer 105 at room temperature was 10 Ω · cm, and the layer thickness was 12 nm. The p-type boron phosphide amorphous layer 201 and the high-resistance boron phosphide amorphous layer 105 are limited to a region where the pedestal electrode 107 is to be provided using a known photolithography technique, The high resistance amorphous layers 105 and 201 were left. The p-type and high-resistance amorphous layers 105 and 201 were left in a circular shape in plan view with the same center and a diameter of 120 μm. Next, the undoped p-type boron phosphide crystal layer 106 described in the first example was deposited on the high resistance boron phosphide amorphous layer 105.
[0038]
Next, using a plasma etching technique, the p-type boron phosphide crystal layer 106 is selectively removed to limit the regions where the pedestal electrode 107 is provided and the region where the cutting line 108 is provided, and high resistance phosphation is performed. The surface of the boron amorphous layer 105 was exposed. The planar region from which the p-type boron phosphide crystal layer 106 was removed was a circle having a diameter of 150 μm. The center of the circular region was made to coincide with the center of the circular plane of the remaining high resistance boron phosphide amorphous layer 105. Next, a base electrode 107 in which the bottom surface portion 107a in contact with the surface of the high resistance boron phosphide amorphous layer 105 is molybdenum (Mo) and the ohmic electrode 107b in the upper portion is gold / beryllium (Au / Be) is formed. Formed. The thickness of the molybdenum (Mo) coating was 10 nm, and the thickness of the Au · Be coating was 700 nm. The Au / Be ohmic electrode 107b that forms the ceiling of the pedestal electrode 107 was provided with an annular electrode and a linear electrode as an auxiliary ohmic electrode 107c as shown in FIG.
[0039]
As described in the first embodiment, {1. -1.0} and {-1. -1.0} Each LED 12 was separated and cut along a cutting line 108 provided parallel to the crystal orientation. The emission center wavelength when a forward current of 20 mA was passed through a square LED 12 having a side of 350 μm was 440 nm, which was substantially the same as that of the LED 10 described in the first example. The brightness in the chip state measured using a general integrating sphere was 9 mcd, resulting in an LED having a higher emission intensity than the LED 10 of the first example. Further, according to the near-field emission image, it was confirmed that light emission with uniform intensity from the emission region other than the base electrode 107 was brought about. This is because the bottom portion 107a below the p-type ohmic electrode 107b, which is the upper portion, is provided on a multilayer structure composed of p-type and high-resistance boron phosphide amorphous layers 105 and 201, and element driving current is supplied to the light emitting layer. It was recognized that this was an effect that could be distributed over a wide range to 103. When the forward current was 20 mA, the forward voltage was 3.4 V, and when the reverse current was 10 μA, the reverse voltage was 8.3 V.
[0040]
【The invention's effect】
According to the present invention, a boron phosphide-based semiconductor crystal layer is provided via a boron phosphide-based semiconductor amorphous layer, and the bottom surface portion is in contact with the surface of the boron phosphide-based semiconductor amorphous layer, Since the pedestal electrode is provided so as to be in contact with the surface of the boron phosphide-based semiconductor crystal layer, it has excellent adhesion to the boron phosphide-based semiconductor crystal layer, and the device drive current is shielded against the pedestal electrode, for example. Therefore, it is possible to provide a boron phosphide-based semiconductor light emitting device such as a light emitting diode having a wide light emitting region and a high light emitting intensity.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a cross-sectional structure of an LED described in a first embodiment.
FIG. 2 is a schematic diagram showing a planar structure of an LED described in a second embodiment.
FIG. 3 is a schematic view showing a cross-sectional structure of an LED described in a second embodiment.
[Explanation of symbols]
10,12 ... LED
11 ... Laminated structure
101 ... Silicon single crystal substrate
102 ... n-type boron phosphide layer
103: n-type gallium nitride / indium light emitting layer
104: n-type gallium nitride layer
105. High resistance boron phosphide amorphous layer
106 ... p-type boron phosphide crystal layer
107: Pedestal electrode
107a: Bottom portion of base electrode
107b: Ohmic electrode forming the upper part of the base electrode
107c ... incidental ohmic electrode
108 ... groove for cutting (cutting line)
109 ... n-type ohmic electrode
201: p-type boron phosphide amorphous layer

Claims

A semiconductor layer including a light-emitting layer is formed as a base layer on a crystal substrate, a boron phosphide-based semiconductor amorphous layer is formed on a first region on the semiconductor layer, and the boron phosphide-based semiconductor amorphous The layer includes a high-resistance boron phosphide-based semiconductor amorphous layer, a pedestal electrode for connection is formed on the high-resistance boron phosphide-based semiconductor amorphous layer, and the semiconductor layer as the underlayer is formed on the semiconductor layer A conductive boron phosphide-based crystal layer is formed on a second region other than the first region, optionally extending to a part of the boron phosphide-based semiconductor amorphous layer, and the base electrode is A boron phosphide-based semiconductor light emitting device characterized by being in contact with the boron phosphide-based semiconductor crystal layer above the bottom surface.

A semiconductor layer including a light-emitting layer is formed as a base layer on a crystal substrate, a boron phosphide-based semiconductor amorphous layer is formed on a first region on the semiconductor layer, and the boron phosphide-based semiconductor amorphous The layer includes a boron phosphide-based semiconductor amorphous layer having a conductivity type opposite to that of the semiconductor layer as the underlayer, and a connection base electrode is provided on the opposite conductivity-type boron phosphide-based semiconductor amorphous layer. A conductive boron phosphide-based crystal layer is optionally formed on the second region other than the first region on the semiconductor layer as the base layer. The boron phosphide-based semiconductor light-emitting device is formed to extend to a portion, and the pedestal electrode is in contact with the boron phosphide-based semiconductor crystal layer above the bottom surface.

The boron phosphide-based semiconductor amorphous layer having a conductivity type opposite to that of the semiconductor layer as the underlayer formed in contact with the semiconductor layer as the underlayer 3. A multilayer structure comprising a layer and a high resistance boron phosphide-based semiconductor amorphous layer formed on the opposite conductivity type boron phosphide-based semiconductor amorphous layer. The boron phosphide-based semiconductor light-emitting device described.

4. The boron phosphide-based semiconductor light-emitting element according to claim 1, wherein the boron phosphide-based semiconductor amorphous layer is composed of an undoped boron phosphide-based semiconductor.

The two boron phosphide-based semiconductor amorphous layers constituting the multilayer structure of the boron phosphide-based semiconductor amorphous layer are both composed of an undoped boron phosphide-based semiconductor. The boron phosphide-based semiconductor light-emitting device according to claim 3.

The portion of the pedestal electrode that is in contact with the conductive boron phosphide-based semiconductor crystal layer is made of a material that makes ohmic contact with the conductive boron phosphide crystal layer. The boron phosphide-based semiconductor light-emitting device according to claim 1.

The portion of the pedestal electrode made of a material that makes ohmic contact with the conductive boron phosphide-based semiconductor crystal layer extends on the conductive boron phosphide-based semiconductor crystal layer. Item 7. A boron phosphide-based semiconductor light-emitting device according to Item 6.

8. The boron phosphide-based semiconductor light-emitting element according to claim 6, wherein a bottom surface portion of the pedestal electrode is made of a material that makes non-ohmic contact with the boron phosphide-based semiconductor amorphous layer. .

The pedestal electrode includes a bottom surface portion on the boron phosphide-based semiconductor amorphous layer, and an ohmic electrode portion formed on the bottom surface portion and having a planar shape center coincident with a shape center. The boron phosphide-based semiconductor light-emitting element according to claim 1, comprising:

The boron phosphide-based semiconductor light-emitting element according to claim 9, wherein the ohmic electrode portion of the pedestal electrode has a plane area that exceeds a plane area of the bottom surface portion of the pedestal electrode.

The boron phosphide-based semiconductor light-emitting element according to claim 10, wherein the ohmic electrode portion of the pedestal electrode extends to a surface of the conductive boron phosphide-based semiconductor crystal layer.

A semiconductor layer including a light emitting layer is formed on a crystal substrate by a vapor deposition method, the semiconductor layer is used as a base layer, and the temperature of the crystal substrate is 250 ° C. or more and 1200 ° C. or less. A boron phosphide-based semiconductor amorphous layer having an opposite conductivity type or high resistance is deposited, the boron phosphide-based semiconductor amorphous layer is selectively removed, and the boron phosphide-based semiconductor amorphous material is removed in the first region. In the second region other than the porous layer, the semiconductor layer as the base layer is exposed, and crystals are formed on the exposed semiconductor layer and the boron phosphide-based semiconductor amorphous layer as the base layer. A conductive boron phosphide-based semiconductor crystal layer is deposited by vapor phase epitaxy with a substrate temperature of 750 ° C. or higher and 1200 ° C. or lower, and the conductive boron phosphide-based semiconductor crystal layer in the first region is selected. To remove the boron phosphide-based semiconductor amorphous layer A connection base electrode is formed on the exposed boron phosphide-based semiconductor amorphous layer so as to be in contact with the boron phosphide crystal layer, and then cut into individual light-emitting elements. A method of manufacturing a boron phosphide-based semiconductor light emitting device.

The conductive boron phosphide-based semiconductor crystal layer in the first region in which the pedestal electrode is provided is removed, and at the same time, the conductive material in the region in which the band-shaped cutting line for cutting and separating the individual light emitting elements is provided. 13. The method for manufacturing a boron phosphide-based semiconductor light-emitting device according to claim 12, wherein the boron phosphide-based semiconductor crystal layer is removed to expose a surface of the underlying layer below.