TW200414460A - Method for fabricating a chip package - Google Patents

Method for fabricating a chip package Download PDF

Info

Publication number
TW200414460A
TW200414460A TW092101441A TW92101441A TW200414460A TW 200414460 A TW200414460 A TW 200414460A TW 092101441 A TW092101441 A TW 092101441A TW 92101441 A TW92101441 A TW 92101441A TW 200414460 A TW200414460 A TW 200414460A
Authority
TW
Taiwan
Prior art keywords
substrate
chip
sealant
wafer
wafers
Prior art date
Application number
TW092101441A
Other languages
English (en)
Chinese (zh)
Other versions
TWI313047B (enExample
Inventor
Kenny Chang
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW092101441A priority Critical patent/TW200414460A/zh
Publication of TW200414460A publication Critical patent/TW200414460A/zh
Application granted granted Critical
Publication of TWI313047B publication Critical patent/TWI313047B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW092101441A 2003-01-23 2003-01-23 Method for fabricating a chip package TW200414460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092101441A TW200414460A (en) 2003-01-23 2003-01-23 Method for fabricating a chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092101441A TW200414460A (en) 2003-01-23 2003-01-23 Method for fabricating a chip package

Publications (2)

Publication Number Publication Date
TW200414460A true TW200414460A (en) 2004-08-01
TWI313047B TWI313047B (enExample) 2009-08-01

Family

ID=45072705

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092101441A TW200414460A (en) 2003-01-23 2003-01-23 Method for fabricating a chip package

Country Status (1)

Country Link
TW (1) TW200414460A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354970B2 (en) 2010-08-06 2019-07-16 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354970B2 (en) 2010-08-06 2019-07-16 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection
US10707183B2 (en) 2010-08-06 2020-07-07 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection
US11121108B2 (en) 2010-08-06 2021-09-14 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection

Also Published As

Publication number Publication date
TWI313047B (enExample) 2009-08-01

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MK4A Expiration of patent term of an invention patent