TW200412667A - Flash memory device structure and manufacturing method thereof - Google Patents

Abstract

A flash memory device structure is provided, the flash memory device comprises: a P type substrate with an opening, an N type deep well is set in the P type substrate, a first gate structure and a second gate structure are set on the sidewall respectively, a insulation layer is set between the first gate structure and the second gate structure, a source region is set in the P type substrate of the bottom of the opening, a drain region is set in the P type substrate of the top of the opening, a P type well is set in the N type deep well and the junction of the P type well and N type deep well is higher than the bottom of the opening, a P type pocket doping region is set in the P type substrate on the sidewall of the opening and the P type pocket doping region connect the P type well and the source region.

Description

200412667

V. Description of the invention (1) Field of invention to which the invention belongs The present invention relates to a non-Memory (NVM) device, and a special structure and a manufacturing method thereof. In the prior art, flash memory elements have become a personal computer and a volatile memory element due to their actions such as removal, erasure, and storage. Non-volatile memory (non-volatile) is a type of atypical pneumonia that is widely used in excellent writing equipment that has a flash memory device that can store data multiple times and read tributary materials that will not disappear even after a power failure. The type of flash memory device is made of doped polycrystalline silicon to make the floating gate and control gate (c0ntr〇1 gate). And the control gate is directly set on the floating gate, the floating gate. The gate and the control electrode are separated by a gate dielectric layer, and the floating gate and the substrate are separated by a tunnel oxide layer (the so-called stacked gate flash memory is used as a pair of flash memory). When writing data, the control gate and source / > and the polar region are applied to bias the electrons into the floating interelectrode. When reading the data in the flash memory, A working voltage is applied to the control gate f. At this time, the charged state of the floating gate will affect the opening / closing of its lower channel (Channel), and the opening / closing of this channel is the reading data value "0" or "1 ". When flash memory is erasing data, it is the base And (source) electrode area or control gate relative potential is increased, and the tunneling effect is used to make electrons from the floating gate through the tunneling oxide layer (Tunneling Oxide) and discharge to the substrate or drain (source) (which is

Substrate Erase or Drain (Source) Side Erase), or

200412667 V. Description of the invention (2) Pass through the inter-gate dielectric layer and discharge into the control gate. Please refer to the structure diagram of the conventional stack gate flash memory shown in FIG. 1 (U.S. Patent No. US 62 1 4668). The flash memory is composed of a deep N-type well region 102 in a p-type substrate, 00, a stacked gate structure on a p-type substrate, 100, and two sides of the stacked gate structure 106. The source region 108 and the drain region 1 10 in the p-type substrate 100, the spacer 1 on the side wall of the stacked gate structure 10, 2 and the deep N-type well region 102 And extends from the drain region 110 to the stacked gate structure 106 (through the oxide layer 120, the floating gate 122, the gate dielectric layer 124, the control gate 126, and the gate cap layer 28) The contact of the P-type well region 104, the inner dielectric layer 114 on the p-type substrate 100, the contact between the drain region 110 and the P-type well region through the inner dielectric layer 114 and the p-type substrate 100 in a short circuit. The window 116 is constituted by a wire 1 1 8 which is located on the inner dielectric layer 114 and is electrically connected to the contact window ιβ. However, as the integrated circuit is being developed toward a miniaturized component with a higher integration degree, the above-mentioned flash memory structure will have the following problems. For example. In order to increase the accumulation of memory components, children need to reduce the memory cell size of flash memory components. Among them, reducing the size of the memory cell can be achieved by means of the gate length of the little brother memory cell and the interval between the data lines. However, a smaller gate length shortens the channel length below the tunneling oxide layer 2 (). It is easy to cause abnormal electrical penetration between the drain region 11 and the source region 108. (Punch Thr〇ugh), so it will seriously affect this. Ji Yi cell electrical performance. In addition, in the manufacture of flash memory, there is also a so-called critical size problem when putting on shirts for personal use.

200412667 V. Description of the invention (3) Reduction of the memory cell size. In addition, the roads are connected together, and the polar region 110 and the ρ-type well region 104 are below the short-pole structure 106, so the pole region 110 extends to the stack gate V 丨 人 + 人 田 5 When zooming out, the P-type # F ·!, The lateral direction may enclose the drain region (N + -type doping). ^: When the memory cell is in the source region, it is 6 volts left. The normal reason of the adjacent flash memory cells is: Ming :: The structure of flash memory cells has the disadvantage of limited integration. In view of this, the purpose of the present invention is to provide a flash memory, body structure, and manufacturing method, which can avoid the occurrence of strikes in the 'and drain region m). Wear (Punch original ♦ [6 :) High accumulation of memory components. In view of this, the present invention provides a structure of a flash memory element, a structure of a body, ... a first type soil with openings and a first type conductive substrate. The first well region of the second conductivity type,; set: open: the bottom and side walls pass through the dielectric layer, and the first floating gate and the second floating gate are respectively arranged on the second, second, and second private layers. 2. Set the two gate dielectric layers on the gate and the second floating gate, the first control gate and the second control gate on the first conductive substrate, and the first control gate extends. Complex I—the side wall of the floating gate, the second control gate extending to cover the side wall of the second floating gate, and the insulation placed in the gap between the first-control gate and the second control gate Layer, a gap wall provided on the side wall of the first control gate and a second control gate, a source region in the second conductive type substrate provided at the bottom of the opening, and a first conductive type 200412667 provided below the gap wall 2. Description of the invention (4) The conductive substrate-doped pocket-doped region at the junction of the second-well region of the drain type in the substrate is in the above-mentioned polar region Disposed in the second guide portion and the second conductivity type disposed conductive pear port region "and one of the first opening than the first connecting a first end of a second conductivity type structure, the drain is connected electrically shorted together. The region and the first conductive type second well include the first electrical layer and the dielectric layer of the tunnel. The first conductive type is provided in the channel area. This can be achieved by eliminating the size of the component. The method of the present invention firstly mentions a flash type floating gate electrode of a conductive type base and a contact window, and the top of the opening in the substrate surrounds the opening side wall to control the shrinkage of the opening. The first well area of the electrical type on the side wall and bottom of the inter-gate dielectric port of the internally connected memory element on the bottom is placed in the ▲ push well area and a conductive short circuit plane. And layer dielectric wires. Structure layer, control 'and draw the first guide in the p-type substrate (vertical depth accurately control the problem, and the first guide in a well area and the first area of the first opening side wall of the conductive plastic And the first conductive plastic source region. The second and second well regions are connected by a contact window through the light pole and the upper structure is more clad and arranged in the interlayer, and the gate structure (through the gate) is arranged in In the polar region and the source region, the straight-type channel region of the sub-type substrate), due to the channel length, can be avoided to increase the component integrated conductivity first patterned port. A method for manufacturing one or two flash memory devices in the opening. This work-type substrate, and a second ® loneliness has been formed in this substrate. A lining and a curtain are sequentially formed on the substrate. A hollow liner and a substrate are formed so that a tunnel dielectric layer is formed in the substrate, and a mixed region is formed in the substrate in the side wall of the opening. Then, a first is formed on the side wall of the opening

10326twf.ptd Page 9

200412667 V. Description of the invention (5) The floating gate and the second spring strike form an inter-gate intermediary in the opening:; ::: bottom :: form Qin. Yuji and the second control gate, and the first-control interpole :: ϊ j U: the side of the pole splits, Mongolia-missing J, 邛 Fu Jidi / Yu brake, and then moves the star ::: 甲 ' The electrode extension covers a side wall of the second floating gate. : 导 ΐΞί: "layer, and after forming the drain region in the substrate, the first well of the first conductivity type is formed in the second ... the adjacent surface of the first well of the first conductivity type is higher than the open bottom

The distance between the two control poles and the second control pole forms an insulation increase, and the second control pole plate H is controlled by 丨 M F. „„. ^ ^ ^ / The side wall forms a first room. Then, after an inner dielectric layer is formed on the substrate, a contact window is formed in the inner dielectric layer. This contact window makes a short-circuit connection between the drain region and the first conductivity type. After that, the guide of the sexual connection in the inner thick Jitai a is formed and the contact window is formed in the above-mentioned flash memory element manufacturing method by ^ _ forming the first-floating interpole and the second floating interrogator 4: System 3 filling Open the first conductor layer, and then remove a part of the second conductor = 7 The surface of the first conductor layer is slightly lower than the surface of the substrate, and it should be a 'two into a second gap [after the cover layer and between; : Conductor | to form the first floating interpole AND; 2: After the second gap is removed. In the manufacturing method of the above-mentioned flash memory device, the first control electrode and the second control electrode are not formed to form a second conductive layer that fills the opening. Then, move it on the substrate so that the surface of the second conductor layer is lower than the surface of the cover layer and the conductor layer, and ask the foreign gate. to

200412667 V. Description of the invention (6) After the third gap wall is formed on the side wall of the mask layer, a portion of the second conductor layer is removed using the mask as a mask 'to form 2 and a third gap wall to control the gate. Then, the third gap is removed. The control gate and the gate structure (tunneling dielectric layer, control gate) of the present invention are formed in the substrate, including the gate electrode, the gate dielectric region, and the source. The polar regions are formed around the top of the opening and on the hair, respectively, and the drain channel region is set in the base of the side wall of the opening (vertical and bottom base, which can accurately control the straight path type by controlling the depth of the opening ^ ^ It avoids the problems caused when the size of the element is reduced, and can increase the degree of component accumulation. Moreover, when the floating gate and the control gate are formed by this meal, the gap wall is formed on the cover layer, and then the gap is formed. The wall and the mask layer are formed by etching the mask layer and etching the conductor layer. Since no lithography technology is used, the process margin can be increased, and the process cost and process time can be saved. Because the interelectrode structure is vertical, so In the shape of the p-type well area, ϋ does not cause the problem of the so-called lateral NPN collapse, and unlike the conventional double-reverse or indirect s-membrane because of the need to form a good N pn isolation, it is necessary to mold P Well area Lateral approach (Late; fal Drive-in) β increases the range of NPN 'and affects the gate-to-gate dielectric range due to this thermal process (oxide stone nitride / nitride stone / gasified stone evening, 0N0) and tunneling Interface quality of the oxide layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the attached formula for detailed description as follows: Page 11 l〇 326twf.ptd 200412667 V. Description of the invention (7) Implementation mode: Figure 2 shows a sectional view of the structure of the flash memory of the present invention. Please refer to Figure 2, the flash memory of the present invention is composed of a p-type substrate 20Q, deep N-type well region 202, P-type well region 204, pocket doped region 204a, gate structure 206a, gate structure 206b, source region 208, drain region 21〇, a spacer 212, an insulating layer 214, a contact window 216, an inner dielectric layer 218, and a wire 220. Among them, the inter-electrode structure 206 is composed of a tunneling dielectric layer 222, a floating gate 224a, The gate dielectric layer 226 and the control gate electrode 22 仏 are formed; the gate structure 206b is composed of a tunneling dielectric layer 222, a floating gate electrode 226, and a gate dielectric layer 226 and Controlled by the gate 228b. The P-type substrate 200 has an opening 230. The deep n-type well region 202 is disposed in the p-type substrate 200. The gate structure 206a and the gate structure 206b are respectively disposed in the opening. 230 side wall. Among them, the tunneling dielectric layer 222 is disposed on the bottom of the opening 23 and the side wall. The floating gate 2 2 a and the floating gate 2 2 4 b are respectively disposed on the side wall of the opening 2 30. On the layer 222. The inter-gate dielectric layer 226 is disposed on the floating gate 2 2 4 a and the floating gate 2 2 4 b. The control gate 2 2 8 a and the control gate 2 2 8 b are disposed on the P-type On the substrate 200, the control gate electrode 228a extends to cover the side wall of the floating gate electrode 226a, and the control gate electrode 228b extends to cover the side wall of the floating gate electrode 226b. The insulating layer 214 is provided in a gap between the gate structure 206a and the gate structure 206b. The partition wall 2 1 2 3 is placed on the side walls of the control gate 2 2 6 a and the control gate 2 2 6 b. The source region 208 is disposed in the p-type substrate 2000 at the bottom of the opening 230. The drain region 210 is disposed in the p-type substrate 2000 under the spacer 212. The p-type well area 204 is disposed in the deep N-type well area 202, and the interface between the P-type well area 204 and the deep-N well area is higher than the bottom of the opening 230. P-type pocket doped region 20 "provided in the opening 200412667

In the P-type substrate 200 of the 2 30 side wall, two sides of the p-type pocket doped region 204a are respectively connected to the P-type well & 204 and the source region 208. The inner dielectric layer 218 is disposed on the P-type substrate 200. The contact window 21β is disposed in the inner dielectric layer 218, and the contact window 2 16 penetrates the junction between the drain region 21 and the p-type well region 204 to electrically connect the two together in a short circuit. The conductive line 220 is disposed on the inner dielectric layer 218 and is electrically connected to the contact window 216. In the above embodiment of the present invention, the gate structures 2 06 a and 2 06 b are disposed on the side wall of the opening 2 3 0 in the P-type substrate 200, and the drain region 2 1 0 and the source The area 2 0 8 is arranged at the top and bottom of the opening 2 30, so the channel areas 2 3 2 a and 232 b are located in the p-type substrate (vertical channel area) outside the opening 230, so the opening can be controlled by The channel length is accurately controlled in depth, which can avoid problems caused when the component size is reduced, and can increase the component integration degree. Next, please refer to FIG. 3A to FIG. 3I for a flash memory § memory process cross-sectional view of a preferred embodiment of the present invention, which is used to explain the flash memory of the present invention. Production method. First, please refer to FIG. 3A to provide a substrate 300, such as a P-type substrate 'this substrate 300 has formed an element isolation structure (not shown), and the element isolation structure is arranged in a stripe layout. And used to define the active area. The formation method of the element isolation structure is, for example, a region oxidation method (Loca i

Oxidation (LOCOS) or Shallow Trench Isolation

Isolation, ST I). Next, a deep N-type well region 302 is formed in the substrate 30q. After that, a lining layer 300 is formed on the surface of the P-shaped substrate 300. The material of the lining layer 300 is, for example, silicon oxide, and the forming method of the lining layer 300 is, for example, thermal oxygen.

200412667

The thermal oxidation method has a thickness of, for example, about 100 angstroms to 150 angstroms. Then, a cover layer 306 is formed on the liner layer 304. The material of the cover layer 306 is, for example, silicon nitride, and the formation method is, for example, Chemical Vapor Deposition (CVD). . Then, the pattern of the mask layer 306, the backing layer 304, and the substrate 300 has been formed in the substrate 300.

Please refer to FIG. 3B. A tunneling dielectric layer 3 10 is formed on the sidewall and the bottom of the opening 308. The material of the tunneling dielectric layer 3 is, for example, silicon oxide. The formation method of the tunnel dielectric layer 3 i 0 is, for example, a thermal oxidation method (Theua i Oxidation), and the thickness thereof is, for example, about 90 Angstroms to 100 Angstroms. Then, an ion implantation step is performed, and a dopant is implanted in the substrate 300 on the side wall of the opening 308, and c = pocket-doped region 3 1 2. The implanted dopant is, for example, a p-type ion, which is implanted in the chamber | to about 50 仟 electron volts, and the implantation dose is about i χ 1012 atoms / square = about λ knife. Among them, the method of implanting the dopant includes implanting the dopant at an oblique angle of 15 degrees to 30 degrees. Then, a conductive layer (not shown) that fills the opening 308 is formed at i; the material is polycrystalline silicon of wind two U. The method for forming this conductive layer is, for example, using the ^ step to form: layer i After the heteropolycrystalline stone layer, ion implantation is performed / below the substrate_surface to open: part of the conductor layer, so that its upper surface ㈣ surface is slightly lower than the bottom 30 π Ϊ into the conductor layer 314], so that the conductor layer The method of connecting the μ- / substrate 300 surface is, for example, an etch-back method. For those who are 31β, referring to FIG. 3C, a gap is formed on the side wall of the cover layer 3 06, and emulsified silicon is formed. The method of forming the partition wall 3 1 6 is, for example,

200412667 V. Description of the invention (ίο) is to first form a layer of insulating material ^ i .1 ^^^^^ # nl, ® " ^^ Gap 316. Then, using the tomb 22: the side wall of the mask layer 306 to form a bulk sound 3U, π to the curtain and the partition wall 316 as the mask etching guide = "it substrate 3". 〇Conductor layers 314a, _ on the side wall. ^ & Floating gate as flash memory. For quality planting, please refer to FIG. 3D. After removing the spacer 316, perform a blending: = clothing process on the opening, and the base 3 at the bottom 8 becomes the source region 3 1 8. Involved with> 4 cases, X 10, 5 atoms / 88% per square For example, 疋 N-type ions, the implantation dose is about 4 n n $ 8. Then, a layer of L is formed on the substrate 300. The material of the inter-gate dielectric layer 32G is, for example, oxidized stone / right, n „gasified silicon, and the thickness is, for example, 60 angstrom / M angstrom. / 60 Angstrom left: The formation method of the second layer 3 2 0 is, for example, first to form the sound i S by a thermal oxidation method, and then use low pressure chemical vapor deposition to form silicon nitride silicon dioxide. . Of course, the inter-gate dielectric layer 3 2 0 can also be an oxygen-filled silicon nitride / silicon nitride layer, etc. Then, a filling layer 2: a conductive layer 322 is formed on the substrate 300, and the material is, for example, doped. Heterocrystalline # & — The method of forming the carcass layer 322 is, for example, by chemical vapor deposition method. 4 After the undoped polycrystalline silicon layer, an ion implantation step is performed to form the electrode, and the eye is removed according to FIG. 3E. A part of the conductor layer 322 is placed on top of it. &Amp;: & is on the cover layer 306 and higher than the surface of the substrate 300 to form a conductor layer bottom 300, so that the upper surface of the conductor layer 322 is lower than the cover layer 306 and A method higher than the Gapir surface is, for example, an etch-back method. Then, the material of the cover layer 3006 / forms the spacer 3 2 6 and the material example of the spacer 3 2 6 And the conductor layer is

200412667 V. Description of the invention (11) 3 2 4 has different engraved selective sounds, complex ^^^ Λ Λ ^^ ° Γθ1 ^ 326 " Use non-isotropic last name to remove the part ^ = material layer (not (Pictured), and then the side wall of the edge is formed with a gap 4 e edge material layer 'to cover the curtain layer 3 ° 6 Mu Yin Figure 3F' with the cover layer 3 06 and the spacer 3 26 as the cover = L is formed on the base 3 Above the °, and the-ends of the conductor layers 324a, 324b of the side walls of the body layers 314a, 314b, respectively, are used as flash memory: = 4b :: layer 324a, inter-gate dielectric layer 32, conductor = A,, medium The V body has an inter-electrode structure 325a; the conductor layer 324b, the second layer 41, the dental dielectric layer 310, and the dielectric layers 31G constitute the gate structure 3 plus. Then, the wall 326, the cover layer 306, and the liner 3G4. The method of removing the crevice wall and the mask layer and the lining layer 304 is, for example, a wet etching method. After that: a J-quality implantation process' implants a bead in a substrate 300 around the top of the opening 308 to form a drain region 328. The implanted dopant is, for example, an N-type off-center dose of about 4 × 10 15 atoms / cm 2. The plant is then "refer to Fig. 3G" in the inner well 330 in the well area 302. Forming a P-well region 33. The method is, for example, an ion implantation method, and the dosage is about 1 × 10 13 atoms / cm 2. Then, the gap between the conductor sounds 324a and 324b forms an insulating layer 332, and a gap wall 33 is formed on the side wall of the conductor 324a / 24b. The method of forming the gap wall is, for example, forming a layer of insulating material on the substrate 300 Layer (removing part of the insulating material layer after iron by using anisotropic method), the side walls of the body sounds 324a, 324b form a partition wall 334, and the insulating material layer = true / 10326t.wf.ptd page 16 200412667

V. Description of the invention (12) The gap between the body layer 3 2 4 a and 3 2 4 b forms the insulating layer 3 3 2. Next, referring to FIG. 3H, an inner dielectric layer 336 is formed on the substrate 300. The material of the inner dielectric layer 336 is, for example, borophosphite / glass (BPSG) or phosphosilicate glass (PSG) to form an inner layer. The method of the dielectric layer 336 is, for example, a chemical vapor deposition method. Then, a chemical mechanical polishing process is performed to planarize the surface of the inner dielectric layer 340. Next, a contact window 338 is formed in the inner dielectric layer 336, and the material of the contact window 338 is, for example, tungsten metal. The contact window 338 penetrates the junction between the drain region 328 and the P-type well region 330, and short-circuits the drain region 328 and the P-type well region 330. After that, open the inner dielectric layer 3 3 6 > to form a wire 3 4 0 electrically connected to the contact window 3 3 8. The method of forming the conductive wire 3 4 0 is, for example, forming a conductive layer (not shown) on the substrate 30 and then performing a lithography step to form a strip-shaped conductive wire 34. Subsequent completion of the process of flashing the alpha memory is well known to those skilled in the art, and will not be repeated here. The gate structures 325a and 325b of the present invention are formed on the side wall of the opening 308 in the substrate 300, and the drain region 328 and the source region 318 are formed on the substrate 3 around the top and bottom of the opening 308. 〇, so its channel area is located on the base 3 outside the opening 308 (vertical channel area), so you can increase the degree of component accumulation 'and can accurately control the return length by controlling the depth of the opening' Furthermore, it is possible to avoid problems caused when the component size is reduced. In addition, the invention uses the present invention to form floating gate electrodes (conductor layers 314a, 314b), and to form a partition wall 316 on the cover layer 306, and then the partition wall 3 1 6 and the cover layer 3 0 6 is an etching mask formed by etching the conductive layer 3 1 4. Since no lithography technology is used, the process margin can be increased 'and the process cost and process time can be saved. Similarly, the present invention is

200412667 V. Description of the invention (13) When forming the control gate (conductor layers 324a, 324b), the spacer wall 326 is formed on the cover layer 306, and then the spacer wall 326 and the cover layer 306 are used as the etching cover. It is formed by etching the conductor layer 3 2 4. Since no lithography technology is used, the process margin can be increased, and the cost and process time can be reduced. In addition, since the gate structure of the present invention is in a vertical direction, the problem of so-called lateral swelling 1 ^ collapse does not occur in the shape of the Yubi area, and the dual-reverse or gate-type memory cells of Dong Erzhi Because it is necessary to form a good foot barrier to handle the "Lateral Drive_in" layer (the oxidation ^ ΛΙΛ), and affect the inter-gate dielectric wide cut due to this thermal process / The interface of the mouse cut / oxygen cut and the oxide layer is wide = the invention has been disclosed as above with a preferred embodiment. Iron 1 is not intended to limit the invention. Anyone familiar with this technique ^ within the scope and scope of its Asian and African uses, When you can make all kinds of changes ^ No, leave the scope of the present invention as the scope of the attached patent == the guarantee of the present invention 10326t.wf.ptd page 18 200412667 Schematic illustration of the first picture It is a structural cross-sectional view of a conventional flash memory. FIG. 2 illustrates a structural cross-sectional view of a flash memory according to a preferred embodiment of the present invention. FIGS. 3A to 3H are diagrams according to the present invention. A perspective view of a flash memory manufacturing process in a preferred embodiment. : 100, 2 0 0, 3 0 0: p-type bases 102, 202, 302: deep η-type well area 104, 204, 330: ρ-type well area 1 0 6: stacked gate structure 1 0 8, 2 0 8 3 1 8 Source regions 110, 210, 328: Drain region 1 1 2, 2 1 2, 3 1 6, 3 2 6, 3 3 4: Spacer walls 114, 218, 336 · Internal dielectric Layers 1 6, 2 1 6, 3 3 8: contact windows 118, 2 2 0, 3 4 0: wires 120, 222, 310 · tunneling dielectric layers 122, 224a, 224b: floating gates 124, 22 6, 3 2 0: Gate dielectric layers 126, 228a, 228b: Control gates 1 2 8, 2 3 2, 3 1 6: Gate top caps 2 0 6a, 2 0 6b > 32 5a > 3 2 5b: Gate structure 2 1 4, 3 3 2: Insulation layer 230, 308: Opening

10326twf.ptd Page 19 200412667 Brief description of the drawings 232a, 232b: Channel area 3 0 4: General layer 3 0 6: Mask layer 312, 2 04a: Pocket doped area 314 > 314a > 314b, 322, 324a 324b: Conductor layer

10326twf, ptd Page 20

Claims (1)

200412667 VI. Scope of patent application 1. A structure of a flash memory device includes: a first conductive type substrate having an opening; a second conductive type first well region provided in the first conductive type substrate; In a conductive substrate; a first gate structure and a second gate structure are respectively disposed on the side wall of the opening; an insulating layer is disposed between the first gate structure and the second gate structure A gap; a source region disposed in the first conductive type substrate at the bottom of the opening; a drain region disposed in the first conductive type substrate at the top of the opening; a first conductive type second well region, Disposed in the second conductive type first well region, and the interface between the first conductive type second well region and the second conductive type first well region is higher than the bottom of the opening; and a first conductive type pocket is mixed with The impurity region is disposed in the first conductive type substrate on the side wall of the opening, and the first conductive type pocket doped region connects the first conductive type second well region and the source region. 2. The structure of the flash memory device according to item 1 of the scope of patent application, wherein the first gate structure and the second gate structure include: a tunneling dielectric layer disposed on a side wall of the opening; A first floating gate and a second floating gate are respectively disposed on the tunneling dielectric layer on the side wall of the opening; an inter-gate dielectric layer is disposed on the first floating gate and the first floating gate. Two floating 10326t.wf.ptd Page 21 6. Scope of patent application On the gate; and the control gates are respectively arranged on the floating gate and the second floating 2 7 第二 π gate side wall. 3. If the scope of patent application is the first one, in which the first conductively mounted and described flash memory element is completed 4. If the patent is applied for; Bottom package correcting base. Wherein, the flash memory element described in the second conductive type S_ item 5. As described in the patent application range, a well area includes a deep N-type well area. ′ Wherein the flash memory device described in the first conductive item 6. If applying for a special brake ^ The second well area includes a P-type well area. Wherein, the structure of the flash memory element described in the source region ^^ 1 item 7. As described in the patent application scope, the 1-pole region is doped with fine ions. The drain region is connected with the flash memory device circuit described in the item. The first conductive type and the second well type are electrically short. The second conductive type is the junction conductive type of the flash memory element described in item 7. The pen-short circuit is formed through a contact window. The interface between the nonpolar region and the first 9. = 2ί interval. The structure of the flash memory device described in item 1 of the 青 t " green patent range, and τ further includes: a bottom j. An inner dielectric layer, the inner dielectric layer being disposed on the first conductive type base, And a window electrical line, the wire is disposed on the inner dielectric layer and is connected to the contact. 1 0 Ln. • The flash memory device described in the second item of patent scope 200412667 6. The scope of patent application, in which the material of the inter-gate dielectric layer includes silicon oxide / silicon nitride / stone oxide. 1 1. A structure of a flash memory device, comprising: a first conductive type substrate having an opening; a second conductive type first well region disposed in the first conductive type substrate A tunneling dielectric layer disposed on the bottom and sidewall of the opening; a first floating gate and a second floating gate respectively disposed on the tunneling dielectric layer on the sidewall of the opening; An inter-gate dielectric layer is disposed on the first floating gate and the second floating gate; a first control gate and a second control gate are disposed on the substrate, and the first control gate Electrode extension covers the side wall of the first floating gate, and the second control gate extends to cover the side wall of the second floating gate; an insulating layer is provided on the first control gate and the second control gate; A gap between the gates; a gap wall provided on a side wall of the first control gate and the second control gate; a source region provided in the first conductive type substrate at the bottom of the opening; a drain A polar region disposed in the first conductive type substrate below the gap wall; A second conductivity type well region, disposed on the second conductive type first well region and the first conductivity type and a second well region of the second conductivity type first well region 10326t.wf.ptd Page 23 200412667 6. The junction of the scope of patent application is higher than the bottom of the opening; and a first conductivity type pocket doped region is not placed in the first conductivity type substrate of the side wall of the opening, And the first conductive pear pocket doped region connects the first conductive type second well region and the source region. 1 2 · The structure of the flash memory device according to item 11 of the scope of patent application, wherein the drain region and the first conductive type second well region are connected together by an electrical short circuit. 1 3 · The structure of a flash memory device as described in item 12 of the scope of the patent application, wherein the electrical short circuit passes through the interface between the drain region and a conductive type second well region with a contact window. Brother 1 4 · According to the nth structure in the scope of patent application, which further includes: one of the flash memory elements described in item 11, an inner dielectric layer on the bottom of the chip; and 9 layers are provided on the The first conductive type base is a wire, and the wire is electrically connected to the sash window. The Λ layer dielectric layer is in contact with the 15. Such as the structure of the patent application No. u structure, wherein the inter-gate dielectric layer; silicon of the L flash memory element. The material includes silicon oxide / silicon nitride / oxide 1 6 · — a series of flash memory device steps: a method of fabricating, the method includes providing a first well type with a first conductivity type and a second conductivity type first well area; < Bottom, the substrate has been formed in sequence-a sequential formation on the substrate-a layer of Λ and a cover layer; 200412667 VI. Application for patent patterning the cover layer, the liner layer and the substrate to form an opening in the substrate; forming the opening in the opening to form a tunneling dielectric layer; in the substrate on the side wall Forming a conductive pocket type doped region on the sidewall of the opening to form a first floating gate and a second floating gate on the opening to form a source region at the bottom of the opening; A gate-shaped dielectric layer; a sidewall-shaped electrode, and the first control gate electrode extending to cover the second control gate to remove the cover in the substrate curtain layer, and the conductive conductive port bottom to the first control insulating layer, and In the first gap wall; in the second area, and the first junction southward extends from the first control gate to a second control gate to cover a side wall of a floating gate, covering the The side wall of the second floating gate; and the lining layer; forming a source region; the first part of the pattern; the first well of the gate and the second well of the first conductivity type and the second conductivity type Gap between a well area and the second control gate Forming a first dielectric layer on the substrate ~ on the inner dielectric region and the first conductivity type on the inner dielectric layer of the inner dielectric control gate and the sidewall of the first gate; forming a first dielectric layer; Contact window, 哕 技 # 3 contact_forms a short failure of the open drain region to form a connection with the contact; and 10326t.wf.ptd Page 25 200412667 6. Scope of Patent Application Line. 17. The method for manufacturing a flash memory device as described in item 16 of the scope of patent application, wherein the method of forming the first conductive type pocket doped region in the substrate on the side wall of the opening includes an inclined angle ion Implantation. 1 8. The method for manufacturing a flash memory device according to item 16 of the scope of the patent application, wherein the step of forming the first floating gate and the second floating gate on the sidewall of the opening includes: Forming a first conductor layer on the substrate, and the first conductor layer filling the opening; removing part of the first conductor layer, so that the surface of the first conductor layer is slightly lower than the surface of the substrate; on the cover A second gap wall is formed on the sidewall of the curtain layer; using the mask curtain layer and the gap wall as a mask, removing a portion of the first conductor layer; and removing the second gap wall. 19. The method for manufacturing a flash memory device according to item 16 of the scope of patent application, wherein the step of forming the first control gate and the second control gate on a sidewall of the opening includes: A second conductor layer is formed on the substrate, and the second conductor layer fills the opening; a part of the second conductor layer is removed, so that the surface of the second conductor layer is lower than the surface of the cover layer and south of the floating layer A gate electrode; forming a third gap wall on a side wall of the cover layer; using the cover layer and the third gap wall as a cover screen, removing a part of the second 10326twf.ptd Page 26 200412667 6. Patent application scope Conductor layer; and Remove the third spacer. 20. The method for manufacturing a flash memory device according to item 16 of the scope of the patent application, wherein the insulating layer is formed in a gap between the first control gate and the second control gate, and the The step of forming the first gap wall between the first control gate and the side wall of the second control gate includes forming an insulating material layer on the substrate, and the insulating material layer fills the first control gate and the first control gate. Controlling the gap between the gates; and removing part of the insulating material layer by anisotropic etching. 10326twf.ptd Page 27