TW200412658A - Integrated circuit package structure with heat dissipation design - Google Patents

Integrated circuit package structure with heat dissipation design Download PDF

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TW200412658A
TW200412658A TW92100792A TW92100792A TW200412658A TW 200412658 A TW200412658 A TW 200412658A TW 92100792 A TW92100792 A TW 92100792A TW 92100792 A TW92100792 A TW 92100792A TW 200412658 A TW200412658 A TW 200412658A
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package structure
integrated circuit
chip
scope
item
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TW92100792A
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TWI289918B (en
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Nai-Shung Chang
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Via Tech Inc
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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Description

200412658
五、發明說明（1) 發明所屬之技術領域 本案係有關於一種積體電路晶片 ^ 具有散熱佈線設計之積體電路晶片封努f結構’尤指一種 表·結構。 先前技術 於積體電路的 口 aa 片，在完成半導體製程之後，將!^曰二；L製造多個半導 粒（d i e )從晶圓上切割下來，而每一、^曰各半導體晶片之晶 體元件。在取得晶粒之後，必須進行4 '為一個半導 得晶粒上之半導體元件能夠在封I = 〃 ^裝製程，使 裝製程包含：準備一封裝基板===運作，此封 接之導電線路；然後，將晶粒固定於封^ ^晶粒作電連 般封裝結構則以打線製程連接半導體元；：匕其f為： 為覆晶封裝結構，則以金屬墊連接株^板，右 板；最後，進行整體的包裝過程，以：件=裝基 裝基板之上。而於積體電路的封裝製 凡== :計係根據半導體元件所需要的電氣特性或散== 。月4見第一圖，其係一核心邏輯晶片 二=用構造示意圖，…心邏輯晶。== I二11 μ 、亡表面，而核心邏輯晶片1 〇經由焊線1 2連接至 " 之信號輸出入接線墊（Pad)，信號輸出入接線墊
第5頁 200412658 五、發明說明（2) 然而，因為 經由透孔1 3連接基板11下表面之球狀接腳1 4 晶片1 0之電源接線數量眾多，因此基板11上方係設有一電 源環結構（power ring) 15，而多條電源接線16便連接至該 電源環1 5之上，至於該電源環1 5則再透過多個透孔1 7與下 方之球狀接腳1 8完成電性連接。而基板11周圍與上方則設 置有一塑料外蓋1 9用來保護核心邏輯晶片丨〇本身。而核心 邏輯晶片1 0經由焊線1 2或電源接線1 6連接至封裝基板11之 信號輸出入接線墊或電源環結構，然後經由透孔丨4、丨7之 中的金屬栓塞連接球狀接腳丨4、1 8，然後電連接於主機板 20，核心邏輯晶片1〇可經由此一封裝結構與電路板2〇上之 其它電路元件完成電性連接。 於第一圖所顯示之積體電路封裝結構，在封裝基板Η 上設置電源環結構，而且此電源環結構係設置於半導體晶 種結構設計係為便於在半導體晶片與電源環 :構導線接線製程與簡化封裝基板上之導線設 汁一疋，在封裝基板上的一側設置電源環社媒，腺奋士 吊連作過転中，電源環結構將會因 相，甚曰β壯* t ^ 1々丨l遇人里電流而發 心右疋封凌基板的散熱效應較差啖去s道# . 蔣合因昝少私壯#上 a者疋導熱效應較差， 將㈢因此在封裝基板上產生熱應力導致 者疋因封裝基板的溫度過高導致半又=丑，多 作。 千導體晶片無法正常運 因此’散熱效率一直是半導體晶 尤其在操作速率快且積隼度高衣仏之重要課題， 檟杲度间之核心邏輯晶片上，若晶片
第6頁 200412658 五、發明說明（3) 之散熱效率不佳，則故障產生之機率將增加很多。但是， 在上述核心邏輯晶片之封裝結構與設置於主機板上之方 式’核心邏輯晶片係經由金屬焊線與封裝基板作電連接， 而核心邏輯晶片係以底部連接封裝基板，而封裝基板係以 球狀焊塾連接於主機板，皆無法有效達成散熱之實際需 求，而如何改善上述技術手段之缺失，係為發展本案之主 要目的。 發明内容
本發明係揭4 一種具有散熱佈線設計之積體電路晶片 封裝結構，在一封裝基板上放置積體電路晶片，在積體電 路晶片的周圍設置電源環結構，於靠近積體電路晶片之高 熱能區域，電源環結構具有較大的表面積，使得其與封裝 基板之間具有較大的接觸面積，以增進散熱效能。 义 本發明係揭露一種具有散熱佈線設計之積體電路晶片封裝 結構，增加電源環結構與封裝基板之間的接觸面積，使得 封裝基板經由電源環結構傳遞熱能至多層電路板之上， 增進散熱效能。
晶片 ，增 封裝 路晶 本發明係揭露一種具有散熱佈線設計之積體電路 封裝結構，利用封裝基板與電腦主機板之電連接通路 加電連接通路的接觸面積，以增進散熱效能。 ^ ^明係揭露一種具有散熱佈線設計之積體電路晶片 、、口構，利用散熱金屬外蓋保護在封裝基板上的積體電
第7頁 200412658
片’以增進散熱效能。 根據上述構想，本案所述之晶片封裝結構，其中該電 源％係由複數個互不相連之區塊組成，而在於該晶片產生 熱能較多之區域周緣之區塊表面積係大於其它區塊之表面 簡單圖式說明 本案得藉由下列圖式及詳細說明，俾得一更深入之了 解： 第圖·其係一核心邏輯晶片封裝與設置於主機板上之習 用構造示意圖。 $二圖：其係本案所發展出來之具有散熱佈線設計之積體 電路封裝結構之較佳實施例的上視示意圖。 ^ 了圖·其係本案所發展出來之具有散熱佈線設計之積體 “路封聚結構之側視剖面示意圖。 核心邏輯晶片1 〇 本案圖式中所包含之各元件列示如下： 基板11 透孔13 電源環結構15 透孔17 塑料外蓋1 9 晶片3 0 信號接線1 2 球狀接腳1 4 電源接線16 球狀接腳1 8 主機板2 0
200412658 五、發明說明（5) 基板31 區塊321、322 透孔3 7 外蓋3 9 主機板40 等電位導電層42 電源環32 電源接線3 6 球狀接腳3 8 散熱金屬上蓋391 透孔41 貫施方式 本發明係揭露一種具有散熱佈線設計之積體電路封裝 結構’凊參見第二圖，其係本發明所發展出來之晶片封裝 散熱結構之較佳實施例構造上視示意圖，其中晶片30係置 放於基板31之上方，而電源環32係由複數個區塊32ι、322 所組成，而為能有效增強散熱功能，本案便在晶片3〇產生 熱能較多之區域（本例中係晶片之左下區域為產熱較多之 區域）周緣之區塊321表面積係大於其它區塊322之表面 斧貝 如此來’原本溫度較南之晶片左下區域將可有效散 熱而維持在較佳之工作溫度。 另外，在請參見第三圖，其係本案所發展出來之晶片 封裝散熱結構之較佳實施例構造側視剖面示意圖，其中晶 片30係置放於基板31之上方，而晶片3〇上之多條電源接線 36連接至電源環（power ring)32之上，至於該電源環32則 再還過多個透孔3 7中之金屬栓塞與下方之球狀接腳38完成 電性連接’而透過球狀接腳38與主機板4〇之電性接觸，晶
第9頁 200412658 五、發明說明（6) =30便可與電路板4〇上之其它電 為了能改善晶η十必义丄处丄 丨卞凡风电r生運接。而 宴39中以A s片政熱功月匕，本案在用來保護晶片30之外 ‘，如此例如銘等金屬）來完成一散熱金屬上蓋 散熱效率。將可有效增加晶片及其封裝結構整體之 構之雷此增加散熱面積，本案更加透過具有多層結 组二ψ #曾上之透孔41的金屬栓塞，進而將球狀接腳38 地I完成遠路技板40中之等電位導電層42(可為電源層或接 導二Μ、隹成連接，進而使該晶片可利用該等大面積之電位 Π Ϊ:散熱。於本發明之一較佳實施例之中，電路板 係為=層電路板，具有一等電位導電層， = 一般電腦主機板。 』馮 丄因&此-，基板Μ經由圍繞於晶片30周圍的電源環結構 ^ α二一圖所不），在晶片3 0產生熱能較多區域（例如為 弟一圖所不之晶片左下角區域），電源環結構Mi (如第二 圖戶/!不）具有較大的表面積，以增加基板3 1與電源環結構 的接觸面積，而電源環結構係經由透孔41中的金屬栓塞 接至球狀接腳38，在連接至電路板4〇之等電位導電層 42(如第三圖所示），以增強基板31的散熱效能。換言之， 在晶片周圍區域增加電源環結構的表面積，以增加電 結構與封裝基板之間的接觸面積，將可經由電路板之等 位導電層加強封裝基板的散熱效能。 ％ 综上所述，本案改變習用晶片封裝結構並利用下方 路板之特殊結構來改善散熱效率，進而有效解決習用手段
第10頁 200412658 五、發明說明（7) 之缺失，而本案之晶片可為一核心邏輯晶片（core logic ch i :p )，而該多層電路板則為一電腦主機板，但本案技術 手段可被應用至其它相類似之晶片封裝結構上，故本案發 明得由熟習此技藝之人士任施匠思而為諸般修飾，然皆不 脫如附申請專利範圍所欲保護者。 參
第11頁 200412658 圖式簡單說明 第一圖：其係一核心邏輯晶片封裝與設置於主機板上之習 用構造示意圖。 第二圖：其係本案所發展出來之具有散熱佈線設計之積體 電路封裝結構之較佳實施例的上視示意圖。 第三圖：其係本案所發展出來之具有散熱佈線設計之積體 電路封裝結構之侧視剖面示意圖。
第12頁

Claims (1)

  1. 200412658 六、申請專利範圍 1 · 一種積體電路晶片之封裝結構，該封裝結構至少包 含： 一基 複數 一電 四周 成電 塞而 積體 其它 申請 複數 生熱 表面 申請 晶片 申請 電路 路晶 申請 蓋的 申請 片為 申請 板， 個球 源環 ，其 性連 與該 電路 區域 專利 個互 能較 積。 專利 係為 專利 晶片 片與 專利 材質 專利 一核 專利 片之 片完 屬栓 於該 於在 2.如 係由 片產 塊之 3 ·如 之該 4 ·如 積體 體電 5 ·如 屬上 6 .如 路晶 7.如 其第一表面係供該積體電路晶片置放； 狀接腳，設置於該基板之第二面；以及 ，設置於該基板之該第一表面並圍繞該晶 中該電源環係透過複數根電源接線與該晶 接，另一端係經由穿過該基板之複數個金 等球狀接腳達成電性連接，而該電源環在 晶片產生熱能較多之區域周圍之表面積大 之表面積。 範圍第1項所述之封裝結構，其中該電源環 不相連之區塊組成’而在於該積體電路晶 多之區域周緣之區塊表面積係大於其它區 範圍第1項所述之封裝結構，其所應用其上 一核心邏輯晶片。 範圍第1項所述之封裝結構.，於該基板與該 之上方覆蓋一散熱金屬上蓋，以保護該積 加強該積體電路晶片的散熱效果。 範圍第4項所述之封裝結構，其中該散熱金 為鋁金屬。 範圍第1項所述之封裝結構，其中該積體電 心缝輯晶片。 範圍第1項所述之封裝結構，其中該基板係
    第13頁 200412658 六、申請專利範圍 應由該球狀接腳與一多層電路板進行電連接。 8 ·如申請專利範圍第7項所述之封裝結構，其中該多層電 路板具有一等電位導電層與複數個透孔，而該球狀接腳 係透過該複數個透孔，而該多層電路板中之一等電位導 電層完成電性連接，進而使該積體電路晶片可利用該等 電位導電層進行散熱。 9 ·如申請專利範圍第8項所述之封裝結構，其中該等電位 導電層係為一電源層或一接地層。 1 0.如申請專利範圍第7項所述之封裝結構，其中該多層 電路板係為一電腦主機板。 1 1 · 一種積體電路晶片之封裝結構，該封裝結構至少包 含： 一基板，其第一面係供該積體電路晶片置放； 複數個接腳，設置於該基板之第二面；以及 一散熱金屬上蓋，設置於該晶片上方，其第一面係 朝向該積體電路晶片，而與該積體電路晶片間僅具有一 空間，而其第二面則接觸外界空氣，進而達成散熱之功 效。 1 2 .如申請專利範圍第1 1項所述之封裝結構，其中該散熱 金屬上蓋之材質係為銘金屬。 1 3.如申請專利範圍第1 1項所述之封裝結構，其所應用其 上之該晶片係為一核心邏輯晶片。 1 4.如申請專利範圍第1 1項之封裝結構，其中該基板具有 複數個電源環結構圍繞於該積體電路晶片的周圍，而該
    第14頁 200412658 六、申請專利範圍 電源環結構在靠近該積體電路晶片產生熱能較多的區域 具有比其他區域更大的表面積，以增強該基板與該積體 — 電路晶片的散熱效能。 1 5 ·如申請專利範圍第1 1項之封裝結構，其中該基板係透 過該複數個接腳電連接一多層電路板。 16.如申請專利範圍第15項之封裝結構，其中該多層電路 板具有一等電位導電層與複數個透孔，而該等接腳係透 過該等透孔而與該等電位導電層完成電性連接，進而使 該積體電路晶片可利用該等電位導電層進行散熱。 1 7 ·如申請專利範圍第1 6項之封裝結構，其中談等電位導 電層係為一電源層或一接地層。 1 8 ·如申請專利範圍第1 5項之封裝結構，其中該多層電路 板係為一電腦主機板。 19.如申請專利範圍第11項之封裝結構，其中該積體電路 晶片係為一核心邏輯晶片。
    第15頁
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