TW200410325A - Method for manufacturing gate - Google Patents

Abstract

A method for manufacturing a gate is described. A gate oxide layer, a gate conductive layer and a sacrificial layer are subsequently formed on a semiconductor substrate first. After patterning the sacrificial layer, the sacrificial layer and the gate conductive layer are etched to completely remove the sacrificial layer and form a polymer layer alongside the sacrificial layer before etching. Thereafter, the gate conductive layer uncovered by the polymer layer is removed. Finally, the gate oxide layer uncovered by the gate conductive layer is removed. When etching the sacrificial layer and the gate conductive layer, the thickness of the formed polymer layer is controlled by changing the injected amount of the oxygen gas. The different line width of the gate can be defined according to different thickness of the formed polymer layer.

Description

200410325 V. Description of the invention (1)-'Technical field to which the invention belongs: The present invention relates to a method for manufacturing a gate, in particular to a method for manufacturing a gate with a line width smaller than the exposure resolution capability. Prior technology: The semiconductor process uses a lithography process and an etching technique to define a layer of line width. It first covers a photoresist layer with a patterned mask, and then performs exposure. After the photoresist layer is developed, Then the patterned photoresist layer is used as a mask to etch the lower layer. After the pattern is transferred to this layer, the photoresist is removed. However, in order to improve the accumulation and product speed, the semiconductor process has continued to evolve toward a trend of shrinking line widths. However, the level of line width is mainly determined by the resolution capability of the exposure machine. For example, in terms of current process capabilities, the exposure machine The resolution is only about 0.1 mm, and the defined line width is only about 0.1 mm. Even when using ultraviolet light with a short exposure wavelength (193nm or 157nm), the improved resolution is still limited. Conventional technologies have developed several methods to solve this problem, such as using a phase shift mask (PSM) to improve the resolution, or changing a light source with a shorter exposure wavelength, such as X-ray, for exposure. Other methods have been able to improve the resolution of the exposure machine. The resolution of these methods is also limited, and additional equipment needs to be added.

200410325 V. Description of the Invention (2) US Patent No. US 6,110,837 proposes a method for manufacturing a gate with a line width smaller than the exposure resolution capability (as shown in Figures 1A to 1H). First, in FIG. 1A, a gate oxide layer 11, a polycrystalline silicon layer 12, a polysilicon stop layer 13, and another polycrystalline silicon layer 14 are sequentially formed over a silicon substrate 10. The material of the etch stop layer 13 may be silicon dioxide, silicon nitride, or silicon oxynitride. In FIG. 1B, a polycrystalline silicon layer 1 * is patterned by a lithography process and an etching technique. In FIG. 1C, a masking layer 5 is deposited on the surface of the polycrystalline silicon layer 4 and the etch stop layer 13. The material of the shielding layer η may be silicon dioxide, nitride nitride or oxynitride. In FIG. 1D, a comprehensive etching is performed to form a spacer 16 on the side wall of the polycrystalline silicon layer 1 *. The thickness of the spacer 16 can be determined by the thickness of the shielding layer 15 in FIG. 1c. / In the figure 1E, the polycrystalline silicon layer is removed by etching. At this time, the spacer wall is used as a hard mask for subsequent gate etching. The thickness of the spacer wall can determine the gate line formed in the subsequent process. width. As shown in FIG. 1F, the polycrystalline silicon layer 12 and the polycrystalline silicon layer 12 are not covered by the spacer 16 by etching. Township X ", and stop layer Next, in the first G diagram, the spacers 6 and the etch stop layer 3 are removed. 200410325 V. Description of the invention (3) ~ Finally, in the first picture, the gate oxide layer 11 ′ which is not covered by the polycrystalline silicon layer i 2 is removed by etching to complete the fabrication of the gate electrode. US6, 1 10, 8 37 has proposed a method for manufacturing a gate with a line width smaller than the exposure resolution capability. However, its manufacturing process is still complicated, which not only increases the manufacturing cost, but also reduces the production capacity of semiconductor products. The lack of conventional technology can be seen from this. . SUMMARY OF THE INVENTION In view of the lack of conventional technology, the object of the present invention is to provide a method for manufacturing a gate electrode, so that the line width of the gate electrode is smaller than the exposure resolution capability. Another object of the present invention is to provide a gate manufacturing method for simplifying the gate manufacturing process. Another object of the present invention is to provide a method for manufacturing a gate electrode for improving the productivity of a semiconductor product. According to the above object, an aspect of the present invention provides a method for manufacturing a gate electrode. This manufacturing method firstly opens a gate dielectric layer, a gate conductor layer, and a sacrificial layer over a semiconductor substrate in order. Then, the sacrificial layer is patterned, and then the sacrificial layer and the gate conductor layer are etched to be completely removed. Sacrificial layer, and a polymer layer is formed on the sidewall before the sacrificial layer is etched, and then the polymer is removed

Page 10 200410325 The gate conductor layer covered by the layer, except for the gate dielectric layer covered by the polymer electrode conductor layer. According to the above purpose, the method of another aspect of the present invention is applied to the manufacture of a semiconductor substrate, and a mask dielectric layer is formed on the bottom surface, and a gate base is patterned. Sacrifice layer, Rand drill f body layer and-sacrificial layer. Layer 'to completely remove the sacrificial layer and shape: ―tj sacrificial layer and the side wall in front of the gate conductor. The knife layer is etched on the sacrificial layer. The present invention includes a fluorine-containing component gas and a slurry gas to etch the sacrificial layer and the gate conductor layer. One of the electrodes CF4, CxFy and CxHyFz or any of them is divided into: The flow rate of He02 can be used to control the formed polymer mouth gas, and the thickness of oxygen or thickness can be used to determine the thickness of different sublayers and different polymer layers. Implementation: Reference: i2A ~ 2F1. Structure> Claw column can not bear the figure. First, as shown in FIG. 2A, a gate oxide layer 21, a gate conductor layer 22, and a sacrificial layer 23 are sequentially formed over a silicon substrate 20. Among them, the gate

200410325 V. Description of the invention (5) The material of the conductor layer 22 may be polycrystalline silicon, and the material of the sacrificial layer may be silicon, silicon nitride or silicon oxynitride. The thickness of the gate oxide layer 21 is between 10 and 30A. The gate conductor layer The thickness of 22 is between 500 and 2000A, and the thickness is between 100 and 100A. In the layer Zd, FIG. 2B, the sacrifice layer 23 is patterned by a lithography process and an etching technique.

In FIG. 2C, the sacrificial layer 23 and the gate body layer 22 are etched with a fluorine-containing component (Huolline-based) gas and an oxygen gas or one of He02 plasma gas, and the sidewalls of the sacrificial layer 23 are etched during the etching process. A south molecular layer 24 is gradually formed. The etching selectivity of the gate conductor layer 22 relative to the sacrificial layer 23 is between 0.5 and 5; the fluorine-containing component gas may be CF4, CxFy, CxHyFz, or a mixture of any two or more thereof. When the etching is continued, the sacrificial layer 23 ′ can be completely removed and another polymer layer 25 ′ can be gradually formed on the inner wall of the polymer layer 24. Wait until the bottom of the formed polymer layer 25 is approximately aligned with the bottom of the polymer layer 24. At this time, the etching is stopped (as shown in FIG. 2D), and the remaining thickness of the gate conductor layer 22 is about 700A. During the etching, the thickness of the polymer layers 24 and 25 can be controlled by the flow of oxygen or He02. Different thicknesses of the polymer layers 24 and 25 can determine different gate line widths formed in the subsequent processes. In Fig. 2E, the gate conductor layer 22 not covered by the polymer layers 24 and 25 is removed by an etching technique. In Figure 2F, the polymer layers 24 and 25 are first removed by a dry etching technique, and then

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Then, one surface of the gate conductor layer 22 is cleaned by a wet etching technique, and the non-gate conductor layer is removed by the etch technique to complete the fabrication of the gate electrode. Finally, as shown in FIG. 2G, the gate oxide layer 22 is covered by 21. Conventional technology US6, 1 1 0, 837 deposits an additional stop layer 13 and a polycrystalline silicon layer 14 compared to the earlier process (FIG. 1A) In FIG. 1B, the polycrystalline silicon layer 14 is first patterned, and in FIG. 1C, a masking layer 15 is deposited, and then the etching is performed in the figure. Therefore, the wafer must wait between the deposition machine and the etching machine. The process is complicated and reduced. Semiconductor product capacity. In contrast, the present invention only deposits one additional sacrificial layer 23 (Figure 2A) compared to the earlier process, and Figures 2B to 2G are etched on the same etching machine. Therefore, the process of the present invention is simpler than 1136,11,837, and can be Increase semiconductor product capacity. ’In the present invention, the sacrificial layer 23 and the gate conductor layer 22 are formed in the remaining time (FIG. 2 (: ~ 21))

The thickness of the polymer layers 24 and 25 can be controlled by changing the flow rate of oxygen or He02. The thinner the polymer layer, the narrower the gate line width can be defined. The technology of the present invention can define a gate of about 0.02 mm Polar line width. X As understood by those familiar with this technology, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below.

200410325 The diagram simply illustrates the preferred embodiment of the present invention in the foregoing explanatory text supplemented by the following figures for more detailed explanation, in which: Figures 1A ~ 1 The figure is a schematic diagram showing the cross-sectional structure of a gate electrode made by conventional techniques ; And FIGS. 2A to 2G are schematic diagrams showing a cross-sectional structure flow for manufacturing a gate electrode according to the present invention.

Description of drawing numbers: 10 silicon substrate 11 gate oxide layer 1 2 polycrystalline silicon layer 1 3 etch stop layer 1 4 polycrystalline silicon layer 1 5 shielding layer 16 gap wall

20 Silicon substrate 21 Gate oxide layer 22 Gate conductor layer 23 Sacrificial layer 24 Polymer layer 25 Polymer layer

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Claims (1)

200410325 VI. Scope of patent application 1 · A method for manufacturing a gate, the manufacturing method includes at least the following steps: · sequentially forming a gate dielectric layer, a gate conductor layer and a sacrificial layer over a semiconductor substrate; & lt ~ Pattern the sacrificial layer; sacrifice the sacrificial layer and the gate conductor layer to completely remove the sacrificial layer and form a polymer layer at the sidewall of the sacrificial layer before etching; 9 remove the polymer that is not Layer covering the gate conductor layer; removing the polymer layer; and removing the gate dielectric layer not covered by the gate conductor layer. L is the method for manufacturing the gate electrode according to the first patent application range, wherein the material of the semiconductor substrate is silicon. Shoubat declares the gate electrode manufacturing method of item 1 of the patent scope, wherein the gate electrode; the thickness of the electrical layer is between 10 ~ 30A. The manufacturing method of the gate electrode of the first patent scope of the Mu brand 1 Ming, wherein the material of the gate conductor layer is polycrystalline silicon. The method for manufacturing a gate electrode according to item 1 of the patent application, wherein the thickness of the gate conductor layer is between 500 and 2000 A. The second layer is a patent, the gate manufacturing method of item 1, wherein the sacrifice is selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. 1 ^ 1 p. 15 200410325 7. The gate electrode manufacturing method as described in the first item of the patent application, the thickness of the layer is between 100 and 1000 A. / 、 The sacrifice 8 • If the gate electrode manufacturing method according to item 丨 of the patent application scope, the process and etching technology pattern the sacrifice layer. 2. China-Israel lithography 9. The manufacturing method of the gate electrode according to item 丨 of the patent application scope, which includes a plasma containing a fluorine-containing component gas and an oxygen gas or one of HeO2. Conductor layer. The breast money is engraved with the sacrifice I. The manufacturing method of the gate electrode according to item 9 of the scope of patent application, the He02 flow rate is used to control the thickness of the polymer layer formed. Medium oxygen or II. If the gate electrode manufacturing method of item 9 of the patent application scope, the complex gas is selected from the group consisting of CF4, CxFy and CxHyFz, or any two of them. Aiki from above 1 2 · If the gate electrode manufacturing method of item 9 of the patent application scope, the etching selectivity of the conductor layer relative to the sacrificial layer is between 0, and the gate electrode 13 · If the gate electrode of the patent application area is manufactured, Method, technology to remove the gate conductor thickness not covered by the polymer layer Page 16 200410325 VI. Application for patent scope 1 4. The manufacturing method of the gate electrode according to item 13 of the patent application scope, wherein removing the polymer layer includes at least the following steps: removing the polymer layer by dry etching technology; and Yuyu technology cleans one surface of the gate conductor layer. 1 5. The method of manufacturing a gate according to item 1 of the patent application scope, wherein the gate dielectric layer not covered by the gate conductor layer is removed by an etching technique. 16. A method for manufacturing a gate, the method includes at least the following steps: sequentially forming a gate dielectric layer, a gate conductor layer, and a sacrificial layer over a semiconductor substrate; patterning the sacrificial layer; The sacrificial layer and the gate conductor layer are etched with a plasma gas containing a fluorine-containing component gas to completely remove the sacrificial layer, and a polymer layer is formed at the sidewall before the sacrificial layer is etched; The gate conductor layer covered by the polymer layer; removing the polymer layer; and removing the gate dielectric layer not covered by the gate conductor layer. 1 7. The method for manufacturing a gate electrode according to item 16 of the scope of patent application, wherein the material of the semiconductor substrate is silicon. 1 8. The manufacturing method of the gate electrode according to item 16 of the patent application scope, wherein the gate country page 17 200410325 The thickness of the dielectric layer is between 10 and 30A. 19 · If the gate electrode manufacturing method according to item 6 of the patent application scope, the material of the electrode conductor layer is polycrystalline silicon. In the gate 20, the gate electrode manufacturing method of item 16 in the scope of patent application, the thickness of the electrode conductor layer is between 500 and 2000a, and the gate of item 21 in the scope of patent application The manufacturing method of the electrode is selected from the group consisting of silicon dioxide, silicon nitride and silicon oxynitride. 22. If the gate electrode manufacturing method according to item 16 of the patent application scope, the thickness of the animal layer is between 100 and 100A. ′, I sacrifice 23. If the gate electrode manufacturing method according to item 16 of the patent application scope, the sacrifice layer is patterned by a photolithography process and an etching technique. 24. If the gate electrode manufacturing method of item 16 in the scope of patent application is applied, the slurry gas further contains an oxygen or He02, and the flow rate of the oxygen or He02 is used to form the thickness of the polymer layer. Control station 2j · If the gate electrode manufacturing method according to item 6 of the patent application scope, the fluorine component gas is selected from CF4, CxFy and CxHyFz or any of them ^ one of the gas-containing Zhao groups. Shit Page 18 200410325 VI. Application scope of patent 26. The manufacturing method of the gate electrode according to item 16 of the scope of patent application, wherein the etching selectivity of the electrode conductor layer relative to the sacrificial layer is between 0.5 and 5. ™ 2 7 · If the gate electrode manufacturing method of item 16 in the patent application scope, the etching technique removes the gate conductor layer not covered by the polymer layer 28 · As in the gate electrode of item 27 of the patent application scope, The manufacturing method, wherein the polymer layer includes at least the following steps: removing the polymer layer by a dry etching technique; and cleaning the gate conductor layer by a wet etching technique. 29. If the gate electrode manufacturing method of the patent application item No. 16 is used, the gate dielectric layer is not covered by the gate conductor layer and the gate dielectric layer is etched away. 30 kinds of hard mask manufacturing methods A gate electrode is formed on the semi-conductor. The surface of the + conductor base is formed with a gate conductor layer and a sacrificial layer above the bottom of the earth. The layer is formed by patterning the sacrificial layer. The sacrificial layer and the gate conductor are etched, and a polymer layer is formed at the sacrificial layer to completely remove the sacrificial layer, and a sidewall is formed before the layer is etched. 200410325 VI. Scope of Patent Application " ~ 32 · The manufacturing method of hard mask as described in item 30 of the scope of patent application, where = the thickness of the closed-electrode dielectric layer is between 10 ~ 30A. '^ 33. If the manufacturing method of the hard cover of item 30 of the patent application scope, the material of the idler conductor layer is polycrystalline. The 34. The manufacturing method of the hard cover as described in item 30 of the scope of the patent application, wherein the thickness of the conductor conductor layer is between 500 and 2000 A. /. 35. The method for manufacturing a hard mask according to item 30 of the scope of patent application, wherein the material of the sacrificial layer is selected from the group of U.S. dioxide, nitrided zone and oxynitride. The manufacturing method of the hard mask of item 30, wherein the thickness of the sacrificial layer is between 100 and 100 (2. 2) The manufacturing method of the hard mask of item 30, wherein the manufacturing process and etching are used. Technology patterned the sacrificial layer. 2. The manufacturing method of the hard mask of Renruo / Patent No. 30, wherein the sacrificial layer and the plasma are etched with a fluorine-containing component gas and oxygen or one of He02 plasma gas. Gate conductor layer. Page 20 200410325 Among them: 6. Scope of patent application 39. The manufacturing method of the hard cover of item 38 of the scope of patent application The gas or He02 flow rate is used to control the thickness of the polymer layer formed. 40. The method for manufacturing a hard mask according to item 38 of the application, wherein the fluorine-containing component gas is selected from the group consisting of CF4, CxFy, CxHyFz, or any two of them. The above is 41. If the manufacturing method of the hard cover of item 38 of the scope of the patent application, the etching selectivity of the gate conductor layer with respect to the sacrificial layer is between 0.5 ′ and 5 ′: Page 21