200405360 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明） (一) 發明所屬之技術領域 本發明係有關一種半導體記憶體裝置，且更特別的是有 一種由各含有複數個記憶體區塊及襯墊/控制區塊之記憶 體排組構成的半導體記憶體晶片架構，以及依符合空間效 益方式將各記憶體區塊安排於半導體記憶體裝置內之記憶 排組上的方法。 (二) 先前技術 如同吾人所熟知的，半導體記憶體裝置一般而言係設置 有一半導體記憶體晶片以及一封包。該半導體記憶體晶片 具有複數個可獨立地接達的記憶體排組。通常，該記憶體 裝置係由例如四個記憶體排組構成的且每一個記憶體排組 係由例如四個記憶體區塊構成的。每一個記憶體區塊都包 含複數個依矩陣形式安排並可藉由相同的X-解碼器和γ-解碼器選出的記憶體單元。 第1圖係用以顯示一半導體記憶體晶片內之標準記憶體 排組的平面圖示。例如，圖中顯示的是2 5 6 -百萬位元（M b i t) 的半導體記憶體晶片。 如圖所示，該半導體記憶體晶片係包含1 6個各呈方形或 矩形的記憶體區塊MB並將四個記憶體區塊指派爲一個記 憶體排組BankO，Bankl，Bank2或Bank3。同時將每一個記 憶體排組BankO, Bankl，Bank2或Bank3建造成矩形的。 每一個記憶體區塊Μ B都是由複數個對應到1 6 -百萬位元 200405360 之單位單元構成的。將各單位單元分組成四個各對應到4 -百萬位元記憶體區塊的單位記憶體區塊UMB。每一個記憶 體區塊都包含有一沿著X-軸的X-解碼器以及一沿著Y-軸 的Y -解碼器以便選出其中一個記憶體單元。 應該將複數個襯墊1 2和控制區塊1 4配置於該半導體記 憶體晶片內除了各記憶體區塊以外的區上。各襯墊1 2和控 制區塊1 4係沿著X-軸配置於如第1圖所示之習知半導體 記憶體晶片1 〇的中心上。如同吾人所熟知的，係使用各襯 墊1 2以便將信號傳送到該半導體記憶體晶片1 0的外部電 路上，且各控制區塊1 4會控制各記憶體單元上的資料輸入 /輸出以回應一由外部電路施加其上的控制信號。 第2圖係用以顯示一種具有增大尺寸之半導體記憶體晶 片與一習知封包之間關係的平面示意圖。 符號2 0代表的是例如用以施行一 2 5 6 - M b i t半導體記憶 體晶片的習知封包。符號2 2代表的是一由依與2 5 6 - M b i t 晶片中所用的設計規則設計出之512-Mbit半導體記憶體 晶片構成的記憶體排組陣列。 如圖所示，例如將具有16個記憶體區塊MB的512-Mbit 半導體記憶體晶片安排在具有與根據聯合電子裝置工程委 員會（JEDEC)之標準封包規則相同之設計規則的習知封包 內。不過，隨著該半導體記憶體晶片之儲存容量的增加例 如從2 5 6 -Mbit增加爲512-Mbit，會在相同的設計規則下顯 著地增大該半導體記憶體晶片的尺寸。結果，無法將尺寸 已增大的16個由512-Mbit半導體記憶體晶片構成的記憶 200405360 體區塊MB安排在如第2圖所示之習知封包內。據此，爲 了將該半導體記憶體晶片安排在相同的封包內，應該施行 具有更高技術的設計規則。不過，爲了開發更高技術下的 設計規則會需要更高的成本和時間，以致存在有記憶體製 造商無法依適當而有時效得方式爲所需要的系統供應具有 已大幅增加其儲存容量之半導體記憶體晶片的問題。 此外，當該半導體記憶體晶片呈方形亦即晶片內水平長 度對垂直長度的比例爲1 : 1時，將可從一晶圓獲致最大數 目的半導體記憶體晶片。不過，假如如第2圖所示係依使 該半導體記憶體晶片內水平長度對垂直長度之比例變得更 大的方式形成該半導體記憶體晶片，則會顯著地減少可從 一晶圓獲致的晶片數目。 (三)發明內容 因此，本發明的目的是提供一種半導體記憶體裝置，其 係能夠根據本發明在未發展高科技下高度地整合各記憶體 晶片。 根據本發明之一項觀點，係提供一種具有半導體記憶體 晶片的半導體記憶體裝置，其中每一個半導體記憶體晶片 都包括：複數個記憶體排組，係可單獨地被存取且各含有 複數個記憶體區塊，其中係使落在相同記憶體排組內且互 爲相鄰的至少兩個記憶體區塊具有不同數目的單位記憶體 區塊，使各排組具有非矩形形式。 根據本發明另一觀點所提供的一種具有半導體記憶體晶 片的半導體記憶體裝置，係將該半導體記憶體晶片分割成 200405360 1 8個含有呈3列x 6行之陣列形式而具有相等面積的區，其 中該半導體記憶體晶片係包括：一第一記憶體排組，係包 含安排在一個選自第二列X第一行的區、第二列X第二行的 區及第二列X第三行的區且落在第一列X第一行的區、第一 列X第二行的區及第一列X第三行的區之類各區上的記憶體 區塊；一第二記憶體排組，係包含安排在一個選自第二列X 第一行的區、第二列X第二行的區及及第二列X第三行的區 且落在第三列X第一行的區、第三列X第二行的區及第三列X 第三行的區之類各區上的記憶體區塊；一第三記憶體排組 ，係包含安排在一個選自第二列X第四行的區、第二列X第 五行的區及第二列X第六行的區且落在第一列X第四行的區 、第一列X第五行的區及第一列X第六行的區之類各區上的 記憶體區塊；一第四記憶體排組，係包含安排在一個選自 第二列X第四行的區、第二列X第五行的區及第二列X第六行 的區且落在第三列X第四行的區、第三列X第五行的區及第 三列X第六行的區之類各區上的記憶體區塊；以及各襯墊和 控制區塊，係包含安排在一個選自第二列X第一行的區、第 二列X第二行的區、第二列X第三行的區、第二列X第四行的 區、第二列X第五行的區及第二列X第六行的區之類各區上 的記憶體區塊。 根據本發明又一觀點提供了 一種用於將記憶體區塊安排 於半導體裝置之半導體記憶體晶片內的方法’係包括下列 步驟：排列複數個記憶體區塊使之具有複數個相鄰的單位 記憶體區塊；以及排列複數個記憶體排組使之具有相鄰的 200405360 記憶體區塊，其中在相同的排組內至少有兩記億體區塊會 具有數目互不相同的單位記憶體區塊，使各記憶體排組都 具有非矩形形式。 (四)實施方式 以下將參照各附圖詳細說明一種能夠根據本發明將具有 已增加其儲存容量之半導體記憶體晶片封裝於一習知封包 內的半導體記憶體裝置。 爲求方便，將說明一種5 1 2 - M b i t雙倍資料速率之同步動 態隨機存取記憶體（DDR SDRAM)當作實例。 1)第一實施例 第3圖係用以顯示一種根據本發明第一實施例之5 12-Mbit DDR SDRAM(以 下稱作 半導體 記憶體 晶片）的 平面示 意圖。 如圖所示，該半導體記憶體晶片係包含1 2個記憶體區塊 MB —0到MB —1 1，且每一個記憶體區塊都包含有一沿著X-軸的X -解碼器以及一沿著Y -軸的Y -解碼器以便選出每一 個記憶體區塊內所含各記憶體單元之一。此中，Y -軸通常 是比X -軸更短。每一個記憶體排組都包含有三個記憶體區 塊Μ B，而該半導體記憶體晶片則包含有四個記憶體排組 BankO，Bankl，Bank2和Bank3，其中每一個記憶體排組都 能夠在其內的各記憶體單元之一上獨立地輸入並輸出資料。 其中一個記憶體排組B an k0係包含三個記憶體區塊 ΜΒ_0到MB — 2。第一記憶體區塊MB —0係包含六個單位記 憶體區塊U Μ B，而每一個單位記憶體區塊都具有一 8 - M b i t 200405360 記憶體單元。因此，該第一記憶體區塊ΜΒ_0會對應到一 4 8-Mbit記憶體區塊。第二和第三記憶體區塊MB_1和MB_2 分別包含有五個單位記憶體區塊，以致第二和第三記憶體 區塊MB—1和MB_2各會對應到一 40-Mbit記憶體區塊。另 外三個記憶體排組Bankl，Bank2和Bank3的排列係類似於 該第一記憶體排組Bank 0的排列。據此，每一個記憶體排 組都是非矩形的。 該48-Mbit記憶體區塊內的X-解碼器係形成於第五單位 記憶體區塊與第六單位記憶體區塊之間，且在接續形成的 第六單位記憶體區塊內具有類似於鄰近4 0 - M b i t記憶體區 塊的設計。該4 8 - M b i t記憶體區塊內的X -解碼器都具有兩 個驅動端子（第3圖中未顯示）以便藉由該48-Mbit記憶體 區塊內的X-解碼器驅動該48-Mbit記憶體區塊。使用某一 驅動端子以驅動具有五個單位記憶體區塊的40-Mb it記憶 體區塊，並使用另一驅動端子以驅動剩餘的8 - M b i t單位記 憶體區塊。可將該48-Mbit記憶體區塊安排在任一記億體 區塊上。 如第3圖所示，係將該第一記憶體排組B ankO安排在第 二象限上並將該第二記憶體排組B ank 1安排在第三象限上 。將該第三記憶體排組B ank2安排在第一象限上並將該第 四記憶體排組Bank3安排在第四象限上。將該48-Mbit記 憶體區塊內的第一排組BankO和第二排組Bankl安排在其 中的最左邊區上並將該48-Mbit記憶體區塊內的第三排組 Bank2和第四排組B a n k 3安排在其中的最右邊區上。 -10- 200405360 如圖所示，在各4 8 - M b i t記憶體區塊之間例如相互間呈 · 垂直相鄰的MB — 0與MB_3或是MB — 8與MB_11之間沒有 任何空間可設置各襯墊及控制區塊。由於在呈垂直相對的 各40-Mbit記憶體區塊之間有足夠的空間30，故可將各襯 墊1 2 0及控制區塊1 4 0安排於其間。亦即，依水平方式將 各襯墊1 2 0及控制區塊1 4 0安排在該半導體記憶體晶片的 中心區內。在將X -軸分割成6個區時，係將各襯墊1 2 0及 控制區瑰1 4 0安排在中心區內，亦即只將它們安排在從第 二區到第五區內。 _ 第4 A圖係用以顯示一種具有習知排組陣列之5 1 2-Mbit 半導體記憶體晶片與一習知封包之間關係的平面示意圖， 而第4 B圖係用以顯示一種具有根據本發明之排組陣列之 5 12-Mbit半導體記憶體晶片與一習知封包之間關係的平面 示意圖。 如圖所示當應用相同的設計規則時本發明的第一實施例 會滿足習知的封包尺寸，不過如第4 A圖所示習知設計並 不滿足該封包。 1 第5 A和5 B圖係用以顯示該半導體記憶體晶片與藉由改 變本發明第一實施例中48-Mbit記憶體區塊及控制區塊之 位置所得到封包之間關係的平面示意圖。第5 A圖顯示的 是將每一個記憶體排組內的每一個48-Mbit記憶體區塊安 排在該半導體記憶體晶片的中心區內，而第5 B圖顯示的 是將各48-Mbit記憶體區塊安排在每一個記憶體排組內的 各4 0 - M b i t記憶體區塊之間。此中，即使當藉由分割成2 200405360 或3個區以安排各襯墊1 2 0及控制區塊1 4 0時，第5 A和 5 B圖也顯示了該半導體記憶體晶片會滿足習知的封包尺 寸。同時較之習知設計，因爲減小了 X -軸長度對Y -軸長_ 度的比例而增加了根據本發明在每個晶圓內得到的晶片數 目。 2 )第二實施例 第6圖係用以顯示一種根據本發明第二實施例之半導體 記憶體晶片亦即一 512-Mbit DDR SDRAM晶片的平面示意圖。 如圖所示，將該半導體記憶體晶片垂直地分割成3個區 且水平地分割成6個區。也就是說，將該半導體記憶體晶 片分割成具有1 8區的3 x6區塊陣列。此中，該半導體記憶 體晶片之水平·軸（以下稱爲X -軸）長度會比其垂直-軸（以 下稱爲Y -軸）長度更長。 於Y -軸的中間區內，係將對應於該1 8區中之第二列及 第一行的區（2, 1)分割成兩個區（2 a，la)和（2b，lb)。同時，將 其中對應於第二列及第三行的區（2,3)分割成兩個區（2a，3 a) 和（2 b，3 b )。該已分割的上邊各區（2 a，1 a )和（2 a，3 a )係連同區 (1，1)，（1，2)和（1，3)包含於第一排組BankO內。該已分割的 下邊各區（2 b，1 b )和（2 b，3 b )係連同區（3，1 )，（ 3，2 )和（3 , 3 )包 含於第二排組Bankl內。據此，該第一排組BankO和第二 排組B ank 1係不同於習知設計而呈非矩形的。將一控制區 塊安排在區（2，2)上以控制該第一記憶體排組BankO和第二 記憶體排組Bankl。 第三排組Bank2和第四排組Bank3具有與該第一排組 -12- 200405360 B a n k 0和第二排組B a n k 1相同的排列。於各中間區內，係 將區（2,4)分割成兩個區（2a, 4 a)和（2b，4b)，並將區（2,6)分割 成兩個區（2 a，6 a )和（2 b，6 b )。該已分割的上邊各區（2 a , 4 a )和 (2a，6a)係連同區（1，4)，（1，5)和（1，6)包含於第三排組Bank2 內。該已分割的下邊各區（2b，4b)和（2b，6b)係連同區（3,4)， (3, 5)和（3,6)包含於第四排組Bank3內。據此，該第三排組 Bank2和第四排組B a n k 3係不同於習知設計而呈非矩形的 。將複數個襯墊安排在該第一排組BankO與第二排組Bank 1 之間以及該第三排組Bank2與第四排組Bank3之間。同時 ，將第二控制區塊安排在區（2，5 )上以控制該第三記憶體排 組Bank2和第四記憶體排組Ban3。 該第一排組BankO係包含：一 48-Mbit的第一記憶體區 塊，係安排在區（1，1 )和（2 a，1 a )內；一 3 2 - M b i t的第二記憶 體區塊，係安排在區（1，2)內；一 48-Mbit的第三記憶體區 塊，係安排在區（1，3)和（2 a，3 a)內。於該第一記憶體區塊內 ，將其中有一個單位記憶體區塊係對應於8-Mbit之記憶體 區塊的四個單位記憶體區塊安排在區（1，1 )內並將兩個單 位記憶體區塊安排在區（2 a，la)內。 由於每一個記憶體排組都包含有兩個48-Mbit記憶體區 塊及一個32-Mbit記憶體區塊，故每一個記憶體排組都是 呈非矩形的。本發明的第二實施例可在未開發已改良規則 下滿足習知的封包尺寸。 第7圖係用以顯示一種根據本發明第二實施例之半導體 記憶體晶片與習知封包之間關係即使在應用與習知設計相 -13- 200405360 同的設計規則時也會滿足習知封包尺寸的平面示意圖。同 時，因爲減小了 X-軸（長度）對Y-軸（長度）的比例而增加了 根據本發明在每個晶圓內得到的晶片數目。 每一個記憶體區塊都包含有一對X-解碼器和Y-解碼器 。該48-Mbit記憶體區塊內的X-解碼器係形成於第四單位 記憶體區塊與第五單位記憶體區塊之間，且在接續形成的 第六單位記憶體區塊內具有類似於鄰近32-Mbit記憶體區 塊的設計。該X-解碼器具有兩個驅動端子（未標示）以便以 該4 8 · M b i t記憶體區塊內的X -解碼器驅動該4 8 - M b i t記憶 體區塊。使用某一驅動端子驅動具有四個單位記憶體區塊 的3 2-Mbit記憶體區塊，並使用另一驅動端子驅動剩餘的 1 6 - M b i t記憶體區塊。 該48-Mbit記憶體區塊內的X-解碼器都具有兩個驅動端 子（第3圖中未顯示）以便藉由該48-Mbit記憶體區塊內的 X -解碼器驅動該4 8 - M b i t記憶體區塊。使用某一驅動端子 以驅動具有五個單位記憶體區塊的4 0 - M b i t記憶體區塊， 並使用另一驅動端子以驅動剩餘的8 - M b i t單位記憶體區 塊。可將該48-Mbit記憶體區塊安排在任一記憶體區塊上。 沿著X-軸將複數個襯墊安排在該第一排組BankO與第二 排組Bankl之間以及該第三排組Bank2與第四排組Bank3 之間。 第8 A和8 B圖係用以顯示該半導體記憶體晶片與藉由改 變第7圖中各控制區塊之位置所得到封包之間關係的平面 示意圖。如第8 A圖所示將第一控制區塊安排在區（2，1 )內 -14- 200405360 並將第二控制區塊安排在區（2，6 )內，且如第8 B圖所示將 第一控制區塊和第二控制區塊安排在不同於第7圖的區 (2，3 )和（2，4 )內。 同時，第8 A和8B圖中的第一到第四記憶體排組Bank 0-Bank3都是呈非矩形的且都會滿足習知的封包尺寸。 3 )第三實施例 第9圖係用以顯示一種根據本發明第三實施例之512-M b i t D D R S D R A Μ晶片的平面示意圖。 如圖所示，將該半導體記憶體晶片垂直地分割成3個區 且水平地分割成6個區。也就是說，將該半導體記憶體晶 片分割成具有1 8個區的3 X 6區塊陣列。此中，該半導體記 憶體晶片之水平-軸（以下稱爲X -軸）長度會比其垂直-軸（ 以下稱爲Υ -軸）長度更長。將各記憶體區塊安排在1 6區以 及一個由四個互爲相鄰之記憶體區塊構成的排組上。第一 和第二控制區塊則安排在另外兩個區內。 分別將四個各具有四個8-Mbit單位記憶體區塊的32-Mbit 記憶體 區塊安 排在第 一排組 BankO 內的區 （1，1)，（1，2)， (1 , 3 )和（2，1 )上。雖則每一個3 2 - M b i t記憶體區塊都是矩形 的，然而由四個記憶體區塊構成的第一排組Ban k0具有不 同於習知排組的非矩形形狀。 分別將四個32-Mbit記憶體區塊安排在第二排組Ban kl 內的區（2，3 )，（ 3，1 )，（ 3，2 )和（3 , 3 )上。雖則每一個 3 2 - M b i t 記 憶體區塊都是矩形的，然而由四個記憶體區塊構成的第二 排組B ank 1具有不同於習知排組的非矩形形狀。將第一控 -15- 200405360 制區塊安排在爲第一排組BankO和第二排組Bankl所圍繞 · 的區（2,2 )上。 依與該第一排組BankO和第二排組Bankl相同的方式安 排第三排組Bank2和第四排組Bank3。將第二控制區塊安 排在爲第三排組Bank2和第四排組Bank3所圍繞的區（2,5) 上。 每一個記憶體區塊都包含有一對沿著X-軸的X-解碼器 和沿著Y-軸的Y-解碼器。屬於相同的排組而呈垂直相鄰 的各32-Mbit記憶體區塊相互間會共享一 X-解碼器。 馨 沿著該半導體記憶體晶片的中心將複數個襯墊安排在該 第一排組BankO與第二排組Bankl之間以及該第三排組 B a n k 2與第四排組B a n k 3之間。 亦即，一個排組係由四個3 2 - M b i t記憶體區塊構成的且 其形狀是非矩形的。 第1 〇圖係用以顯示第9圖中根據本發明第三實施例之半 導體記憶體晶片與一習知封包之間關係會滿足習知封包尺 寸的平面示意圖。 ^ 第1 1 A和1 1 B圖係用以顯示根據本發明第三實施例之半 導體記憶體晶片與藉由改變第一和第二控制區塊之位置所 得到封包之間關係的平面示意圖。 如第1 1 A圖所示，將第一控制區塊安排在區（2，1 )上並將 第二控制區塊安排在不同於第9圖之陣列的區（2，6 )上。同 時如第1 1 B圖所示，可將第一控制區塊安排在區（2，3 )上並 將第二控制區塊安排在區（2，4)上。根據本發明的第三實施 -16- 200405360 例，各記憶體排組BankO到Bank3都是呈非矩形的且該半 導體記憶體晶片滿足習知的封包尺寸，以致不需要在應用 相同的規則時擴充該封包的X-軸以便使該半導體記憶體 晶片具有已增大的儲存容量。 因爲將記憶體排組製造成非矩形的形狀以取代規則的矩 形形狀，故能夠使具有已增大儲存容量的半導體記憶體晶 片滿足習知的封包尺寸。因此，能夠以低成本製造出具有 高效率的半導體記憶體晶片。 以下將要說明一種由將要用於上述結構內的複數個襯墊 、電源線及資料線構成的陣列。 第1 2圖係用以顯示第6圖中相互間將要根據本發明第二 實施例作佈線接合之各電源引線框架與各襯墊間之互連結 構的平面示意圖。 符號la，lb和lc代表的是用於VSS的引線框架而符號 2a, 2b，和2c代表的是用於VDD的引線框架。同時，符號 3代表的是一襯墊而符號4代表的是一電線。 一般而言，SDRAM具有由三對VDD和VSS構成的封裝 銷栓。如第1 2圖所示，各電源引線框架係排列在該半導體 記憶體晶片的左右兩側以及中間部分上。定位在該半導體 記憶體晶片之中間部分上的引線框架1 b和2b的形成方式 係藉由依雙向方式使引線框架擴充到X -軸上而與三對 V D D和V S S作佈線接合。第6圖中，不需要在區（2 a，3 a ) 與區（2b，3 b)之間以及區（2 a，4a)與區（2b，4b)之間形成引線 框架用電源排流。同時，可將上述引線框架應用到第3圖 -17- 200405360 和第9圖的實施例上。 排列於晶片內之晶圓位準內的各電源線係以平面篩網型 式建造於該晶片的各記憶體區塊上方。假如將各電源線或 信號線排列在Y -解碼器的各輸出線之間，則可使各電源線 或信號線連接於第一控制區塊與第二控制區塊之間。因此 ，不需要在區（2a，3a)與區（2b，3b)之間以及區（2a，4a)與區 (2 b，4 b )之間形成各電源線或信號線，以致能夠減少爲各襯 墊及控制區塊所佔據的空間。 第1 3圖係用以顯示第6圖中根據本發明第二實施例之資 料線排列平面示意圖。 一般而言，係將記憶體陣列的各資料線連接到該Y -解碼 器內的感測放大器上。並將用於每一個記憶體排組的各資 料線結合到一通用資料線上。此時，爲了減小肇因於電線 的資料延遲，係將每一個記憶體排組的左側資料線7 a連接 到一左側資料襯墊上，並將每一個記憶體排組的右側資料 線7 b連接到一右側資料襯墊上。 由於該半導體記憶體晶片具有的記憶體排組係呈含平面 的非矩形形狀，故可在未開發已改良設計規則下將具有已 增加之儲存容量的半導體記憶體裝置應用在習知封包上。 亦即，可以低成本提供該半導體記憶體晶片。 同時由於不需要擴充其封包尺寸亦即明確地說其X -軸 以便獲致具有高儲存容量的半導體記憶體晶片，故存在有 減小該半導體記憶體晶片上X-軸與Y-軸之間比例的效應 。因此，增加了可從一晶圓獲致的晶片數目。 -18- 200405360 此外，由於可減小用於每一個記憶體排組的x -解碼器數 目，故可減小爲各X-解碼器所佔據的面積。 雖則已相對於各特定實施例說明了本發明，對熟悉習用 技術的人而言很明顯地可在不偏離本發明定義如下之申請 專利範圍的精神及架構下作各種改變和修正。 (五)圖式簡單說明 本發明的上述及其他目的、特性、及優點將會因爲以下 結合各附圖對各較佳實施例的說明而變得更明顯。 第1圖係用以顯示一半導體記憶體晶片內之標準記憶體 排組的平面圖示。 第2圖係用以顯示一種具有增大尺寸之半導體記憶體晶 片與一習知封包之間關係的平面示.意圖。 第3圖係用以顯示一種根據本發明第一實施例之5 1 2 -Mbit DDR SDRAM晶片的平面示意圖。 第4 A圖係用以顯示一種具有習知排組陣列之5 1 2 - M b i t 半導體記憶體晶片與一習知封包之間關係的平面示意圖。 第4 B圖係用以顯示一種具有根據本發明之排組陣列之 5 1 2 - M b i t半導體記憶體晶片與一習知封包之間關係的平面 示意圖。 第5 A和5 B圖係用以顯示該半導體記憶體晶片與藉由改 變本發明第一實施例中4 8 - M b i t記憶體區塊及控制區塊之 位置所得到封包之間關係的平面示意圖。 第6圖係用以顯示一種根據本發明第二實施例之半導體 記憶體晶片亦即一 5 1 2-Mbit DDR SDRAM晶片的平面示意 200405360 圖。 第7圖係用以顯示一重根據本發明第二實施例之半導體 記憶體晶片與習知封包之間關係會滿足習知封包尺寸的平 面示意圖。 第8 A和8 B圖係用以顯示該半導體記憶體晶片與藉由改 變第7圖中各控制區塊之位置所得到封包之間關係的平面 示意圖。200405360 发明 Description of the invention (The description of the invention should state: the technical field, prior art, content, embodiments, and drawings of the invention briefly) More specifically, there is a semiconductor memory chip architecture composed of a memory bank containing a plurality of memory blocks and pads / control blocks, and each memory block is arranged in a semiconductor in a space-efficient manner. Method on memory bank in memory device. (II) Prior technology As I am familiar with, a semiconductor memory device is generally provided with a semiconductor memory chip and a package. The semiconductor memory chip has a plurality of independently accessible memory banks. Generally, the memory device is composed of, for example, four memory banks and each memory bank is composed of, for example, four memory banks. Each memory block contains a plurality of memory cells arranged in a matrix and selectable by the same X-decoder and γ-decoder. Figure 1 is a plan view showing a standard memory bank in a semiconductor memory chip. For example, the figure shows a 2 5 6 -Mbit semiconductor memory chip. As shown in the figure, the semiconductor memory chip includes 16 memory blocks MB each having a square or rectangular shape and assigns four memory blocks as a bank bank BankO, Bankl, Bank2 or Bank3. At the same time, each bank group BankO, Bankl, Bank2 or Bank3 is formed into a rectangular shape. Each memory block MB is composed of a plurality of unit cells corresponding to 16-million bits 200405360. Each unit cell is grouped into four unit memory blocks UMB each corresponding to a 4-megabit memory block. Each memory block contains an X-decoder along the X-axis and a Y-decoder along the Y-axis to select one of the memory cells. A plurality of pads 12 and control blocks 14 should be arranged on the area of the semiconductor memory chip except for each of the memory blocks. Each pad 12 and the control block 14 are arranged along the X-axis at the center of a conventional semiconductor memory wafer 10 shown in Fig. 1. As we are familiar, each pad 12 is used to transmit signals to the external circuit of the semiconductor memory chip 10, and each control block 14 controls the data input / output on each memory unit to In response to a control signal applied by an external circuit. Fig. 2 is a schematic plan view showing the relationship between a semiconductor memory chip having an increased size and a conventional packet. The symbol 2 0 represents, for example, a conventional packet used to implement a 2 5 6-M bit semiconductor memory chip. The symbol 2 2 represents a memory bank array composed of 512-Mbit semiconductor memory chips designed according to the design rules used in the 2 56-M bit chip. As shown in the figure, for example, a 512-Mbit semiconductor memory chip having 16 memory blocks MB is arranged in a conventional package having the same design rules as the standard package rules of the Joint Electronic Device Engineering Committee (JEDEC). However, as the storage capacity of the semiconductor memory chip is increased, for example, from 256-Mbit to 512-Mbit, the size of the semiconductor memory chip is significantly increased under the same design rules. As a result, it is impossible to arrange the 16 memory blocks 200405360 of the 512-Mbit semiconductor memory chip having the increased size in the conventional package shown in FIG. 2. Accordingly, in order to arrange the semiconductor memory chip in the same package, design rules with higher technology should be implemented. However, in order to develop design rules under higher technology, higher costs and time are needed, so that there is a memory manufacturer that cannot supply the required system with semiconductors that have significantly increased its storage capacity in an appropriate and effective manner. Problems with memory chips. In addition, when the semiconductor memory chip is square, that is, the ratio of the horizontal length to the vertical length in the wafer is 1: 1, the maximum number of semiconductor memory chips can be obtained from one wafer. However, if the semiconductor memory chip is formed in such a manner that the ratio of the horizontal length to the vertical length in the semiconductor memory chip becomes larger as shown in FIG. 2, it will significantly reduce the Number of wafers. (3) Summary of the Invention Therefore, an object of the present invention is to provide a semiconductor memory device capable of highly integrating various memory chips according to the present invention without developing high technology. According to an aspect of the present invention, there is provided a semiconductor memory device having a semiconductor memory chip, wherein each semiconductor memory chip includes: a plurality of memory banks, which are individually accessible and each contain a plurality of Memory blocks, where at least two memory blocks that are within the same memory bank group and are adjacent to each other have different numbers of unit memory blocks, so that each bank group has a non-rectangular form. According to another aspect of the present invention, there is provided a semiconductor memory device having a semiconductor memory chip. The semiconductor memory chip is divided into 200 405 360 1 8 regions having an equal area in the form of an array of 3 columns x 6 rows. The semiconductor memory chip system includes: a first memory bank group including a region selected from a second column X first row region, a second column X second row region, and a second column X second row Three rows of memory blocks that fall on various regions such as the first column X first row region, the first column X second row region, and the first column X third row region; The memory bank group is arranged in a region selected from the second column X first row region, the second column X second row region and the second column X third row region and falls in the third column X third row A block of memory on each region, such as a row of regions, a third column X a second row region, and a third column X a third row region; a third memory bank group, which is arranged in a group selected from The second column X fourth row area, the second column X fifth row area, and the second column X sixth row area, and the first column X fourth row area, first column A memory block on each area such as the area in the fifth row of X and the area in the first row X of the sixth row; a fourth memory bank includes a region arranged in a row selected from the second column X the fourth row The second column X fifth row area and the second column X sixth row area and the third column X fourth row area, the third column X fifth row area, and the third column X sixth row area Memory blocks on various regions such as; and pads and control blocks, which are arranged in a region selected from the second column X first row region, second column X second row region, second column A memory block on each region such as a region in the third row, a region in the second column X, a region in the fourth row, a region in the second column X fifth row, and a region in the second column X sixth row. According to yet another aspect of the present invention, a method for arranging a memory block in a semiconductor memory chip of a semiconductor device is provided. The method includes the following steps: arranging a plurality of memory blocks to have a plurality of adjacent units Memory blocks; and arranging multiple memory banks to have adjacent 200405360 memory blocks, where at least two billion bank blocks within the same bank will have different numbers of unit memory Blocks, so that each memory bank has a non-rectangular form. (IV) Embodiment A semiconductor memory device capable of packaging a semiconductor memory chip having an increased storage capacity in a conventional package according to the present invention will be described in detail below with reference to the accompanying drawings. For convenience, a 5 1 2-M b i t double data rate synchronous dynamic random access memory (DDR SDRAM) will be described as an example. 1) First Embodiment FIG. 3 is a plan view showing a 5 12-Mbit DDR SDRAM (hereinafter referred to as a semiconductor memory chip) according to the first embodiment of the present invention. As shown in the figure, the semiconductor memory chip system includes 12 memory blocks MB-0 to MB-11, and each memory block includes an X-decoder along the X-axis and a A Y-decoder along the Y-axis in order to select one of the memory cells contained in each memory block. Here, the Y-axis is usually shorter than the X-axis. Each memory bank contains three memory banks MB, and the semiconductor memory chip contains four memory banks BankO, Bankl, Bank2, and Bank3, each of which can Data is input and output independently on one of the memory cells therein. One of the memory banks Bank0 contains three memory blocks MB_0 to MB-2. The first memory block MB-0 contains six unit memory blocks U MB, and each unit memory block has an 8-Mbit 200405360 memory unit. Therefore, the first memory block MB_0 will correspond to a 48-Mbit memory block. The second and third memory blocks MB_1 and MB_2 each contain five unit memory blocks, so that the second and third memory blocks MB-1 and MB_2 each correspond to a 40-Mbit memory block . The arrangement of the other three memory banks Bank1, Bank2 and Bank3 is similar to that of the first memory bank Bank0. Accordingly, each memory bank is non-rectangular. The X-decoder in the 48-Mbit memory block is formed between the fifth unit memory block and the sixth unit memory block, and has a similarity in the subsequent sixth unit memory block. Designed for adjacent 40-M bit memory blocks. The X-decoder in the 48-M bit memory block has two drive terminals (not shown in Figure 3) to drive the 48 by the X-decoder in the 48-Mbit memory block. -Mbit memory block. One drive terminal is used to drive a 40-Mb it memory block with five unit memory blocks, and another drive terminal is used to drive the remaining 8-Mb it unit memory blocks. This 48-Mbit memory block can be arranged on any of the 100 million memory blocks. As shown in FIG. 3, the first memory bank BankO is arranged on the second quadrant and the second memory bank Bank1 is arranged on the third quadrant. The third memory bank Bank2 is arranged on the first quadrant and the fourth memory bank Bank3 is arranged on the fourth quadrant. The first bank Bank0 and the second bank Bank1 in the 48-Mbit memory block are arranged on the leftmost region, and the third bank Bank2 and the fourth bank in the 48-Mbit memory block are arranged. The bank B ank 3 is arranged on the rightmost area. -10- 200405360 As shown in the figure, between each of the 4 8-M bit memory blocks, for example, there is a vertical adjacent MB — 0 and MB_3 or MB — 8 and MB_11 without any space to set Each pad and control block. Since there is sufficient space 30 between the vertically opposed 40-Mbit memory blocks, each pad 120 and control block 140 can be arranged in between. That is, the pads 120 and the control blocks 140 are arranged horizontally in the center area of the semiconductor memory chip. When the X-axis is divided into 6 regions, each pad 120 and control region 140 are arranged in the center region, that is, they are arranged only from the second region to the fifth region. _ Figure 4A is a plan view showing the relationship between a 5 1 2-Mbit semiconductor memory chip with a conventional bank array and a conventional package, and Figure 4B is a view showing a A schematic plan view of the relationship between a 5 12-Mbit semiconductor memory chip of a banked array of the present invention and a conventional packet. As shown in the figure, when the same design rule is applied, the first embodiment of the present invention will satisfy the conventional packet size, but the conventional design as shown in FIG. 4A does not satisfy the packet. 1 Figures 5 A and 5 B are schematic plan views showing the relationship between the semiconductor memory chip and packets obtained by changing the positions of the 48-Mbit memory block and the control block in the first embodiment of the present invention. . Figure 5A shows that each 48-Mbit memory block in each memory bank is arranged in the center area of the semiconductor memory chip, and Figure 5B shows that each 48-Mbit Memory blocks are arranged between each of the 40-M bit memory blocks in each memory bank. Here, even when the pads 1 2 0 and the control block 1 40 are arranged by being divided into 2 200405360 or 3 regions, the graphs 5A and 5B show that the semiconductor memory chip will satisfy the habit. Known packet size. At the same time, compared with the conventional design, the number of wafers obtained in each wafer according to the present invention is increased because the ratio of the X-axis length to the Y-axis length is reduced. 2) Second Embodiment FIG. 6 is a schematic plan view showing a semiconductor memory chip, that is, a 512-Mbit DDR SDRAM chip according to a second embodiment of the present invention. As shown in the figure, this semiconductor memory wafer is vertically divided into three regions and horizontally divided into six regions. That is, the semiconductor memory wafer is divided into a 3 x 6 block array having 18 regions. Here, the horizontal-axis (hereinafter referred to as X-axis) length of the semiconductor memory chip is longer than the vertical-axis (hereinafter referred to as Y-axis) length. In the middle region of the Y-axis, the region (2, 1) corresponding to the second column and the first row of the 18 region is divided into two regions (2 a, la) and (2b, lb). . At the same time, the area (2,3) corresponding to the second column and the third row is divided into two areas (2a, 3a) and (2b, 3b). The divided upper regions (2 a, 1 a) and (2 a, 3 a) are included in the first row group BankO together with the regions (1, 1), (1, 2), and (1, 3). . The divided lower regions (2 b, 1 b) and (2 b, 3 b) are included in the second row group Bankl together with the regions (3, 1), (3, 2), and (3, 3). . Accordingly, the first bank Bank0 and the second bank Bank 1 are non-rectangular, unlike conventional designs. A control block is arranged on the region (2, 2) to control the first bank bank Bank0 and the second bank bank Bank1. The third bank Bank2 and the fourth bank Bank3 have the same arrangement as the first bank -12-200405360 B a n k 0 and the second bank B a n k 1. In each intermediate area, the area (2,4) is divided into two areas (2a, 4a) and (2b, 4b), and the area (2,6) is divided into two areas (2a, 6) a) and (2b, 6b). The divided upper regions (2a, 4a) and (2a, 6a) are included in the third row group Bank2 together with the regions (1, 4), (1, 5), and (1, 6). The divided lower regions (2b, 4b) and (2b, 6b) are included in the fourth row group Bank3 together with the regions (3,4), (3, 5), and (3,6). According to this, the third row Bank2 and the fourth row Bank 3 are different from the conventional design and are non-rectangular. A plurality of pads are arranged between the first row Bank0 and the second row Bank1 and between the third row Bank2 and the fourth row Bank3. At the same time, the second control block is arranged on the area (2, 5) to control the third memory bank Bank2 and the fourth memory bank Ban3. The first bank BankO includes: a 48-Mbit first memory block, which is arranged in the areas (1, 1) and (2 a, 1 a); a 3 2-M bit second memory The volume block is arranged in the area (1, 2); a 48-Mbit third memory block is arranged in the areas (1, 3) and (2 a, 3 a). Within the first memory block, four unit memory blocks having one unit memory block corresponding to the 8-Mbit memory block are arranged in the region (1, 1) and two The unit memory blocks are arranged in the area (2 a, la). Since each memory bank contains two 48-Mbit memory blocks and a 32-Mbit memory block, each memory bank is non-rectangular. The second embodiment of the present invention can satisfy conventional packet sizes without developing improved rules. FIG. 7 is a diagram showing a relationship between a semiconductor memory chip and a conventional packet according to the second embodiment of the present invention, and the conventional packet is satisfied even when the same design rule as that of the conventional design is applied. Dimensional plan view. At the same time, the number of wafers obtained in each wafer according to the present invention is increased because the ratio of the X-axis (length) to the Y-axis (length) is reduced. Each memory block contains a pair of X-decoders and Y-decoders. The X-decoder in the 48-Mbit memory block is formed between the fourth unit memory block and the fifth unit memory block, and has a similarity in the subsequent sixth unit memory block. Designed for adjacent 32-Mbit memory blocks. The X-decoder has two drive terminals (not labeled) to drive the 4 8-M b i t memory block with the X-decoder in the 4 8 · M b i t memory block. One drive terminal is used to drive a 3 2-Mbit memory block with four unit memory blocks, and the other drive terminal is used to drive the remaining 16-M b i t memory blocks. The X-decoder in the 48-Mbit memory block has two driving terminals (not shown in Figure 3) to drive the 4 8 by the X-decoder in the 48-Mbit memory block. M bit memory block. One drive terminal is used to drive a 40-Mbit memory block with five unit memory blocks, and another drive terminal is used to drive the remaining 8-Mbit memory block. This 48-Mbit memory block can be arranged on any memory block. A plurality of pads are arranged along the X-axis between the first bank Bank0 and the second bank Bank1 and between the third bank Bank2 and the fourth bank Bank3. Figures 8A and 8B are schematic plan views showing the relationship between the semiconductor memory chip and packets obtained by changing the position of each control block in Figure 7. Arrange the first control block in area (2,1) as shown in Figure 8A-14-200405360 and arrange the second control block in area (2,6), as shown in Figure 8B It is shown that the first control block and the second control block are arranged in areas (2, 3) and (2, 4) different from FIG. 7. At the same time, the first to fourth memory banks Bank 0-Bank3 in Figures 8 A and 8B are all non-rectangular and all meet the conventional packet size. 3) Third Embodiment FIG. 9 is a schematic plan view showing a 512-M bi D D R S D R AM chip according to a third embodiment of the present invention. As shown in the figure, this semiconductor memory wafer is vertically divided into three regions and horizontally divided into six regions. That is, the semiconductor memory wafer is divided into a 3 X 6 block array having 18 regions. Here, the horizontal-axis (hereinafter referred to as X-axis) length of the semiconductor memory wafer is longer than the vertical-axis (hereinafter referred to as Υ-axis) length. Each memory block is arranged on 16 and a bank composed of four mutually adjacent memory blocks. The first and second control blocks are arranged in two other zones. Four 32-Mbit memory blocks each with four 8-Mbit unit memory blocks are arranged in the banks (1, 1), (1, 2), (1, 3) ) And (2,1). Although each 3 2-M b i t memory block is rectangular, the first bank Ban k0 composed of four memory blocks has a non-rectangular shape different from the conventional bank. Four 32-Mbit memory blocks are respectively arranged in the areas (2, 3), (3, 1), (3, 2), and (3, 3) in the second row group Ban kl. Although each 3 2-M b i t memory block is rectangular, the second bank group Bank 1 composed of four memory blocks has a non-rectangular shape different from the conventional bank group. The first control -15- 200405360 block is arranged on the area (2, 2) surrounded by BankO of the first row and Bankl of the second row. The third row Bank2 and the fourth row Bank3 are arranged in the same manner as the first row Bank0 and the second row Bank1. The second control block is arranged on the area (2,5) surrounded by the third row Bank2 and the fourth row Bank3. Each memory block contains a pair of X-decoders along the X-axis and Y-decoders along the Y-axis. Each 32-Mbit memory block that belongs to the same bank and is vertically adjacent to each other will share an X-decoder. Xin arranges a plurality of pads along the center of the semiconductor memory chip between the first bank Bank0 and the second bank Bank1 and between the third bank Bank 2 and the fourth bank Bank 3 . That is, a bank is composed of four 3 2-M bit memory blocks and its shape is non-rectangular. FIG. 10 is a schematic plan view showing the relationship between the semiconductor memory chip and a conventional packet according to the third embodiment of the present invention in FIG. 9 which will satisfy the conventional packet size. ^ Figures 1 1 A and 1 1 B are schematic plan views showing the relationship between a semiconductor memory chip and a packet obtained by changing the positions of the first and second control blocks according to the third embodiment of the present invention. As shown in FIG. 11A, the first control block is arranged on the area (2, 1) and the second control block is arranged on a different area (2, 6) from the array of FIG. At the same time, as shown in Figure 11B, the first control block can be arranged on the area (2, 3) and the second control block can be arranged on the area (2, 4). According to the third embodiment of the present invention-16-200405360, each of the memory banks BankO to Bank3 is non-rectangular and the semiconductor memory chip meets the conventional packet size, so that it is not necessary to expand when applying the same rules The X-axis of the packet allows the semiconductor memory chip to have an increased storage capacity. Since the memory banks are manufactured in a non-rectangular shape instead of a regular rectangular shape, a semiconductor memory wafer having an increased storage capacity can satisfy a conventional packet size. Therefore, a semiconductor memory chip having high efficiency can be manufactured at a low cost. An array composed of a plurality of pads, power lines, and data lines to be used in the above structure will be described below. Fig. 12 is a schematic plan view showing the interconnection structure between the power supply lead frames and the pads in Fig. 6 which are to be wire-bonded to each other according to the second embodiment of the present invention. Symbols la, lb, and lc represent lead frames for VSS and symbols 2a, 2b, and 2c represent lead frames for VDD. Meanwhile, the symbol 3 represents a pad and the symbol 4 represents a wire. Generally speaking, SDRAM has package pins consisting of three pairs of VDD and VSS. As shown in Fig. 12, the power supply lead frames are arranged on the left and right sides and the middle portion of the semiconductor memory chip. The lead frames 1 b and 2 b positioned on the middle portion of the semiconductor memory chip are formed by wiring the lead frames to the X-axis in a bidirectional manner to join three pairs of V D D and V S S. In Figure 6, it is not necessary to form a lead frame power drain between the areas (2a, 3a) and (2b, 3b) and between the areas (2a, 4a) and (2b, 4b). . At the same time, the above-mentioned lead frame can be applied to the embodiments of Figs. 3-17-200405360 and Fig. 9. Each power line arranged at the wafer level in the wafer is constructed in a flat screen pattern above each memory block of the wafer. If the power lines or signal lines are arranged between the output lines of the Y-decoder, each power line or signal line can be connected between the first control block and the second control block. Therefore, it is not necessary to form each power line or signal line between the areas (2a, 3a) and (2b, 3b) and between the areas (2a, 4a) and (2b, 4b), so that it can be reduced to Space occupied by each pad and control block. Fig. 13 is a schematic plan view showing the arrangement of data lines in Fig. 6 according to the second embodiment of the present invention. Generally speaking, the data lines of the memory array are connected to the sense amplifier in the Y-decoder. The data lines for each memory bank are combined into a common data line. At this time, in order to reduce the data delay caused by the electric wire, the left data line 7 a of each memory bank is connected to a left data pad, and the right data line 7 of each memory bank is connected. b Connect to a data pad on the right. Since the semiconductor memory chip has a non-rectangular shape including a planar surface, a semiconductor memory device having an increased storage capacity can be applied to a conventional package without developing an improved design rule. That is, the semiconductor memory chip can be provided at low cost. At the same time, since there is no need to expand its packet size, that is to say its X-axis explicitly in order to obtain a semiconductor memory chip with high storage capacity, there is a reduction in the ratio between the X-axis and the Y-axis on the semiconductor memory chip Effect. Therefore, the number of wafers available from a wafer is increased. -18- 200405360 In addition, since the number of x-decoders used for each memory bank can be reduced, the area occupied by each X-decoder can be reduced. Although the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and structure of the scope of the patent application as defined below. (V) Brief Description of the Drawings The above and other objects, features, and advantages of the present invention will become more apparent from the following description of the preferred embodiments in conjunction with the accompanying drawings. Figure 1 is a plan view showing a standard memory bank in a semiconductor memory chip. Figure 2 is a plan view showing the relationship between a semiconductor memory wafer with an increased size and a conventional packet. FIG. 3 is a schematic plan view showing a 5 1 2 -Mbit DDR SDRAM chip according to the first embodiment of the present invention. Figure 4A is a schematic plan view showing the relationship between a 5 1 2-M b i t semiconductor memory chip with a conventional bank array and a conventional packet. Figure 4B is a schematic plan view showing the relationship between a 5 1 2-M bit semiconductor memory chip having a banked array according to the present invention and a conventional packet. Figures 5A and 5B are planes showing the relationship between the semiconductor memory chip and the packet obtained by changing the positions of the 48-M bit memory block and the control block in the first embodiment of the present invention. schematic diagram. FIG. 6 is a schematic 200405360 diagram showing a semiconductor memory chip according to the second embodiment of the present invention, that is, a 5 1 2-Mbit DDR SDRAM chip. FIG. 7 is a schematic plan view showing a relationship between a semiconductor memory chip and a conventional packet according to the second embodiment of the present invention which will satisfy the conventional packet size. Figures 8A and 8B are schematic plan views showing the relationship between the semiconductor memory chip and packets obtained by changing the position of each control block in Figure 7.
第9圖係用以顯示一種根據本發明第三實施例之5 1 2 -Mbit DDR SDRAM晶片的平面示意圖。 第1 〇圖係用以顯示第9圖中根據本發明第三實施例之半 導體記憶體晶片與一習知封包之間關係的平面示意圖。 第1 1 A和1 1 B圖係用以顯示該半導體記憶體晶片與藉由 改變根據本發明第三實施例中第一和第二控制區塊之位置 所得到封包之間關係的平面示意圖。FIG. 9 is a schematic plan view showing a 5 1 2 -Mbit DDR SDRAM chip according to a third embodiment of the present invention. Figure 10 is a schematic plan view showing the relationship between the semiconductor memory chip and a conventional packet according to the third embodiment of the present invention in Figure 9. 11A and 11B are schematic plan views showing the relationship between the semiconductor memory chip and packets obtained by changing the positions of the first and second control blocks according to the third embodiment of the present invention.
第1 2圖係用以顯示第6圖中相互間將要根據本發明第二 實施例作佈線接合之各電源引線框架與各襯墊間之互連結 構的平面示意圖。 第1 3圖係用以顯示第6圖中根據本發明第二實施例之資 料線排列的平面示意圖。 主要部分之代表符號說明 1 a，2 a，3 a V S S用引線框架 1 b，2b，3b VDD用引線框架 3 襯墊 4 電線 -20- 200405360 7a，7b 資料線 10 半導體記憶體晶片 12 襯墊 13 控制區塊 20 封包 22 記憶體排組陣列 3 0 空間 B a n k 0 - 3 記憶體排組 MB，MB_0- 1 1 記憶體區塊Fig. 12 is a schematic plan view showing the interconnection structure between the power supply lead frames and the pads in Fig. 6 which are to be wire-bonded to each other according to the second embodiment of the present invention. Fig. 13 is a schematic plan view showing the arrangement of data lines according to the second embodiment of the present invention in Fig. 6. Description of main symbols 1 a, 2 a, 3 a Lead frame for VSS 1 b, 2b, 3b Lead frame for VDD 3 Pad 4 Electric wire-20- 200405360 7a, 7b Data line 10 Semiconductor memory chip 12 Pad 13 Control block 20 Packet 22 Memory bank array 3 0 Space B ank 0-3 Memory bank MB, MB_0- 1 1 Memory block
UMB 單位記憶體區塊UMB unit memory block