JPH0278268A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the reduction of power consumption by a method wherein an ERAM is composed of a rectangular semiconductor chip, where a bonding pad is provided to each side of the chip and a first and a second memory group are arranged sandwiching a row decoder in between them. CONSTITUTION:An external terminal P is provided to all the sides of a rectangular SRAM semiconductor chip. A memory cell array MARY divided into 32 parts is arranged on the center of the chip, and row decoder R-DC is positioned between centered MARYs 15 and 16. A word driver WDDR is provided between divided MARYs respectively. R-DC selects two MWLs from main word lines MWL on the direction of an address signal. A load circuit LD is provided to the upper end of each MARY, and a column switch CSW and a column decoder CDC are provided to the lower end. By the structure and the layout as mentioned above, the current flowing from LD to MARY is reduced to 1/32 and power consumption is made to decrease.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device equipped with a static random access memory.

[Conventional technology]

Static random access memory (SRAM)
(T'Q), a memory cell is arranged at the difference between a complementary data line (referred to as a complementary data line or complementary data line) and a word line. The memory cell is
A flip-flop circuit and two transfer MISFE'r (insulated gate field effect transistors) each have one semiconductor region connected to a pair of input/output terminals of the flip-flop circuit. The flip-flop circuit includes, for example, two driving MISFETs and two high resistance load elements. In order to reduce the area occupied by the memory cell, the high-resistance load element is formed of a polycrystalline silicon film into which impurities that reduce the resistance value of the element are not introduced or are slightly introduced. The gate electrode of each transfer MISFET of the memory cell is connected to a word line. The other semiconductor regions of the transfer MISFETs are respectively connected to complementary data lines.

A plurality of memory cells are arranged in the direction in which the complementary data lines extend and in the direction in which the word lines extend, forming a memory cell array. A word driver circuit and a row decoder (X decoder) circuit for selecting a desired word line from a plurality of word lines formed in the memory cell array are arranged at one end of the memory cell array. At the other end of the memory cell array, a column switch for selecting a desired complementary data line from a plurality of complementary data lines formed in the memory cell array and a column decoder circuit for controlling the column switch are arranged. In this case, the complementary data line is connected to the common data line via a column switch. That is, a column switch is interposed between the complementary data line and the common data line.

The information of the memory cell is transferred from the complementary data line to the sense amplifier through the column switch and the common data line, and the sense amplifier amplifies the information of the memory cell, that is, 1" information or 10" information. This amplified information is output to the outside of the SRAM from an external output terminal through an output signal line (data bus).

Note that SRAM is described, for example, in Kaigaru Micro Devices, No. 5, 1986, pages 77 to 93.

[Problem to be solved by the invention]

The inventor has determined that 256 (Kbit)
High-speed MO8 with large capacity like configuration 1 (Mbit)
Prior to the development of the SRAM type SRAM, we studied the SRAM and found that the following problems occurred.

1. The sealing method of SRAM is DILP (D
ual-In Line Package),
S OJ (Smail 0utlineJ-bend
Resin sealing such as package) is the mainstream.

In large-capacity SRAMs that employ this type of sealing method, the shape of the semiconductor chip is, for example, s, xsxl.
s, 2xc pieces! ] It becomes a slim rectangle. When simply forming a large capacity SRAM of 1 (Mbit) on this semiconductor chip, 2048 sets of complementary data lines are arranged in the long side direction, 512 word lines are arranged in the short side direction,
A memory cell array (memory mat) can be configured by arranging memory cells at the intersection between the two. In the SRAM configured in this manner, when one word line is selected, 2048 memory cells are simultaneously selected. Therefore, current flows into the 2048 memory cells from the load circuit (load MISFET) that constitutes the load of the complementary data line. This causes a problem in that the power consumption of the SRAM increases.

Further, it is difficult for the row decoder circuit that selects a desired word line from the plurality of word lines to drive 2048 memory cells substantially simultaneously at a time. For this reason, a so-called divided word line method is adopted. As a result of basic research by the present inventor, the number of memory cells that can be selected by - word lines is 128. The above-mentioned divided word line method is to divide a word line connected to a memory cell into multiple sub-word lines to form sub-word lines, place a word driver circuit for each sub-word line, and connect the word line via the main word line. This is a method in which the driver circuit is controlled by a row decoder circuit. The row decoder circuit is arranged at the end of a memory cell array divided into a plurality of parts. In the SRAM configured in this manner, the main word line extends from the farthest end of the memory cell array to the opposite farthest end, so the main word line becomes relatively long. Therefore, the fF raw capacitance f (load capacitance) coupled to the main word line and the parasitic resistance (load resistance) of the main word line are very large, resulting in a problem that the operating speed of the SRAM decreases. arise.

2. In the SRAM, 512 words a (actually sub-word lines) need to be arranged in the short side direction of the semiconductor chip. However, since the shape of the semiconductor chip becomes slim as described above, a problem arises in that the size of the semiconductor chip in the short side direction is considerably restricted when the word lines are arranged.

3. In the SRAM, external terminals (ponding pads) are arranged along opposite short sides of the semiconductor chip.Address signals, data output signals, power supply, etc. are applied to the external terminals.

However, since the shape of the semiconductor chip becomes slim as described above, a problem arises in that all of these external terminals cannot be arranged along the short sides of the semiconductor chip. In addition, if the semiconductor chip has a slim shape and the row decoder circuit is arranged at the end of the memory cell array as described above, the address signal external terminals are arranged at the other end opposite to the row decoder circuit. The distance between the two becomes longer. In other words, the distances between each address signal external terminal and the row decoder circuit are not uniform. In this case, it is necessary to match the timing at which each address signal is transmitted to the row decoder circuit, resulting in a problem that the operating speed of the SRAM decreases.

4. In the SRAM, the information of the memory cell is transmitted from complementary data lines (one set of complementary data lines consists of a non-inverted data line and an inverted data line) provided for each data line. It is output to the common data line via the column switch. The column switch is composed of a transmission gate circuit composed of complementary MO8FETs, and is controlled by a column decoder circuit. Dimension between complementary data lines.

Although the method can be made extremely small by increasing the integration of memory cells, two (one set) of column switches and two (one set) column decoders are required within the dimension between one set of complementary data lines. A problem arises in that it is very difficult to place the circuit.Also, if the spacing between complementary data lines is determined by the size of the column switch and column decoder circuit, the spacing between the complementary data lines will become large, making it difficult to integrate. A problem arises in that the degree of deterioration decreases.

The SRAM reads 4 [bits] in one information read operation.
] adopts a multi-bit method that outputs information.

That is, in one read operation, 4 (bits) of information are output in parallel. In an SRAM, an output transistor for outputting information to the outside is formed so that its driving capability is considerably larger than that of a transistor forming an internal circuit of the SRAM. For this reason, when 4 [bit] worth of output transistors are driven at one time in the information continuous operation, large noise is generated in the reference potential (circuit ground potential).This noise causes the reference potential of the SRAM to be Since the input signal level of the input stage circuit in the SRAM is floated compared to an external reference potential, the margin of the input signal level of the input stage circuit in the SRAM becomes small, causing a problem that malfunctions are likely to occur. A problem arises in that the standard level cannot be compensated for.

An object of the present invention is to provide a technique that can reduce power consumption of SRAM.

Another object of the present invention is to provide a technique that can reduce the power consumption of an SRAM, reduce the load capacitance and load resistance of word lines, and increase the operating speed.

Another object of the present invention is to provide a technology that can reduce the power consumption of an SRAM, increase its operating speed, and increase its integration.

In particular, another object of the present invention is to provide a technology that can achieve high integration by reducing the size of data lines in the -f direction in an SRAM.

Another object of the present invention is to provide a technique that can alleviate restrictions on the placement position of external terminals of an SRAM.

Another object of the present invention is to provide a technique that can make the length of signal lines uniform in an SRAM and increase the operating speed.

Another object of the present invention is to provide a technique that allows high integration of SRAM. In particular, another object of the present invention is to provide a technology that can reduce the column decoder area and achieve high integration in SRAM.

Another object of the present invention is to reduce noise generation and
The objective is to provide technology that can prevent malfunctions.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

Among the inventions disclosed in this application, typical ones are briefly explained below.

In an SRAM, a memory cell array is divided into at least 32 parts in the direction in which word lines extend, and a row decoder circuit is arranged in the center.

In the SRAM, a column switch, a column decoder circuit, etc. are arranged at one end of each divided memory cell array.

External terminals are arranged on each of the four sides of a rectangular semiconductor chip constituting the SRAM, and a row decoder circuit is arranged in the center of the semiconductor chip.

In an SRAM, two sets of column switches are controlled by one column decoder circuit.

In a multi-hit SRAM, the length of each common data line or each output signal line is changed.

[Effect]

According to the above-mentioned means, the amount of current flowing from the load circuit to the memory cell can be reduced to 1/32, so that the SR
The power consumption of AM can be reduced, the length of the main word line can be halved, and the load capacitance and load resistance can be reduced, so the operating speed of SRAM can be increased. .

Furthermore, since the SRAM can minimize the number of column switches, column decoder circuits, etc.4), it is possible to reduce the size in the extending direction of the complementary data line and achieve high integration. .

Since each side of the semiconductor chip can be effectively used, restrictions on the arrangement positions of external terminals can be relaxed. Further, since the length of the address signal line connecting the external terminal for each address signal and the row decoder circuit can be shortened, the operating speed of the SRAM can be increased.

Since the number of column decoder circuits can be reduced, the SRAM can be highly integrated by an amount corresponding to the area thereof.

Furthermore, according to the above-mentioned means, the load capacitances and/or load resistances of the individual common data lines or the individual output signal lines are made to be different from each other, so that the output timings for outputting each information are made to be different from each other. become. This makes it possible to disperse the noise and reduce its value, thereby making it possible to prevent malfunctions of the SRAM.

[Embodiment] The present invention will be described below based on an embodiment in which the present invention is applied to a 1 (Mbit) large-capacity, high-speed MO8 type SRAM having a 256 [Kbitl x 4 [bit] configuration.

In the following drawings for explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

An embodiment of the present invention: 256 (Kbit) x 4
(bit) Configuration No. 1 (Mbit) (7) S RA
M i:g It is shown in Figure 1 (layout diagram of a semiconductor chip). That is, the main circuit blocks shown in the figure are drawn according to their actual arrangement.

The SRAM of this embodiment is sealed with a resin sealing method such as DILP or SOJ, so as shown in FIG.
．． It is formed into a slim rectangular semiconductor chip of about 15 x 15.21 cm2). Although not particularly limited, in this embodiment, the semiconductor chip is composed of an n-type semiconductor substrate made of single crystal silicon. A p-type well region is formed in a predetermined main surface portion of the semiconductor chip (for example, a region where an n-channel MISFET is to be formed).

In addition, when a semiconductor chip is comprised of an n-type semiconductor substrate, for example, an n-type well region method (an n-type well region is formed in an n-type semiconductor substrate) or a twin-well method (
An n-type well region and a p-type well region are formed in a semiconductor substrate).

External terminals (ponding pads) P are arranged in areas along each side of the periphery of the semiconductor chip, that is,
External terminals P are arranged on all four sides of the semiconductor chip.

External terminals P-A0 to P-A1. are bonding pads to which address signals A0 to A0, , are applied from outside the SRAM, and external terminals P-C8
This is a bonding pad to which a chip select signal C8 is applied from outside. The external terminal P-OE is a bonding pad to which an output enable signal OE is applied from outside the SRAM, and the external terminal P-WE is a bonding pad to which an output enable signal OE is applied from outside the SRAM.
This is a bonding pad to which write enable A/signal WE is applied from outside M. External terminal P-I10°~P
-I104 is the input/output data signal I10. This is a bonding pad to which steps 104 are applied. That is, external terminal P-I10. ~P-I 104 is applied with a data signal to be supplied to the SRAM from outside the SRAM. Also, when reading data from SRAM,
From the SRAM internal circuit to the above external terminal P-I101-P
-I10. A data signal is applied to the head. In other words, these external terminals P-I10. ~P-I 104 is commonly used for input signals and output signals. External terminal p-vcc
x.

P-vccz is a bonding pad to which a power supply voltage, for example, a circuit operating potential of 5 [V] is applied from outside the SRAM, and external terminals P-Vss1* and P-Vss* are S
A reference voltage is supplied from outside the RAM, for example, the ground potential of the circuit is 0 [■
] is applied to the bonding pad.

As shown in FIG. 1, the external terminals P-A0 to P-A are arranged along the opposing long sides of the semiconductor chip, respectively, and the short side on the right side.

External terminal P-C8, external terminal P-OE, external terminal P-W
Each of E is arranged along the left short side. External terminal P-I10. ~P-I 10. are arranged along the lower long side and the left short side.

External terminals P-Vcc1+P-Vcc* are arranged along the right short side. The external terminal P-VCCI is for the internal circuit, and the external terminal P-vccz is for the output buffer circuit. That is, the external terminal P-VCCI is coupled to internal circuits such as a sense amplifier via a power supply wiring (not shown), and supplies a power supply voltage to these internal circuits. On the other hand, the external terminal P-vccz is connected to the data output buffer DoBn via a power supply wiring (not shown).
(n=1 to 4), and supplies a power supply voltage to these. This makes it possible to reduce the transmission of power supply voltage fluctuations caused by the operation of the data output buffer to the internal circuitry. These external terminals P-VCCI and P-VCC2 are connected to one inner lead for the power supply' voltage by newly developed double bonding.

Similarly, external terminal P V881 * P-v s s
x is located along the left short side. External terminal P
-V3Si is for the internal circuit, and external terminal P-v882 is for the output buffer circuit. That is, the external terminal P-vs
st is connected to an internal circuit such as a sense amplifier via a power supply wiring (not shown), and connected to an external terminal p-vast.
is coupled to the data output buffer DoB via power supply wiring, also not shown. As a result, the internal circuit is supplied with the reference voltage from the external terminal P-VBBl, and the data output sofa is supplied with the reference voltage from the external terminal P-VBBl.
A reference voltage should be supplied from VB82. These external terminals P Vsst and P -Vssz are connected to the reference voltage inner lead by double bonding.

A memory cell array MARY is arranged in the center of the semiconductor chip. As shown in FIG. 1, this memory cell array MARY is arranged along the long side from the left side to the right side of the figure (hereinafter referred to as the column direction).
It is divided into 32 parts like RYO-MARY31. 2048&l memory cells are arranged in the arrangement direction of the memory cell array M A RY (substantially in the extending direction of the word cells).

In each divided memory cell array MARY, 64 (2048/32 division=64) memory cells are arranged in the column direction. Basically, the optimal number of memory cells that can be selected by one word line is about 128, but in order to improve safety, in this example, 64
Individually.

Details of the memory cell array MARY are shown in Figure 2 (■ in Figure 1).
(enlarged layout diagram of the part) and FIG. 3 (enlarged layout diagram of the part ■ in FIG. 2).

As shown in FIG. 2 and FIG.
Since the J configuration is adopted, it is further divided into four in the column direction. In other words, each divided memory cell array MAR
Y (for example, MARYO) is composed of four unit memory cell arrays MARY (MARYO, to MARYO,). Unit memory cell array MARY (for example, M
In ARY O+), 16 (64/4 division=16) memory cells are arranged in the column direction.

Divided individual memory cell arrays MARYO to MAR
A sub-word line SWL is configured to extend in the column direction on Y31. 512 subwords 1IisWL are arranged in the row direction, and one main word line MWL is provided for four subwords @SWL. That is, four sub-word lines SWL are regarded as one set, and this one set can be selected by one main word line MWL. Therefore, main word line MWL
128 lines are arranged in the row direction on one side of a row decoder circuit R-DC to be described later.

Individual unit memory cell array MARYnm (n=0 to 3
1. Complementary data lines DL (d+, dt) are configured to extend in the row direction above (m=1 to 4, the same applies hereinafter). In the unit memory cell array MARYnm, 16 memory cells are arranged in the extending direction of the sub-word line SWL, so 16 sets of complementary data lines DL are arranged in the column direction.

Divided memory cell array MARYn (n=0 to 31
, hereinafter the same), the 16th divided memory cell array MARY15 and the 17th divided memory cell array MAR
A row decoder circuit (X decoder circuit) is connected to Y16.
R-DC is located. Row decoder circuit R-DC
are divided memory cell arrays MARYO~MARY
15, divided memory cell array MARY16 to M
The main word lines MWL each extend on ARY31.
and configured to select it. That is, the row decoder circuit R-DC has 256 lines (128 lines x 2) connected to it.
Two main word lines MWL designated by the address signal are selected from IMW L, and the remaining main word lines are rendered unselected. In this case, one main word line is selected from 128 main word lines, and a total of two main word lines MWL are selected. In this embodiment, the row decoder circuit R-DC includes:
Address signals predecoded in advance by a plurality of predecoder circuits, that is, selection signals obtained by predecoding, are supplied, thereby selecting two desired main words #MWL. In Figure 1,
A predecoder circuit that predecodes address signals A and A, and a predecoder circuit that predecodes address signals A and A are illustrated as PDs.

An address signal is supplied to the predecoder circuit PD via an address buffer circuit. In FIG. 1, there are four address buffer circuits AD6 to AD.

is exemplified. The selection signal (predecode signal) obtained by the predecoder circuit PD is sent to the row decoder circuit R- through the signal line Adl illustrated in FIG.
Supplied to DC.

Since the row decoder circuit R-DC is placed almost in the center of the chip, the length of the signal line that transmits the selection signal from the predecoder circuit PD to the row decoder circuit can be made almost the same, which reduces the operating speed of the SRAM. You can improve your performance.

The right side or left side of each divided memory cell array MARYn, that is, the divided memory cell array M ARY
A word driver circuit WDDR is provided between n. Since word driver circuit WDDR is arranged for each divided memory cell array MARYn, word driver circuit WDDRO to word driver circuit WD
There are 32 pieces arranged up to DR31. Each word driver circuit WDDRn (n=o to 31, the same applies hereinafter) is connected to a row decoder circuit R-DC via a main word line MWL.
It is connected to the. Each word driver circuit WDDRn is connected with a plurality of sub-word lines SWL, as shown in FIG. 3 and FIG. It is configured to select a sub word line. In other words, this SRA
M uses a divided word line system.

As shown in FIGS. 1 and 41, a data line load circuit (load circuit) LD is arranged at the upper end of each divided memory cell array M A RY n.

Load circuit LD is provided corresponding to divided memory cell array MARYn.

Therefore, in this embodiment, 32 load circuits L
A DO-LD 31 is arranged. Each load circuit LDn
(n=0 to 31, same below) is complementary data line DL
is set to a predetermined level (for example, high level), and the potential of the complementary data line DL is set in accordance with the information from the memory cell during the operation of extracting information from the memory cell or during the operation of writing information to the memory cell. It is configured to set the potential according to the potential or information to the memory cell. The load circuit L D'n is basically composed of an n-channel MISFET whose source region is connected to each data line d, , d of complementary data iDL. This n channel M
A power supply potential VCC is supplied to the drain region of the ISFET via a power supply wiring.

As shown in FIGS. 1 to 41, a column switch C8W and a column decoder circuit CDC are arranged at the lower end of each divided memory cell array MARYn.

Column switch C8W is divided memory cell array M A
Column switch csw corresponding to RY n.

32 pieces from C3W31 to C3W31 are arranged. Each column switch C3Wn (n=0 to 31) has four unit column switches C3Wn as shown in FIG.
The unit column switch C8Wnm corresponds to the above-described unit memory cell array MARYnm. Furthermore, since the unit memory cell array MARYn1yl has 16 sets of complementary data lines, the unit column switch C8Wnm is configured by 16 column switch circuits C8W accordingly. Each column switch circuit C8W has one switch arranged for each data line d+, dt of complementary data iDL, as shown in the 41st cell. That is, a set of complementary data i! 1li1DL has two switches (one set) arranged. In this embodiment, each switch is composed of a p-channel MISFET and an n-channel MISFET. That is, the column switch circuit C8W has an n-type #MISFETQ! in which the respective source and drain regions are connected to each other.
(or Q, ) and p-channel MISFETQ+ (or Q
4) consists of a CMO8 transmission gate circuit.

Column switch C8W selectively connects the complementary data line to common data line I10. in accordance with a selection signal from column decoder circuit CDC. ~I10. join to. The column decoder circuit CDC includes a divided memory cell array MARYO-
There are actually 32 decoders C corresponding to MARY31.
It can be considered that it is composed of DC0 to CDC31. Furthermore, each decoder CDCn (n = O
~31) are four unit column decoders CDCnm (n=o~31, m=1) according to the unit memory cell block.
~4) can be considered as one. Each of the unit column decoders CD Cn rn described above substantially includes a plurality of decoder circuits (logic circuits).
It can be considered that it is composed of In this embodiment, one decoder circuit is provided for two column switch circuits. Therefore, one unit column decoder circuit CDCnm is composed of eight decoder circuits as shown in FIG. As shown in the 41st prisoner, the column switch circuit receives the selection signal YSL from the corresponding decoder circuit.

Controlled by YSL. The selection signal YSL is a selection signal for controlling the n-channel MI 5FET of the column switch circuit C8W, and the selection signal YSL is a selection signal for controlling the p-channel MISFET of the column switch circuit C8W.

As mentioned above, the column decoder circuit CDC is composed of 32 column decoder circuits CDC0 to CDC31 arranged corresponding to the divided memory cell arrays (see FIG. 1). The decoder circuit is configured to select two sets of complementary data-DL substantially simultaneously, that is, to control four switches (two sets of column switch circuits C5W) (Fig. 4<A). ].

The column switch circuit C8W has complementary data mDL.
and complementary common data 1I10. Since the SRAM of this embodiment has a 4bit configuration, the common data i%1ilI10 is formed by four sets of complementary common data lines I10. The complementary common data 11M110 is configured to transfer the information of the memory cells transmitted to the unit column switch C8Wnm to the complementary common data line 110.The complementary common data 11Ml10 has a length corresponding to two unit memory cell arrays MARYnm. extends in the column direction, is drawn out in the row direction from between unit memory cell arrays MARYnm, and is connected to the sense amplifier SA (see FIGS. 2 and 3).

As shown in FIGS. 1 to 41, the sense amplifier SA is arranged at the lower end of the memory cell array MARY with a column switch C8W and a column decoder circuit CDC interposed therebetween. As can be seen from FIG. 2, each complementary common data line connects four unit memory cell arrays MARY
It is common to nm. Therefore, the number of sense amplifiers is half of the unit memory cell array. Sixty-four sense amplifiers SA are arranged in the column direction. Common data aX10+ is connected to the sense amplifier 5A-1. The sense amplifier 5A-2 has a common data line I10. is connected. Sense amplifier 5A-
Common data +18 for 3! l103 is connected. Sense amplifier 5A-4 has common data @ I 10
．． is connected.

In this embodiment, during a read operation, four sense amplifiers 5A-1 to 5A out of 64 sense amplifiers SA
-4 is designated by the address signal and is activated, and the remaining 601fi sense amplifiers are deactivated. As a result, the sense amplifier SA, which has been activated, amplifies the memory cell information transmitted by the common data 1I10, and supplies this to the data output buffer DoB via the output signal 1IBDBus. In this embodiment, two main word lines are selected by the row decoder circuit R-DC, and the word driver circuit W D D Rn
One sub-word line is selected by word driver circuit WDDRn from among a plurality of sub-word lines coupled to these main words @MWL via. Therefore, during a successive read operation or a write operation, memory cells coupled to a selected sub-word line in one divided memory cell array M A RY n are simultaneously selected. Therefore, the four sense amplifiers to be operated are sense amplifiers 5A-1 to 5A-4 coupled to the one divided memory cell array MARYn.

As described above, the common data line I10 is formed in common for two unit memory cell arrays MARYnm adjacent to each other (two unit memory cell arrays MARYnm).
(formed with a length corresponding to ARYn). As shown in FIG.
, I10! .

They are arranged in the order of Ilo, , Ilo. As a result, for example, the complementary common data line 101 is connected to the "C*" memory cell array MARYI, , M through the column switch.
Complementary data lines in any one unit memory cell array of ARYI, MARYO, MARYO are coupled. Also, complementary common data line I10. Also, unit memory cell array MAR is connected via column switch.
Y1. .

Complementary data lines in any one of the unit memory cell arrays MARYI, MARYO, MARYO are coupled. In this case, FIG.

As shown in FIG. 4 (8), the common data line I
10. ．． I10. are coupled to different (close to each other) complementary data lines via different column switches, so the same complementary data line is never coupled to the complementary common data lines I10+ -l10x.

In this embodiment, although not particularly limited, the inner common data I%l I/ot and the outer common data wirework 104 have substantially the same wiring length. That is, in each of the complementary common data 1I10, the parasitic capacitance and the parasitic resistance are made equal to each other. Of course, complementary common data MI1
0. ~l104 may be changed so that the values of their parasitic capacitances and parasitic resistances are changed.

Accordingly, the operation timings of the data output buffers may be made different from each other to reduce the occurrence of noise.

In the SRAM of this embodiment, input/output is performed in units of 4 bits as described above, and 4 bits are input/output to a memory cell selected from one unit memory cell array MARYnm.
Please note that bit data is not input or output. That is, in this embodiment, two bits are selected from one unit memory cell array MARYnm, and two bits are selected from another unit memory cell array M ARYn m in the same divided memory cell array M ARY n as this unit memory cell array MARYnm. Two bits are selected and data is input/output to and from these four bits. For example, in FIG. 3, 2 bits (10+,
l10x) is selected, and this unit memory cell array MA
A unit memory cell array MARY that is not adjacent to RYO,
2 bits from O4 (Ilo, .

I104) is selected and these 4 bits (I101
~l104), data is input and output. This makes it possible to prevent each decoder circuit constituting the column decoder circuit CDCtt from becoming larger (longer) in the direction in which the complementary data lines extend, and to prevent the short sides of the chip from becoming larger.

The sense amplifier SA has an output signal line (data bus) D.
It is connected to a data output buffer circuit DoB via a bus. The data output buffer circuit is a data output buffer circuit DoB placed on the left short side in FIG.
1. Data output buffer circuit Do placed on the lower long side
B2~DoB.

It consists of four pieces. Data output buffer circuit Do
A sense amplifier 5A-1 is connected to B through an output signal line DBusl. A sense amplifier 5A-2 is connected to the data output buffer circuit DOB2 via an output signal line DBus2. A sense amplifier 5A-3 is connected to the data output buffer circuit DoB1 with an output signal 1DBus3 interposed therebetween. A sense amplifier 5A-4 is connected to the data output buffer circuit D o B a with an output signal line DBus4 interposed therebetween.

The output signal lines DBus are arranged from the inside to the outside [output signal lines DBusl, DBus2 . DBus3.

They are arranged in the order of DBus4. As a result, the inner output signal line DBusl has a shorter wiring length than the outer output signal line DBus4. In other words, the output signal line DBus
The parasitic capacitance and parasitic resistance are configured to increase from the inside to the outside.

The output signal line DBus is configured to drive an output transistor that outputs information of the memory cell. FIG. 4(B) shows an embodiment of the data output buffer DoB. In the figure, data output buffer DoB
1 is shown as a representative. For other data output buffers DoB2 to DoB4, data output buffer D
Since it has the same configuration as oB1, it is not shown. The data output buffer Doll includes an amplification stage AP to which a complementary signal is supplied via the output signal line DBusl, and a NAND game that receives the complementary signal amplified by the amplification stage AP.
(NAND) NOI, NO2 and inverter IVO
I, lVO2 and output transistor Qo 1 =
Qo 2 . The output transistors QO11QO2 are connected in series between the power supply lines VCC and VO3, and when the control signal OC is at a high level, the output transistors QO11QO2 are supplied to the data output buffer via the output signal line DBus1. It is turned on and off according to complementary signals. This allows the output signal line DBus
The information according to the signal of 1 is the bonding pad P-I10.
It is output via ゜. When the control signal OC is set to low level, the output transistor Q. 1°QO2 are both turned off. As a result, the bonding pad P-I10. It becomes possible to transfer input data supplied from the outside to a data buffer (not shown).

The control signal OC is a control signal WE supplied from outside the SRAM.

A timing signal generation circuit (not shown) is formed based on OE and C8.

As shown in FIG. 3, the unit memory cell array MA
The complementary common data line I10 is connected between RY n m.
A small space has been created for pulling out. Utilizing this space, unit memory cell array M A
The reference potential wiring V88 is drawn out in a letter-shaped shape from the reference potential wiring V88 extending in the column direction between RY n m and the column switch C8W, and the drawn out reference potential wiring Vs
s and the p-type well region (the connection part is simplified and
Indicated by a mark: so-called well control). The unit memory cell array M A RY' is formed in the p-type well region, and the connection with the reference potential wiring V88 can stably maintain the potential of the p-type well region. In other words, in the SRAM of this embodiment, the number of information write operations of the memory cell can prevent malfunctions of information continuous output operations, or the latch-up phenomenon peculiar to CMO8 can be prevented.

The memory cells arranged in the unit memory cell array M A RY n m are arranged at the intersection of one set of complementary data lines DL and one sub-word line SWL, as shown in the 41st cell. The memory cell includes a flip-flop circuit that holds information and a transfer MISF circuit in which one semiconductor region is connected to each of its pair of input/output terminals.
It is composed of E T Q t + and Qtt.

The transfer MISFETQt is composed of an n-channel MISFET. Each gate electrode of the transfer MISFETQt is connected to the same sub-word line swL.

The other semiconductor region of the transfer MISFET Qt is connected to the data line d1 or d of the complementary data line DL.
).

The flip-flop circuit consists of two driving MISF E
It is composed of T Q d + and Q d t and two high resistance load elements R7 and R1. Drive MIS
FETQd is composed of an n-channel MIsFET. The high-resistance load element R is made of a polycrystalline silicon film into which no or a small amount of impurities are introduced to reduce the resistance value in order to reduce the area occupied by the memory cell. Note that instead of the high resistance load element R, a p-channel M
The memory cell may be configured with an ISFET. The source region of the driving MISFET Qd is connected to the base S potential VSS. The drain region of the driving MISFET Qd is connected to one end side of the transfer MISFETQt and the high resistance load element R. The other end of high resistance load element R is connected to power supply potential VCC.

The specific structure of the SRAM memory cell constructed in this manner is shown in FIG. 5 (a plan view of the memory cell) and FIG. 6 (a plan view of the memory cell in a predetermined manufacturing process).

As shown in FIGS. 5 and 6, the SRAM memory cell is formed on the main surface of a p-type well region 2 formed on the main surface of an n-type semiconductor substrate 1. As shown in FIGS. Each element (MISI"ET) of the memory cell is surrounded by a field insulating film (silicon oxide film) 3 formed on the main surface of the well region 2,
Its area is defined. Although not shown, a p-type channel stopper region is formed on the main surface of the well region 2 under the field insulating film 3.

The memory cell transfer MISFET Qt mainly includes a well region 2, a gate insulating film (not shown), a gate electrode 5,
It is composed of a pair of n+ type semiconductor regions 6 that are source regions or drain regions.

The well region 2 of the transfer MISFET Qt is used as a channel forming region.

As the gate insulating film, use a silicon oxide film formed by oxidizing the main surface of the well region 2.

The gate electrode 5 is made of high melting point metal silicide (MoSil, TiSil, TaSi) on a polycrystalline silicon film.
It is composed of a composite membrane that formed a membrane (L, WSil). Further, the gate electrode 5 is made of a polycrystalline silicon film, a high melting point metal silicide film, or a high melting point metal (Mo, Ti, Ta).
, W), or a composite film in which a high melting point metal film is formed on a polycrystalline silicon film. MISFET for transfer
The gate electrode 5 of Qt is configured integrally with the gate electrode 5 of other transfer MI 5FETQt arranged in the column direction, and constitutes a sub-word line (SWL) 5. The gate electrode 5 and the sub-word edge 5WL5 are the first
It is formed in the second layer gate wiring formation process. Note that in FIGS. 5, 6, and 7, which will be described later, the gate wiring in the first layer and the gate wiring in the second layer are shown in dotted patterns to aid understanding of the drawings.

The semiconductor region 6 is a region defined by the field insulating film 3 and is formed on the main surface of the well region 2 on both sides of the gate electrode 5. The semiconductor region 6 is doped with n-type impurities (A
s ) by ion implantation. Although not shown in detail, the semiconductor region 6 has a low impurity concentration on the channel formation region side. The low impurity concentration portion of the semiconductor region 6 is formed by introducing n-type impurities (P) by ion implantation similarly to the semiconductor region 6 with a high impurity concentration. This semiconductor region with a low impurity concentration is a so-called LDD (Lightly Doped Dra).
in) Configure a transfer MISFETQt of the structure.

MI 5FETQd for driving memory cells is MI for transfer.
Like the SFETQt, it mainly consists of a well region 2, a gate insulating film, a gate electrode 5, and a pair of n+ type semiconductor regions 6 that are source or drain regions.

One end of the gate electrode 5 of the driving MISFETQdI and both ends of the gate electrode 5 of the driving MI 5FETQd are connected to a predetermined semiconductor region through the connection hole 4 formed in the gate insulating film. 6 is directly connected.

The high resistance load element (R) 8 of the memory cell is connected to the gate electrode 5
It extends thereon with an interlayer insulating film (not shown) interposed therebetween. The high resistance load element (R+) is a transfer MISFET
Qd, is arranged on the gate electrode 5 of Qd. The high resistance load element (ut) 8 is arranged on the gate electrode 5 of the transfer MISFETQa. The high resistance load element 8 is connected to a predetermined gate electrode 5 and semiconductor region 6 through a connection hole 7 formed in the interlayer insulating film. The high resistance load element 8 contains impurities (As, P or B) that reduce the resistance value.
It is composed of a polycrystalline silicon film in which no or a small amount of silicon is introduced. Regions where impurities are not introduced or where some impurities are introduced are indicated by the symbol R in FIG.
It is within the area surrounded by the dotted chain line.

A power supply wiring (Vcc) 8 is integrally formed with the high resistance load element 8 . The impurities are introduced into this power source 8.

The high-resistance load element 8 and the lead wire 8 are formed in the second layer gate wiring formation process.

A glabella insulating film (not shown) is interposed on the high resistance load element 8 and the power supply wiring 8, and the main word line (MWL) is connected to the main word line (MWL).
10, a reference voltage wiring (Vsg) 10 and an intermediate conductive layer 10 are configured.

The reference voltage wiring 10 is connected to the semiconductor region 6, which is the source region of the driving MISFETQd, through a connection hole 9 formed in the interlayer insulating film.

The intermediate conductive layer 10 is connected to the MISFE for transfer through the connection hole 9.
It is connected to the other semiconductor region 6 of TQt. The intermediate conductive layer 10 has a complementary data line DL formed thereon.
It is configured to prevent wire breakage due to the step shape.

The main word 1O is formed between the reference voltage wiring 10 and the intermediate conductive layer 10 so as to extend in the column direction by utilizing the space between them.

Main word line 10, reference voltage wiring 10 and intermediate conductive/
! Reference numeral 10 indicates a step of forming a first layer wiring, for example, an aluminum film or an aluminum film containing a predetermined additive (Cu or Si) is formed.

A complementary data line (DL:d) is formed on the main word line 10, the reference voltage line 10, and the intermediate conductive layer 10 with a glabella insulating film (not shown) interposed therebetween.

d, ) 12 extends in the row direction. Complementary data line 1
The individual data lines d, d, of 2 are once connected to the intermediate conductive layer 10 through the connection hole 11 formed in the interlayer insulating film, and are connected to the transfer MISFET through this intermediate conductive layer 10.
It is connected to the other semiconductor region 6 of Qt. The complementary data line 12 is formed in the second layer wiring formation process, and is formed of, for example, the same aluminum film as described above.

Next, the specific configuration of the SRAM column switch C8W is shown in FIG. 7 (a plan view of the main part of the column switch) and the
This will be briefly explained using one prisoner. FIG. 7 is slightly scaled down compared to FIGS. 5 and 6. Furthermore, the area corresponding to the two sets of complementary data lines on the left side of FIG.
- The eye wiring te1a and the second layer wiring RA12 are shown, and the area corresponding to the two sets of complementary data lines on the right side is shown with only the second wiring layer 12 removed.

As shown in FIG. 7, the complementary data line DL shown on the upper side is a reference voltage wiring (Vss) 1 for supplying power to the well region 2.
2 and is connected to column switch C8W.

The column switch csw includes four p-channel MISFETs Q9. Q-, Qa, Q- and 4 n f Janel MI 5FETQ! ,Qs,
Qt and Qs are arranged. Upper two p-channel MISFETQI.

Q4 and upper two n-channel MISF B
TQl-Qs constitutes a column switch C8W for connecting complementary data wlDL and common data 1I10I or 110s. Lower two p-channel MIs
5FETQ+ -Q4 and bottom two n-channel MIs
SFETQ*, Qs are complementary data iDL and common data 1I10. Alternatively, configure a column switch C8W for connection to l104.

Total 8 MISFETQ of column switch C8W
I-Q4- Ql, Qa, Qt, Qs, Qt.

The extending direction of each gate electrode of Q is arranged to be orthogonal to the extending direction (row direction) of complementary data RDL. Column switch C arranged like this
For the 8W MISFET, the size of the MISFET and the number of MISFETs can be set independently of the data line dlpd* interval.

In this embodiment, as described above, two sets of complementary data lines (
dt, dt-dt, dt) Four column switches C8W (2 sets of 1 total of 8 MISFETs) are arranged within the interval of DL. These four column switches C8W, that is, the two sets of complementary data lines DL, are
Selection signal YSL from one column decoder circuit CDC
It is configured to be driven by. The selection signal YSL is 4
n-channel MI 5FETQ*, Qs, Qt
, Qs. This selection signal YSL is applied to the inverter circuit (n-channel MISFETQs and p-channel MISFET
SFETQ) is converted into a selection signal YSL by the four p-channel NMI 5
It is configured to control FETQ+, Q4, Qa, and Qa.

In this way, in the SRAM, by controlling two sets of column switch circuits (or two sets of complementary data lines DL) with one decoder circuit, the column decoder circuit CD
Since the number of decoder circuits configuring C can be reduced, the degree of integration can be improved by an amount corresponding to the area. Note that four sets (or eight sets, 16 sets, etc.) of column switch circuits may be controlled by one decoder circuit.

Next, the information read operation of the SRAM will be briefly explained.

First, when an external address signal is determined, one main word @MWL designated by the address signal ADI is selected by the row decoder circuit R-DC shown in FIGS. 1 and 41.

At the same time as this main word line MWL is selected, the address signal AD2 input to the word driver circuit WDDR shown in FIGS. 3 and 4 is determined, and one of the four sub-words 1SWL is selected. Ru. In other words, 64 in the memory cell array M A RY n divided into 9
memory cells are selected.

Next, the selected memory cell transfers its information to the complementary data line DL. When this sub-word line SWL is selected, a current continues to flow directly from the load circuit LD to the memory cell.

The information transferred to the complementary data line DL is transmitted to the common data line I10 through the column switch circuit,
It is further transmitted to sense amplifier SA. sense amplifier S
A person amplifies the level of the common data line 10 and outputs the amplified information to the data output buffer circuit DoH through the output signal line D Bus. Data output 777
The 7-circuit DoB further amplifies the output information and performs waveform shaping, and then drives the output transistor. Information is output to the outside by driving this output transistor.

In this way, the SRAM memory cell array MARY is divided into 32 columns, and the row decoder circuit R-
By arranging the DC, the amount of current flowing from the load circuit LD to the memory cell can be reduced to 1/32nd, thereby reducing the power consumption of the SRAM and reducing the length of the main word line MWL by 2. Since the parasitic capacitance and parasitic resistance coupled thereto can be reduced by a factor of 1, the operating speed of the SRAM can be increased. Note that in the present invention, the SRAM memory cell array MARY may be divided into 64 or more divisions.

In addition, in the above configuration, a column switch C8W and a column decoder circuit CDC1 sense amplifier SA are provided at one end (lower side in FIG. 1) of each divided memory cell array MARY.
By arranging etc.

Since the number of column switches C8W, the number of column decoder circuits CDC, the number of sense amplifiers SA, etc. can be kept to a minimum, the size of the complementary data line DL in the extending direction can be reduced and high integration can be achieved. Note that when the above-mentioned peripheral circuit is arranged in the center of the memory cell array MARY, twice the area of the peripheral circuit is required.

Furthermore, by arranging the external terminals P on the four sides of the rectangular semiconductor chip constituting the SRAM, each side of the semiconductor chip can be effectively used.
It is possible to relax the restrictions on the location of the . Furthermore, the interval between inner leads (not shown) connected to the external terminals P via bonding wires can be relaxed.

In addition, by arranging external terminals P on the four sides of the rectangular semiconductor chip that constitutes the SRAM, and arranging the row decoder circuit R-DC in the center of the semiconductor chip, each external terminal P to which an address signal is applied, for example, Since the distance between -A and the row decoder circuit R-DC can be configured to be the shortest distance, the wiring length of the address signal line can be shortened. Further, the wiring length between each address signal line can be made uniform. As a result, the operating speed of the SRAM can be increased.

In addition, in a (multi-bit system) SRAM that simultaneously outputs multiple pieces of information in a continuous information output operation, by changing the wiring length for each common data line I10 or each output signal line DBus, it is possible to Since the parasitic capacitance and parasitic resistance of the data line 110 or the individual output signal lines DBus are different, and the timing of outputting information is different, noise generated in the reference potential VS8 or the power supply potential Vcc can be dispersed. As a result, malfunctions can be particularly prevented in the input stage circuit of the SRAM. In other words, it is possible to compensate for the standard level of the SRAM input signal. Note that in this embodiment, the output signal line DBus is formed of the second wiring layer 12.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is applicable not only to a single SRAM but also to logic circuits (MOS type or bipolar transistor type) and SR
It can be applied to a semiconductor integrated circuit device having AM.

Further, the present invention provides 128 [Kbit]
It can be applied to an SRAM with a t':J configuration or a large capacity SRAM of 4 [Mbit] or more.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having an SRAM, power consumption can be reduced and operation speed can be increased. Furthermore, it is possible to prevent malfunctions of the SRAM.

Furthermore, the semiconductor integrated circuit device 1 having the SRAM can be highly integrated.

Further, it is possible to increase the operating speed of a semiconductor integrated circuit device having an SRAM.

Further, the number of column decoder circuits in a semiconductor integrated circuit device having an SRAM can be reduced, and higher integration can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of an SRAM that is an embodiment of the present invention, FIG. 2 is an enlarged layout diagram of the SRAM shown in FIG. 1, and FIG. 3 is an enlarged layout diagram of the SRAM shown in FIG. 41 is an equivalent circuit diagram of the main part of the SRAM, FIG. 4 is a circuit diagram showing an embodiment of the data output buffer DoB, and FIG. A specific plan view of the memory cell; FIG. 6 is a plan view of the memory cell shown in FIG. 5 in a predetermined manufacturing process; FIG. 7 is a plan view of a main part of the SRAM column switch. . Agent: Patent attorney Katsuo Ogawa. Figure 6

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a static random access memory includes: a rectangular semiconductor chip; bonding pads formed on each side of the semiconductor chip; and bonding pads formed in the center of the semiconductor chip. means for connecting at least some of the bonding pads to the selection means; first and second memories formed on the semiconductor chip so as to sandwich the selection means therebetween; It is characterized by having a cell group. 2. The semiconductor integrated circuit device includes: a first memory cell array having a plurality of memory cells and data lines close to each other; a second memory cell array having a plurality of memory cells and data lines close to each other; a first column switch means coupled between the data line of the first memory cell array and the first common data line; and a first column switch means coupled between the data line of the first memory cell array and the second common data line. Column switch means of the E2 coupled; third column switch means coupled between the data line of the second memory cell array and a third common data line; and the data line of the second memory cell array. and a fourth common data line; and a first column switch means coupled to the first and second column switch means.
control means, and a second column switch coupled to the third and fourth column switch means.
and an output means that is coupled to the first, second, third and fourth common data lines and outputs a plurality of output signals corresponding to data on these common data lines substantially simultaneously. It is characterized by having.