JP2003017582A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contract the layout area of a sense amplification block in a semiconductor block. SOLUTION: One dispersion area 10b out of two dispersion areas 10a, 10b which two shared switch transistors constituting a shared switch circuit have is shared as one dispersion area 10b of two pre-charge transistors constituting a bit line pre-charge circuit. The other dispersion area 10c of the pre-charge transistor is extended in the same method as a sense amplification array, and shared as the dispersion area 10c of the other adjacent pre-charge transistor. Thus, an element separation area need not be provided, and the layout area of the sense amplification block can be contracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a high-capacity dynamic RAM (random access memory) or a system LSI equipped with the dynamic RAM, which is further highly integrated, large-scaled, and low-cost. Technology that is effective in reducing power consumption and power consumption.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device, a memory including a plurality of word lines and bit lines arranged orthogonally to each other and a large number of memory cells connected to these word lines and bit lines in a matrix. There is a dynamic RAM having a cell array as a constituent element. In recent years, high integration and large scale of dynamic RAM and the like have been remarkable, and various techniques for further promoting this are being developed.

In a semiconductor memory device, since the increase of the chip area greatly affects the increase of the chip cost, the problem of how to efficiently perform the chip layout and reduce the chip area is the most important issue in the development of the semiconductor memory device. This is one of the important issues. In particular, since the memory cell peripheral circuits such as the sense amplifier and the sub-word driver, which are circuits that depend on the layout pitch of the memory cells, are configured by arranging a large number of the same circuits as the memory cells,
Very high percentage of chip area.

However, the reduction of the area, the reduction of the power consumption, and the speeding up of the operation are in conflict with each other. For example, if bit line precharge / equalize transistors are arranged on both sides of the shared switch transistor, that is, on the memory cell side and the sense amplifier side in order to precharge the bit line pair at a high speed, the layout area is increased for this high speed operation. Will tend to increase.

In the semiconductor memory device, the data stored in the memory cell is read out through the bit line and amplified by the sense amplifier. FIG. 4 is a circuit diagram of a sense amplifier and its associated shared switch circuit, a memory cell block precharge / equalize circuit, a sense amplifier block bit line precharge / equalize circuit, and a column switch circuit. In the figure, reference numeral 1 denotes a latch type sense amplifier, which has a function of amplifying the data read from the memory cell to the bit line pair BIT and XBIT. A column switch circuit 2 connects the bit line pair BIT and XBIT to the data lines DQ and XDQ, and plays a role of transferring the data amplified by the sense amplifier 1 from the bit line pair to the data line pair. Shared switch circuits 3 and 4 connect the bit line pair in the memory cell and the bit line pair in the sense amplifier block.
Is a bit line precharge / equalize circuit in the sense amplifier which short-circuits the bit lines BIT and XBIT in the sense amplifier 1 to equalize each other and precharges them to a predetermined potential. 6 and 7 are bit lines in the memory cell block ( BITL, XBITL), (BITR, XBIT
This is a bit line precharge / equalize circuit in a memory cell block for shorting (R) to equalize and precharge to a predetermined potential.

The operation of the semiconductor memory device configured as shown in FIG. 4 will be described below. First, the read operation of the data stored in the memory cell will be described. The bit lines in the memory cell block and the sense amplifier block are equalized and precharged by the precharge / equalize circuits 6 and 7 in the memory cell block and the bit line precharge / equalize circuit 5 in the sense amplifier. The potentials of the bit line pairs are set to the same potential as a preparation for reading the data from. After that, the shared switch 3 or 4 on the side opposite to the memory cell side for reading is controlled from ON to OFF (for example, when the memory cell for reading data is connected to the bit line BITR, the shared switch 3 is turned off). Then, the word line, which is the gate of the memory cell connected to the bit line, is activated, and the accumulated charge stored in the memory cell capacitor is transferred to the bit line BITR. The shared switch circuit 4 remains ON, and the data read from the memory cell to the bit line BITR is read to the bit line BIT in the sense amplifier via the shared switch 4. After that, the minute potential difference read to the bit line pair BIT, XBIT in the sense amplifier is amplified by the ON operation of the sense amplifier 1.

Subsequently, the column switch circuit 2 is controlled to be in the ON state by the column selection signal Y, and the bit line pair BI.
T, XBIT and the data line pair DQ, XDQ are connected,
The data amplified on the bit line pair BIT and XBIT in the sense amplifier is transferred to the data lines DQ and XDQ.

Thereafter, in order to enter the standby state, the potential of the word line, which is the gate electrode of the memory cell transistor, is lowered to turn off the memory cell transistor, hold the accumulated charge, and then turn off the sense amplifier 1. Then, the shared switch 3 on the side that has been turned off is controlled to be turned on, and the precharge / equalize circuits 5, 6 and 7 are controlled to be turned on again to perform the equalization and precharge of the bit line to perform the memory cell operation. Bit line pair BIT as a preparation for reading data from
L, XBITL, BIT, XBIT, BITR, XBI
The potential of TR is set to the same potential.

FIG. 7 is a conventional example showing the layout of a semiconductor memory device. In the circuit configuration in the sense amplifier block shown in FIG. 4, two shared switch circuits 4 are provided.
And bit line precharge in two memory cell blocks
A general transistor layout layout with the equalizer circuit 7 is shown. The layout arrangement of the shared switch circuit 3 and the bit line precharge / equalize circuit 5 in the memory cell block is also the same as this transistor arrangement. In FIG. 7, 10 is a diffusion region of the MOS transistor, 11 is a gate electrode of the MOS transistor,
Reference numeral 13 represents an element isolation region.

In the conventional layout diagram shown in FIG. 7, the shared switch circuit 4 and the bit line precharge / equalize circuit 7 in the memory cell block are formed on different diffusion regions, and between the diffusion regions of the respective transistor elements. The element isolation region 13 is formed. Therefore, in the sense amplifier block, three diffusion regions must be laid out by only one shared switch circuit 4 and one memory cell block bit line equalize circuit 7.
In the conventional layout diagram of FIG. 7, contacts to wirings face each other in the diffusion region of the bit line precharge / equalize circuit 7 in the sense amplifier and the diffusion region of the shared switch circuit 4. In the diffusion region where the contact is made, it is necessary to separate the gate electrode from the contact, to make an overlap margin between the contact and the diffusion region, etc., so that a wide diffusion region is required. It is necessary to secure it.

[0011]

However, in the transistor layout arrangement of the conventional semiconductor memory device described above, in the layout of the shared switch transistor and the precharge transistor, the separation of the gate electrode and the contact, the contact and diffusion region overrun. There is a drawback that the layout area of the sense amplifier block becomes large because the wrap distance and the element isolation region must be secured between the two diffusion regions. It is difficult to form an element isolation region in a small area in a semiconductor process, and it is difficult to lay out each functional circuit in the conventional structure in the sense amplifier block of a small area required in the future large-scale integrated circuit. Is.

As a result, in the semiconductor memory device in which a large number of sense amplifiers are arranged as described above, the chip area and the chip cost increase. Therefore, reducing the layout area of the sense amplifier in which a large number of the same circuits are arranged similarly to the memory cell greatly contributes to the reduction of the chip size and exerts a great effect on the cost reduction. The reduction of the layout area is one of the most important issues in the design and development of semiconductor memory devices.

The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a semiconductor memory device in which a shared switch circuit and a precharge circuit in a sense amplifier block are efficiently laid out in a small area. Especially.

[0014]

In order to achieve the above object, according to the present invention, a diffusion region of a shared switch transistor which constitutes a shared switch circuit, a precharge transistor which constitutes a bit line precharge / equalize circuit and an equalize circuit. The diffusion area of the transistor is shared to reduce the area.

That is, a semiconductor memory device according to a first aspect of the present invention includes a memory cell array in which a plurality of memory cells connected to a bit line are arranged, and a plurality of sense amplifiers provided for each pair of the bit lines. A row of sense amplifiers, a row of precharge transistors for precharging the bit line pairs, and a row of shared switch transistors for connecting the bit line pairs to corresponding sense amplifiers. A shared switch transistor array is provided, and one diffusion region of the precharge transistor and one diffusion region of the shared switch transistor corresponding to the precharge transistor are shared.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the other diffusion region of the precharge transistor is shared with another diffusion region of another precharge transistor. Is characterized by.

According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the gate electrode of the shared transistor and the gate electrode of the precharge transistor corresponding to the shared transistor extend in the same direction. It is characterized by being arranged.

According to another aspect of the semiconductor memory device of the present invention,
A memory cell array in which a plurality of memory cells connected to a bit line are arranged, a sense amplifier row in which a plurality of sense amplifiers provided for each pair of bit lines are arranged, and a precharge circuit for precharging the bit line pair. A pre-charge transistor row in which a plurality of charge transistors are arranged, an equalize transistor row in which a plurality of equalize transistors that equalize the bit line pair are arranged, and a plurality of shared switch transistors that connect the bit line pair to a corresponding sense amplifier. A shared switch transistor row is arranged side by side, and one diffusion region of the equalizing transistor and one diffusion region of the shared switch transistor corresponding to the equalizing transistor are shared.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the other diffusion region of the equalizing transistor and one diffusion region of the precharge transistor corresponding to the equalizing transistor are made common. It is characterized by

According to a sixth aspect of the invention, in the semiconductor memory device according to the fourth aspect, the other diffusion region of the precharge transistor is shared with the other diffusion region of the other precharge transistor. Characterize.

The invention according to claim 7 is the same as claim 4,
Alternatively, in the semiconductor memory device described in the paragraph 6, the gate electrode of the shared transistor and the gate electrodes of the equalize transistor and the precharge transistor corresponding to the shared transistor are arranged so as to extend in the same direction.

According to an eighth aspect of the present invention, in the semiconductor memory device according to the second or sixth aspect, the diffusion region shared by the precharge transistor and another precharge transistor is the same as the sense amplifier row. And the common diffusion region of the precharge transistor is connected to a precharge potential supply wiring arranged in the metal wiring layer through one contact.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the eighth aspect, the contact is arranged near an end of the gate electrode of the precharge transistor, and the gate electrode of the precharge transistor is
It is characterized in that it is bent so as to bypass the contact in the vicinity of the contact.

According to a tenth aspect of the present invention, the first and second aspects are provided.
In the semiconductor memory device described in item 2, 4 or 7, the precharge transistor and the shared switch transistor have different gate oxide film thicknesses.

The invention according to claim 11 is the same as claim 1,
In the semiconductor memory device described in 2, 4, or 7, the threshold voltage of the precharge transistor is lower than the threshold voltage of the shared switch transistor.

The invention according to claim 12 is the same as claim 1,
The semiconductor memory device according to 2, 4, or 7 is characterized in that a gate length of the precharge transistor is shorter than a gate length of the shared switch transistor.

According to a thirteenth aspect of the present invention, in the semiconductor memory device according to the fourth or seventh aspect, the equalizing transistor has a gate length shorter than a gate length of the precharge transistor.

According to a fourteenth aspect of the present invention, in the semiconductor memory device according to the fourth or seventh aspect, the precharge transistor is turned on after the equalizing transistor is turned on.

According to a fifteenth aspect of the present invention, in the semiconductor memory device according to the first or fourth aspect, the diffusion region shared by the precharge transistor and another precharge transistor is the sense amplifier column and the word line. It is characterized in that it is connected to a wiring for supplying a precharge potential arranged in the metal wiring layer at the position of the intersection with the drive circuit.

According to a sixteenth aspect of the present invention, in the semiconductor memory device according to the first or fourth aspect, the diffusion region shared by the precharge transistor and another precharge transistor is the sense amplifier column and the word line. It is characterized in that it is connected to a wiring for supplying a precharge potential arranged in the metal wiring layer at a position of an intersection with the lining region.

According to a seventeenth aspect of the present invention, in a semiconductor memory device, a memory cell array in which a plurality of memory cells connected to a bit line are lined up, and a plurality of sense amplifiers provided for each pair of the bit lines are lined up. A shared switch in which a sense amplifier row, a precharge transistor row in which a plurality of precharge transistors for precharging the bit line pair are arranged, and a plurality of shared switch transistors in which the bit line pair is connected to a corresponding sense amplifier are arranged. A corresponding precharge transistor of the precharge transistor line is directly connected to each bit line pair, and the corresponding bit line pair is precharged from the precharge power supply via each precharge transistor. It is characterized by

As described above, the semiconductor integrated circuit according to the present invention has the following effects. That is, in a semiconductor memory device configured to amplify data read on a bit line by a sense amplifier, for example, a semiconductor memory such as a DRAM or a system LSI equipped with this semiconductor memory, particularly a large-capacity semiconductor memory device, the bit line One pair or two pairs of sense amplifiers are arranged in a layout, and a large number of sense amplifiers are arranged on a semiconductor chip. Therefore, the ratio of the sense amplifier area to the semiconductor memory device is large. Therefore, reducing the layout area of the circuit associated with the sense amplifier is effective in reducing the chip size of the semiconductor memory device. In order to reduce the area of this sense amplifier, a shared sense amplifier system is generally adopted in which one sense amplifier is laid out for the left and right bit line pairs of the sense amplifier, but in this shared sense amplifier system, Since one sense amplifier is provided for two pairs of bit lines, the number of sense amplifiers can be reduced by half and the area of the sense amplifier can be significantly reduced. However, in the shared sense amplifier system, two pairs of bit lines located on both sides of the sense amplifier share one sense amplifier, so when connecting one bit line pair to the sense amplifier, Because it needs to be separated
A transistor (shared switch transistor) that functions as a switch having this disconnection function is required between the bit line pair connected to the memory cell and the sense amplifier. It is necessary to arrange one shared switch transistor for each bit line, and four shared switch transistors are required for each sense amplifier. As described above, since it is necessary to arrange the same number of shared switch transistors as the number of bit lines, the number of shared switch transistors is very large, and the layout area becomes large. Here, before reading the data stored in the memory cell to the bit line, a precharge operation is carried out in which the potential of the bit line pair is set to the same potential. A precharge transistor for supplying the voltage is arranged. In order to speed up the precharge operation, a precharge transistor is often arranged also on the bit line on the memory cell side.

Here, in the invention described in claims 1 to 3, since the diffusion region of the shared switch transistor and the diffusion region of the precharge transistor are shared, the diffusion region of the shared switch transistor and the diffusion region of the precharge transistor are shared. It is not necessary to provide an element isolation region with the region, and the layout area of the sense amplifier block is significantly reduced. Therefore, the layout area of DRAM, system LSI, or the like in which a large number of sense amplifier blocks are arranged can be effectively reduced.

In particular, according to the second aspect of the invention, since the diffusion regions are shared by the plurality of precharge transistors, the number of connection contacts from the metal wire for supplying the precharge potential to the diffusion regions of the plurality of precharge transistors. Can be reduced. As a result, in a plurality of precharge transistors, there is no need to separate the gate electrode and the contact, overlap margin between the contact and the diffusion region, and the large diffusion region becomes unnecessary. Since it is not necessary to secure the isolation region, it is possible to significantly reduce the layout area.

Further, in the semiconductor memory device according to the present invention as defined in claims 4 to 7, in the shared sense amplifier system, when the equalizing transistors for equalizing the potentials of the bit lines are provided, the shared switch transistor and the equalizing transistor are connected. Since the diffusion regions are made common, it is not necessary to provide an element isolation region between the diffusion region of the shared switch transistor and the diffusion region of the equalize transistor, so that the layout area can be effectively reduced.

Particularly, since the other diffusion region of the equalizing transistor and one diffusion region of the precharge transistor are made common, the element is provided between the diffusion regions of the equalizing transistor and the precharge transistor. It is not necessary to provide an isolation region, and the layout area is further reduced.

According to the sixth aspect of the invention, since the diffusion regions of the plurality of precharge transistors are made common, the number of connection contacts from the metal wiring for supplying the precharge potential to the diffusion regions of the plurality of precharge transistors. Can be reduced. As a result, in a plurality of precharge transistors, there is no need to separate the gate electrode and the contact, overlap margin between the contact and the diffusion region, and the large diffusion region becomes unnecessary. Since it is not necessary to secure the isolation region, the layout area can be significantly reduced.

According to the eighth aspect of the invention, it is sufficient to secure only one connection contact from the metal wiring for supplying the precharge potential to the diffusion region shared by the plurality of precharge transistors. It is effective for reduction.

According to the ninth aspect of the invention, although the connection contact for connecting the metal wire for supplying the precharge potential to the diffusion region of the precharge transistor is arranged near the end of the gate electrode of the precharge transistor, Since the end portion of the gate electrode is bent so as to bypass the connection contact, a space between the connection contact and the gate electrode is secured, and a separate region for arranging the connection contact is not required. Moreover, since the connection contact can be provided in the empty area between the two precharge transistors, it is not necessary to enlarge the sense amplifier block, and the area can be reduced.

Further, the invention according to claim 10 has the following operation. The gate potential of the shared switch transistor is generally higher than the power supply potential of the sense amplifier, the precharge potential is about half the power supply potential of the sense amplifier, and the gate potential of the precharge transistor is the gate potential of the shared switch transistor. It doesn't have to be set as high. From this relationship, in the precharge transistor and the shared switch transistor, the voltage applied to the gate oxide film is lower in the former case, and the former gate oxide film thickness can be reduced. From the above, the gate oxide film thickness of the precharge transistor can be set thinner than the oxide film thickness of the shared switch transistor, so that the amount of current flowing through the precharge transistor can be increased,
The precharge operation can be speeded up.

Further, in the invention according to claim 11, since the threshold voltage of the precharge transistor is lower than the threshold voltage of the shared switch transistor, the amount of current of the precharge transistor is increased to speed up the precharge operation. be able to. Here, if the threshold voltage of the precharge transistor is set low, the OFF current of the precharge transistor when it is OFF increases, but the precharge transistor is always turned on when the semiconductor memory device is on standby.
Since it is in the N state, the problem that the standby current becomes too large does not occur. Further, even when the semiconductor memory device is operating, a current enough to destroy the data amplified by the sense amplifier does not flow, so there is no problem of malfunction of the semiconductor memory device.

In addition, according to the invention of claim 12, the gate length of the precharge transistor is set shorter than the gate length of the shared switch transistor.
The current amount of the precharge transistor is increased, and the precharge operation can be speeded up. Here, if the gate length of the precharge transistor is set to be slightly shorter, the OFF current when the precharge transistor is OFF increases, but the problems such as standby current and circuit malfunction do not occur as described above.

In addition, the invention according to claim 13 has the following operation. That is, during the precharge operation, the precharge transistor is turned on, and charging / discharging of the pair of two bit lines, which have been oscillating at the high level potential and the low level potential, respectively. Here, the timing at which the precharge transistor turns on will be described. The precharge transistor connected to the bit line of the low level potential is
Since the source potential is at a low level, the threshold voltage is low and O
The gate potential to turn on is low, it starts to turn on quickly, and the amount of transistor current is large. On the other hand, since the source potential of the precharge transistor connected to the high-level potential bit line is at the precharge level, the threshold voltage is high and the precharge transistor is turned on.
The gate potential is high, the ON delay is delayed, and the transistor current amount is small. Therefore, even if the bit line pair is short-circuited by the equalizing transistor, the precharge transistor that turns on earlier than the current flows from the bit line having the high level potential to the bit line having the low level potential is applied to the bit line having the low level potential. A large proportion of current is supplied from the charge power supply, resulting in a large current consumption from the precharge power supply. However, since the gate length of the equalizing transistor is shorter than the gate length of the precharge transistor, the amount of current flowing through the equalizing transistor increases. Therefore, the rate of charging / discharging the bit lines by precharging is reduced, and the rate of equalizing the potentials of the bit line pairs by the equalizing operation is increased. As a result, the current consumption from the precharge power supply is reduced and the low power consumption It becomes possible to use electricity.

According to the fourteenth aspect of the invention, the equalizing transistor is turned on first during the precharge operation.
Then, the potentials of the pair of bit lines are set to the same level, and then the precharge transistor is turned on to charge / discharge the precharge potential, so that the current consumption from the precharge power supply is reduced and low power consumption is achieved. Be promoted.

Further, in the invention according to the fifteenth and sixteenth aspects, for supplying the precharge potential to the position of the intersection of the sense amplifier row and the word line drive circuit or the position of the intersection of the sense amplifier row and the word line lining region. Since the connection contact that connects the metal wiring to the diffusion region of the precharge transistor is arranged, the number of connection contacts in the diffusion region of the precharge transistor is reduced. Therefore, there is no need to separate the gate electrode from the connection contact and to provide an overlap margin between the connection contact and the diffusion region, a wide diffusion region becomes unnecessary, and it is necessary to secure an element isolation region between the diffusion regions. Therefore, the layout area can be significantly reduced. Moreover, since a resistance is inserted in the current supply path from the precharge power supply to the bit line, and the precharge transistor substantially functions as an equalizing transistor, the rate of charge / discharge operation of the bit line pair by the precharge transistor is reduced. As a result, the rate of equalization of the potentials of the bit line pairs by the equalizing operation increases. Therefore, the current consumption from the precharge power supply is reduced, and the power consumption can be reduced.

In addition, in the seventeenth aspect of the present invention, since the diffusion layer of the shared switch transistor and the diffusion layer of the precharge transistor can be made common, an element isolation region is provided between the diffusion layers of both transistors as in the conventional case. No need. Moreover, since the diffusion layers of a plurality of precharge transistors can be made common, it is possible to reduce the number of connection contacts from the metal wiring having the precharge potential to this common diffusion layer. It is not necessary to take an overlap margin with and, and a wide activation area is unnecessary. Further, it is not necessary to secure the element isolation region between the diffusion regions.
Therefore, the layout area can be significantly reduced.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a dynamic RAM (semiconductor memory device) of the present invention or a DRAM on a system LSI equipped with this dynamic RAM.
The block block diagram of a core is shown. First, an outline of the configuration and operation of this dynamic RAM will be described. still,
In the circuit elements forming each block of FIG.
A transistor (collectively referred to as an insulated gate field effect transistor) is formed on one semiconductor substrate such as single crystal silicon. In the following drawings, the names of terminals and signal lines are used repeatedly as names of signals transmitted through these terminals or signal lines or their wirings, unless otherwise specified. In the circuit diagram below,
If the gate part of a transistor is shown by a thick line, the MOS transistor is a P-channel type MOS transistor, and if the gate part is shown by a thin line, it is an N-channel M transistor.
An OS transistor is shown.

In FIG. 1, the dynamic RAM is
Four large memory cell blocks MB0 as basic components
To MB3, and main word line drive circuit blocks MWDB0 to MWDB3 are arranged adjacent to them. Each of the large memory cell blocks MB0 to MB3 roughly includes 128 sub memory cell arrays arranged in a grid, and each of these sub memory arrays includes a memory including dynamic memory cells arranged in a grid. A cell block, a sub word line drive circuit including a unit sub word line drive circuit, a main word line generation circuit connected to the sub word line drive circuit to generate a main word line selection signal, a sense amplifier row, and a sense amplifier power supply. And a sense amplifier driver for supply. The sub memory cell array, the sub word line drive circuit circuits on both sides of the sub memory cell array, and the sense amplifier rows above and below the sub memory cell array are arranged to form a sub memory block. The sense amplifier driver is arranged at the intersection of the sub word line drive circuit and the sense amplifier row.
Then, sub memory blocks including the memory cells and peripheral circuits are arranged in a grid pattern. Further, main word lines generated by the main word line drive circuit are arranged in an upper layer of 128 sub memory cell arrays arranged in a matrix.

Hereinafter, the dynamic RA of this embodiment will be described.
An outline of the M chip layout will be described. In the following description regarding the layout, the upper and lower sides and the left and right sides of the respective arrangement planes of chips and the like are represented by the positional relationship of the corresponding layout drawings.

In FIG. 1, the dynamic RAM is
A device manufactured on the P-type semiconductor substrate PSUB will be described as an example. The dynamic RAM has a so-called LOC (Lead On Chip) form and includes a bonding pad for coupling the inner lead and the semiconductor substrate PSUB, an address input buffer, a data output buffer, and other control circuits. The peripheral circuit PC is arranged in a cross shape along the vertical and horizontal center lines of the semiconductor substrate PSUB. Further, a large memory cell block MB0 is arranged in the upper left portion of the semiconductor substrate PSUB, a large memory cell block MB1 is arranged in the upper right portion thereof, a large memory cell block MB2 is in the lower left portion thereof, and a large memory cell is in the lower right portion thereof. Each block MB3 is arranged. Main word line drive circuits MWDB0 to MWDB3 are arranged adjacent to the large memory cell blocks MB0 to MB3. In the present embodiment, the main word line drive circuits MWDB0 to MWDB
3 is arranged outside the semiconductor substrate PSUB of each of the large memory cell blocks MB0 to MB3. The number of the large memory cell blocks MB0 to MB3 and the positions of the main word line drive circuits MWDB0 to MWDB3 are not particularly limited. Also, the peripheral circuit PC is arranged in a cross shape,
This is also not particularly limited. Therefore, the LOC structure is not particularly limited, and a memory core in a system LSI equipped with a dynamic RAM may have no bonding pad and may be connected to a logic circuit section arranged on the same semiconductor substrate.

FIG. 2 shows the dynamic RAM of FIG.
3 is a block diagram showing an internal configuration of a large memory cell block MB0 included in FIG. FIG. 3 shows four adjacent sub-memory cell arrays SMA24, SMA25, SMA34, SMA3 forming the large memory cell block MB0 shown in FIG.
6 shows a partial block diagram of 6 and its peripheral circuits. 4, 5, and 6 are circuit diagrams of sense amplifier blocks having different configurations. FIG. 7 shows a layout layout of a conventional shared switch transistor and precharge / equalize transistor. 8, 9, and 10
11 and 11 are layout layout diagrams of the shared switch transistor and the precharge transistor in the present embodiment.

With these figures as the bottom, a large memory cell block MB0 which constitutes the dynamic RAM of this embodiment is formed.
The block configuration of the sub memory cell array, the specific configuration and operation of the memory cells and their peripheral circuits forming the sub memory cell array, and their characteristics will be described. still,
The description of the large memory cell block will be given by taking the large memory block MB0 as an example.
Since B1 to MB3 have the same configuration as this,
The description is omitted. Further, the following description regarding the sub memory cell array, the memory cell and the peripheral circuit will be given in the sub memory arrays SMA24, SMA25, SMA34, S
The MA 35 will be taken as an example, but the other sub memory cell arrays SMA00 to SMAF7 have the same configuration as this, and therefore the description thereof will be omitted.

In the large memory cell block MB0 of FIG. 2, the sub memory cell arrays are 128 sub memory cell arrays SMA arranged in a 16 × 8 matrix.
00 to SMAF. Further, in the peripheral portion of these sub memory cell arrays, sub word line drive circuits SWLB00 to SWLBF8 are provided above and below in the drawing.
However, the sense amplifier rows SAB00 to SABG7 are arranged on the left and right
Are placed. Sense amplifier drivers SDR00 to SDRG8 are arranged at the intersections of the sub word line drive circuits and the sense amplifier columns. In the large memory cell block MB0, the main word line is selected based on the main word line drive circuit MWDB selected based on the external row address, and the sub word line drive circuit S is selected.
WLB is selected and the sense amplifier driver S at each intersection
Each of the sense amplifiers in the sense amplifier row is driven by DR00 to SDRG8.

Next, four adjacent sub memory cell arrays SMA24 shown by hatching in FIG.
The block configurations of SMA 25, SMA 34, SMA 35 and their peripheral circuits are shown in FIG. 3 and will be described. Here, the sub memory arrays SMA00 to SMAF7 are provided with sub word line drive circuits SWLB24 and SWLB25 below and above the sub memory cell array SMA24, as represented by the sub memory array SMA24 in FIG. Sense amplifier columns SAB34 and SAB24 are arranged on the left and right sides of the cell array SMA24. Similarly, sub word line drive circuits SWLB25 and SWLB26 are provided under the sub memory cell array SMA25.
However, the sense amplifier rows SAB35 and SAB25 are arranged on the left and right, and the sub word line drive circuits SWLB34 and SWLB35 are provided above and below the sub memory cell array SMA34.
However, the sense amplifier arrays SAB44 and SAB34 are arranged on the left and right, and the sub-word line drive circuits SWLB35 and SWLB36 are provided under the sub-memory cell array SMA35.
Sense amplifier rows SAB45 and SAB35 are provided on the left and right. In addition, a sense amplifier driver is arranged in the area of the intersection of the sub word line drive circuit and the sense amplifier row. For example, as shown in FIG. 3, the sense amplifier driver SDR3 is provided at an intersection located between the two sub word line drive circuits SWLB25 and SWLB35 and between the two sense amplifier arrays SAB34 and SAB35.
5 are arranged.

FIG. 3 shows the sub memory cell array SMA24,
The block configuration around SMA25, SMA34, and SMA35 is shown. In the sub memory cell array SMA24, sub word lines are arranged parallel to the vertical direction of the drawing. In the figure, four pairs of bit lines (BITR0, XBITR0),
(BITR1, XBITR1), (BITL0, XBI
TL0) and (BITL1, XBITL1) are shown. Here, the number of bit lines is not particularly limited, but in the present embodiment, 256 bit line pairs (BITR0, X).
BITR0) to (BITR127, XBITR12)
7), (BITL0, XBITL0) to (BITL12
7 and XBITL 127) will be described. (Note that the inverted signal is represented by adding an X to the beginning of its code. This sub-memory cell array is not shown,
It includes 512 sub-word lines arranged in parallel in the horizontal direction of the figure and 256 bit line pairs arranged in parallel in the vertical direction. The number of word lines and bit lines is not particularly limited. At the intersections of these sub-word lines and bit lines, 512.times.256 dynamic memory cells composed of information storage capacitors and address selecting MOS transistors are arranged in a matrix.
As a result, each sub memory cell array SMA00 to SM
The AF 7 has a so-called dynamic storage capacity of 128 kilobits. Also, a large memory cell block MB
0 to MB3 is 128 kg x 128, that is, 16
The dynamic RAM has a memory capacity of 16 mega.times.4, that is, 64 megabits.

In FIG. 3, the sub memory cell array SM
A25 and a sub-memory cell array SMA35 sandwiched between the sense amplifier array SAB35 sense amplifier S
A30 is connected to the bit lines BITR0 and XBITR0 of the sub memory cell array SMA25, and at the same time, the bit lines BITL0 and XB of the sub memory cell array SMA35.
Connected to ITL0. Similarly, the sense amplifier array SAB
The sense amplifier SA31 that constitutes the bit line 35 includes bit lines BITR1 and XBITR of the sub memory cell array SMA25.
1 is connected to the sub memory cell array SMA3
5 bit lines BITL1 and XBITL1.

Further, the two sub word line drive circuits SWL
A sense amplifier driver SDR35 is arranged between B35 and SWLB25 and in the region of the intersection between the two sense amplifier arrays SAB35 and SAB34. The sense amplifier drive signals SAN3 and SAP3 generated by the sense amplifier driver SDR35 are input to all the sense amplifiers in the sense amplifier array SAB35 including the sense amplifiers SA30 and SA31. Further, in this embodiment, 128 memory cells are connected to each bit line.

Next, the structure and operation of each sense amplifier will be described. Each sense amplifier SA has a sense amplifier drive signal line SAN, SAP and a bit line pair BIT, XBI.
T is connected. Here, the sub memory cell array SAM
The operation when the data of the memory cell connected to the bit line BITR in the sub memory cell array SAM25 is read when the sub word line in 25 is activated will be described. When the sub word line in the sub memory cell array SAM25 is activated, the data stored in the memory cell connected to the bit line BITR is read to this bit line BITR, and the potential of the bit line BITR slightly changes. When the data stored in the memory cell is high level, the potential of the bit line BITR is slightly higher than the precharge potential, and when the data stored in the memory cell is low level, the potential of the bit line BITR is pre-charged. It becomes slightly lower than the charge potential. On the other hand, the bit line XBIT on the inverted signal side
The potential of R is maintained as the precharge potential. Then, the sense amplifier drive signals SAN2, SAN3, SAP are sent from the sense amplifier drivers SDR25, SDR35.
2, SAP3 is generated, the sense amplifier array SAB25,
All the sense amplifiers in the SAB 35 operate to amplify the bit line in the sense amplifier.

FIG. 4 shows a circuit configuration in the sense amplifier block. In the figure, 1 is a sense amplifier, and 2 is a column switch circuit for transferring the data transmitted to the bit lines BIT and XBIT in the sense amplifier to the data lines DQ and XDQ. 3 is a bit line BIT, X in the sense amplifier
BIT and bit line BI on the memory cell side located to the left of BIT
Shared switch circuit 4 for disconnecting TL and XBITL is also the bit lines BIT and XB in the sense amplifier.
IT and the bit line BIT on the memory cell side located to the right of IT
A shared switch circuit for disconnecting R and XBITR. These shared switch circuits 3 and 4 each include two shared transistors (3a, 3b), (4).
a, 4b). Further, in FIG. 4, 5 is a bit line precharge / equalize circuit 6 and 7 in the sense amplifier.
Is a bit line precharge / equalize circuit in the memory cell block, each including two precharge transistors (5a, 5b), (6a, 6b), (7a, 7b).
And one equalizing transistor 5c, 6c, 7c.

Here, the data amplification operation by the above-described sense amplifier will be described in detail with reference to the circuit diagram of FIG. First, by the memory cell block precharge / equalize circuits 6 and 7 and the sense amplifier bit line precharge / equalize circuit 5, bit lines BITL, XBITL, BITR, and XBITR in the memory cell block and bit lines BIT in the sense amplifier block. , XBIT are equalized and precharged, and the potentials of the bit line pairs are set to the same potential in preparation for reading data from the memory cell. At that time, the potentials of all the bit lines are set to the precharge potential.

After that, the shared switch opposite to the memory cell side for reading is turned from ON to OFF. Figure 3
As described above, when the memory cell for reading data is connected to the bit line BITR, the shared switch circuit 3 is turned off. Then, the sub-word line, which is the gate of the memory cell connected to the bit line, is activated, and the accumulated charge stored in the memory cell capacitor is transferred to the bit line. As described above, the sub memory cell SA
The sub word line in M25 is activated, and the bit line BIT
The data stored in the memory cell connected to R is read to the bit line BITR. As a result, the bit line BI
The potential of TR changes slightly and bit line XB on the inverted signal side
Since the potential of ITR is kept at the precharge potential,
A minute potential difference is generated between the two bit lines BITR and XBITR. Here, the shared switch circuit 4 holds the ON state, but the bit lines BITR and XB on the memory cell side are held.
In order to speed up the potential transfer between the ITR and the bit lines BIT and XBIT in the sense amplifier, or to completely transfer the potential amplified by the sense amplifier 1, it is used as the gate voltage of the transistors forming the shared switch circuits 3 and 4. Often uses a boosted potential. Then, the data read from the memory cell to the bit line BITR is read from the bit line BITR in the memory cell block to the bit line BIT in the sense amplifier via the shared switch circuit 4. Therefore, the bit line BIT in the sense amplifier also becomes slightly higher or lower than the precharge potential, and the bit line XBIT in the sense amplifier on the inverted signal side is held at the precharge potential. After that, the bit line pair B in the sense amplifier
The minute potential difference read out to IT and XBIT is the sense amplifier drive signal S generated by the sense amplifier driver.
The sense amplifier 1 operates by AN and SAP and starts amplification.

Thereafter, the bit line pair BI in the sense amplifier
The data amplified by T and XBIT is the column selection signal Y
By turning on the column switch circuit 2 with
Bit line pair BIT, XBIT and data line pair DQ, XDQ
Are connected to each other, and the data of the bit line pair BIT and XBIT are transferred to the data line pair DQ and XDQ and read out to the outside.

When the reading of data is completed, the potential of the word line, which is the gate electrode of the memory cell transistor, is lowered to bring the memory cell transistor into the standby state, the memory cell transistor is turned off, and the accumulated charge is held. Is turned off. Then, the shared switch circuit 3 on the side that was turned off is turned on to precharge
The transistors of the equalizing circuits 5, 6 and 7 are turned on again, the bit line pair is equalized and precharged, and the bit line pair (BITL, XBITL) is prepared in preparation for the subsequent reading of data from the memory cell.
The potentials of (BIT, XBIT) and (BITR, XBITR) are set to the same potential.

FIG. 5 is a circuit diagram of a sense amplifier block having a structure different from that of FIG. In the figure, the bit line precharge / equalize circuits 6 and 7 in the memory cell block of FIG.
(7a, 7b) only, the equalizing transistors 6c, 7c are not provided, and the precharge / equalize operation described above is performed by the precharge transistors (6a, 6b), (7a, 7b) only.

FIG. 6 also shows a circuit diagram having a structure different from that of the sense amplifier block shown in FIG. The bit line precharge / equalize circuit 10 in the memory cell block shown in FIG.
In 11, a single precharge transistor 10a, 1
1a and two equalizing transistors (10b, 10
c) and (11b, 11c) are provided, and the connection relationship between them is shown in FIG.
The equalization circuits 6 and 7 have a different configuration, and the precharge / equalize operation described above is possible with the circuit configuration of FIG.

The layout arrangement in this embodiment will be described below with reference to FIG. As already mentioned, FIG.
In the layout of shared switch transistors and precharge transistors, when the layout of transistors is similar to that of the conventional layout, the distance between the gate electrode and the contact, the overlap distance between the contact and the diffusion area, and the distance between the two diffusion areas. Therefore, the layout area of the sense amplifier block becomes large because it is necessary to secure the element isolation region. It is difficult to form an element isolation region in a small area in a semiconductor process, and each functional circuit is laid out in the conventional configuration in a sense amplifier block of a small area required in a large-scale semiconductor memory device in the future. It is difficult.

Therefore, for the two sets of sense amplifier blocks shown in FIG. 5, two shared switch circuits 4 and 2 are used.
Bit line precharge circuit 7 in each memory cell block
And are arranged in a layout as shown in FIG. In the layout arrangement shown in the figure, four shared switch transistors (two 4a and two 4b) are arranged vertically in accordance with the pitch of the bit lines, with the shared switch signal SH as a gate input. These shared switch transistors 4a, 4b, 4a, 4b have a common gate electrode 4g.
Of the two bit lines (BIT0, BITR0) and (XBIT0, XBIT0, X).
(BITR0), (BIT1, BITR1), (XBIT
1, XBITR1).

Further, with the precharge signal PR as a gate input, four precharge transistors in the memory cell block (two 7a and two 7b) are arranged vertically. These precharge transistors 7a, 7b
Has a common diffusion region 10c and diffusion regions 10b on both sides of the gate electrode 7g. The diffusion region 10b is shared with one diffusion region 10b of the shared switch transistors 4a and 4b. The common diffusion region 10c of the precharge transistors 7a and 7b is connected to the metal wiring 16 having the precharge potential VPRE via one contact 7c. The metal wiring 16 is arranged in the upper metal wiring layer. The gate electrode 4g to which the shared switch signal SH is input and the gate electrode 7g to which the precharge signal PR is input are arranged in parallel to each other in the same direction as the direction in which the sub word lines extend (vertical direction in the figure).
In FIG. 8, 15 is a memory cell plate electrode, 1
Reference numeral 4 is an inter-wiring isolation region that prevents interference between the memory cell plate electrode 15 and the metal wiring 16.

With the layout arrangement shown in FIG. 8, the shared switch transistors 4a and 4b and the precharge transistors 7a and 7b are adjacent to each other, as is apparent from comparison with the conventional example shown in FIG. Since the diffusion region 10b is shared, it is not necessary to use the element isolation 13 shown in FIG. 7 of the related art, and the area can be greatly reduced. Therefore, the areas of the shared switch circuit 4 and the memory cell block precharge circuit 7 in the sense amplifier block circuit shown in FIG. 5 can be significantly reduced, and the size of the semiconductor chip can be significantly reduced.

(Second Embodiment) A semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 9 shows a layout diagram of the semiconductor memory device according to the present embodiment. FIG. 9 also shows the layout arrangement of the shared switch circuit 4 and the bit line precharge circuit 7 in the memory cell block in the portion including the two sense amplifier block circuits shown in FIG. In the layout arrangement of FIG. 8 which is the first embodiment, the inter-wiring isolation region 14 is necessary, which hinders the area reduction. In FIG. 8, since the precharge transistor in the memory cell block is arranged beside the sub memory cell array, the precharge transistor is adjacent to the wiring layer which is the plate electrode of the sub memory cell array. However, the wiring layer that is the plate electrode of the sub memory cell array and the VPRE
There is a case where the height is close to that of the metal wiring of the above. Therefore, if they are very close to each other, the wiring layer that is the plate electrode of the sub memory cell array and the metal wiring of VPRE may be electrically short-circuited. Therefore, the inter-wiring isolation region 14 of FIG. 8 is required. Therefore, the present embodiment proposes a configuration that eliminates the area increase due to the inter-wiring isolation region 13.

In this embodiment, as in the first embodiment shown in FIG. 8, four shared switch transistors are arranged in accordance with the bit line pitch with the shared switch signal SH as the gate input. These shared switch transistors are BIT0-BITR0, XBIT0-X.
BITRO, BIT1-BITR1, XBIT1-XB
The transistors each having the ITR1 as the source-drain are arranged vertically. Further, similarly to FIG. 7, the precharge signal PR is used as a gate input, and BITR0, which is a diffusion region on one side of the shared switch transistor,
The precharge transistors in the memory cell block are arranged vertically with XBITR0, BITR1 and XBITR1 as a common diffusion region. At this time, the gate electrodes of the shared switch signal SH and the precharge signal PR are arranged in parallel in the vertical direction in the figure, which is the same direction as the sub word line.

The feature of this embodiment is that the common diffusion region 10 of the two precharge transistors 7a and 7b of the bit line precharge / equalize circuit 7 in the memory cell block is set to the bit line precharge in another memory cell block. It extends to the two precharge transistors 7a and 7b of the charge / equalize circuit 7 and is shared with the common diffusion region of the precharge transistors 7a and 7b. In the figure, the common diffusion region 10c is shared by the four precharge transistors (7a, 7b) and (7a, 7b) of the bit line precharge / equalize circuit 7 in two adjacent memory cell blocks. The number of precharge transistors sharing the diffusion region may be larger. The precharge transistors 7a and 7b that share a plurality of these diffusion regions supply the precharge potential VPRE only in the common diffusion region. In the recent process structure, a substance such as silicide or salicide, which has a higher resistance than the metal wiring but a lower resistance than the diffusion region, is formed on the surface of the diffusion region. As a result, the metal wiring for supplying the precharge potential VPRE becomes unnecessary. Therefore, the inter-wiring isolation region 14 with respect to the memory cell plate electrode 15 is not necessary, and the sense amplifier block can be laid out in close proximity to the memory cell plate electrode 15.

In this way, according to the layout arrangement as shown in FIG. 9, the plate electrode 15 of the sub memory cell array and the precharge potential V can be obtained as is clear from the comparison with FIG.
Since it is not necessary to provide the isolation region 14 between the metal wirings for supplying PRE, the area can be reduced. Therefore, the areas of the shared switch circuit 4 and the memory cell block precharge circuit 7 in the sense amplifier block circuit shown in FIG. 5 can be significantly reduced, and the size of the semiconductor chip can be significantly reduced.

(Third Embodiment) Next, the third embodiment of the present invention will be described.
The semiconductor memory device of the embodiment will be described. In the semiconductor memory device of this embodiment, in the layout arrangement of the sense amplifier block of the second embodiment shown in FIG. 9, when a metal wiring for supplying the precharge potential VPRE is further arranged, It proposes an appropriate arrangement of contacts connecting to the common diffusion region.

FIG. 10 shows this embodiment. In the figure,
Each of the shared switch circuit 4 and the bit line precharge circuit 9 in the memory cell block is composed of two, 10 is a diffusion region, 11 is a gate electrode, 15 is a memory cell plate electrode, and 16 is a metal wiring. In FIG. 10, which is the third embodiment, four shared switch transistors and four bit line precharge transistors in the memory cell block have the same layout arrangement as that in FIG. Further, even if the potential supply contact from the metal wiring of the precharge potential VPRE is arranged in the common precharge potential diffusion region 10c, a layout configuration is not increased to secure the separation region of the metal wiring. suggest.

That is, in the precharge transistor 7b located at the lower end in the figure, the lower end of the gate electrode 7g is formed by bending in a rightward convex shape. Further, in the shared switch transistor 4b located at the lower end, the lower end of the gate electrode 4g is also bent leftward in a convex shape. The gate electrode of the shared switch transistor 4b and the gate electrode 7g of the precharge transistor 7b.
A diffusion region 10d is formed in a portion surrounded by both bent portions of and, and the diffusion region 10d is connected to the common diffusion region 10c of the four precharge transistors 7a, 7b, 7a, 7b. Then, in the diffusion region 10d, a contact 10e connecting the metal wiring 16 for supplying the precharge potential VPRE and the diffusion region 10d is arranged. Accordingly, even if the contact 10e of the metal wiring 16 needs to be separated from the gate electrodes 4g and 7g, the area of the contact 10e can be secured. With this configuration, the metal wiring 16 for supplying the precharge potential VPRE can be laid out without approaching the memory cell plate electrode 15, so that the area can be reduced.

The precharge transistors 7a and 7b
Since the gate electrode 7g of the
A new transistor is formed in the common diffusion region 10c of the precharge transistors 7a and 7b from the diffusion region 10 in which e is arranged.
Since they have the same gate electrode 7g as a and 7b and have the same gate potential, the ON and OFF timings are the same,
There is no problem.

(Fourth Embodiment) Next, the fourth embodiment of the present invention will be described.
An embodiment will be described. If the above-described layout configuration is adopted for the layout arrangement of the sense amplifier blocks in the above-described first and second embodiments of the present invention, the gate width of the precharge transistor depends on the memory cell pitch. . Therefore, the current amount of the precharge transistor is reduced, and the time required for the precharge operation of the bit line on the memory cell side is delayed.
Therefore, the semiconductor memory device according to the fourth embodiment of the present invention proposes a configuration for increasing the current amount of the precharge transistor.

This embodiment will be described with reference to FIGS. 5 and 9. Normally, the shared switch transistor having the shared switch signal SH as a gate input is a bit line pair BIT0, XBIT0, BI amplified by a sense amplifier.
The potentials of T1 and XBIT1 are set to the bit lines BITR0, XBITR0, BITR1 and XBITR in the memory cell block.
In order to completely transmit the signal to 1, the potential of the shared switch gate SH is usually set higher than the power supply potential SAP of the sense amplifier. On the other hand, the precharge potential VPRE
Is normally set to about half the power supply potential of the sense amplifier, and the precharge potential VPRE is set to the bit lines BITR0, XBITR0, BIT in the memory cell block.
The gate potential PR of the precharge transistor does not need to be as high as the gate potential SH of the shared switch transistor in order to transmit to R1 and XBITR1. Therefore, it is possible to lower the gate potential of the precharge transistor at the high level than the gate potential of the shared switch transistor at the high level. Since the gate potential of the precharge transistor at a high level is low, the voltage applied to the gate oxide film of the precharge transistor is lower than the voltage applied to the gate oxide film of the shared switch transistor.

From the above, in the present embodiment, the oxide film thickness of the gate electrodes 7g of the precharge transistors 7a and 7b is set thinner than the oxide film thickness of the gate electrodes 4g of the shared switch transistors 4a and 4b. . When the gate oxide film thickness of a transistor is reduced, the amount of current of the transistor generally increases. As described above, by reducing the gate oxide film thickness of the precharge transistors 7a and 7b, the current amount of the precharge transistors 7a and 7b can be increased, and the time required for the precharge operation can be shortened. It is possible to speed up the precharge operation. Here, since the gate electrodes 4g of the shared switch transistors 4a and 4b and the gate electrodes 7g of the precharge transistors 7a and 7b are wired in parallel in the vertical direction of FIG. 9, the oxide film thickness of each transistor is also as shown in FIG. It is possible to have different film thicknesses in parallel in the vertical direction.

(Fifth Embodiment) Further, a semiconductor memory device according to a fifth embodiment of the present invention will be described. The present tenth aspect realizes the same purpose as that of the fourth embodiment by a different method. If the layout configuration of the sense amplifier block in the first and second embodiments is taken as described above, the precharge operation of the bit line on the memory cell side is delayed. Therefore, the precharge transistor 7
It proposes a configuration for increasing the current amounts of a and 7b.

This embodiment will be described with reference to FIGS. 5 and 9. Normally, if the threshold voltage of the precharge transistors 7a and 7b is made lower than the threshold voltage of the shared switch transistors 4a and 4b, the precharge transistor 7 will be
The current amounts of a and 7b are increased, and the precharge operation is speeded up. As a method of changing the threshold voltage of the transistor, it can be realized by changing the control injection of the threshold voltage. Therefore, the layout must be such that different threshold voltage control injections can be performed around the gate electrode of the transistor whose threshold voltage is to be changed. Since the gate electrodes 4g of the shared switch transistors 4a and 4b and the gate electrodes 7g of the precharge transistors 7a and 7b are wired in parallel in the vertical direction of FIG. 9, the threshold voltage control injection region of each transistor is It is possible to have different threshold voltage controlled implants located in parallel in the up and down direction.

Here, if the threshold voltage of the transistor is lowered, the current when the transistor is OFF (OFF current) will increase. Depending on the circuit, this OFF current may cause the standby current to be too large or cause the circuit to malfunction. However, the precharge transistor 7
Even if the OFF currents of a and 7b become too large, as described above, the precharge transistors 7a and 7b are always in the ON state in the standby state, so that the problem of the standby current does not occur. In addition, even when the circuit is operating, the sense amplifier 1
This is not a problem because a large current that destroys the data amplified by is not generated.

Therefore, in the present embodiment, the threshold voltages of the precharge transistors 7a and 7b are set lower than the threshold voltages of the shared switch transistors 4a and 4b, which causes problems such as standby current and circuit malfunction. Therefore, it is possible to speed up the precharge operation.

(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
A semiconductor memory device according to the embodiment will be described. The present embodiment realizes the same purpose as that of the fourth embodiment by a different method. As mentioned above, the first and second
In the layout configuration of the sense amplifier block in the present embodiment, a delay occurs in the precharge operation of the bit line on the memory cell side. Therefore, the present embodiment proposes a configuration in which the current amount of the precharge transistor is increased. It is a thing.

This embodiment will be described with reference to FIGS. 5 and 9. Normally, if the gate lengths of the precharge transistors 7a and 7b are made shorter than the gate lengths of the shared switch transistors 4a and 4b, the current amount of the precharge transistors 7a and 7b increases, and the precharge operation can be speeded up. it can. Here, if the gate oxide film thickness is large, it becomes difficult to control the threshold voltage and the like, and therefore the gate length of the transistor cannot be unnecessarily shortened. However, as described above, the precharge transistors 7a, 7
It is possible to reduce the gate oxide film thickness of b. Therefore, in the present embodiment, the gate length of the gate electrodes 4g of the shared switch transistors 4a and 4b in FIGS. 5 and 9 is made shorter than the gate length of the gate electrodes 4g of the shared switch transistors 4a and 4b. The gate electrodes 4g of the shared switch transistors 4a and 4b and the gate electrodes 7g of the precharge transistors 7a and 7b are wired in parallel in the vertical direction of FIG. 9, and the threshold voltage control injection region of each transistor is also in the vertical direction of FIG. Since different oxide film thicknesses are provided in parallel with each other, different gate lengths can be obtained.

Here, if the gate length of the transistor is shortened, the OF of the transistor becomes the same as in the fifth embodiment.
Although the OFF current at the time of F increases, the problem of the standby current does not occur because the precharge transistors 7a and 7b are always on in the standby state as described above. Further, even when the circuit is operating, a large current that destroys the data amplified by the sense amplifier 1 is not generated, so there is no problem.

Therefore, in the present embodiment, the gate lengths of the precharge transistors 7a and 7b are made shorter than the gate lengths of the shared switch transistors 4a and 4b, which causes problems such as standby current and circuit malfunction. Therefore, it is possible to speed up the precharge operation.

(Seventh Embodiment) Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described. This figure shows the layout arrangement of the semiconductor memory device according to the present embodiment, and shows the layout arrangement when the bit line precharge / equalize circuit 11 in the memory cell block shown in FIG. 6 has two equalize transistors. .

The semiconductor memory device according to this embodiment will be described with reference to the drawings. FIG. 11 also shows the layout arrangement of the shared switch circuit 4 and the bit line precharge / equalize circuit 11 in the memory cell block among the two sense amplifier block circuits in FIG. In the layout layout diagram of FIG. 11, each of the shared switch circuit 4 and the bit line precharge circuit 11 in the memory cell block is configured by two, and 10 is a diffusion region and 1 is a diffusion region.
Reference numeral 1 is a gate electrode, and 15 is a memory cell plate electrode.

As described above, a precharge transistor is often arranged on the bit line on the memory cell side in order to speed up the precharge operation. However, the operation speed is further increased and the current consumption due to the precharge operation is reduced. Therefore, an equalizing transistor for performing an equalizing operation for short-circuiting the bit lines may be provided on the bit line on the memory cell side. Therefore, the present embodiment proposes a configuration in which the increase in area when the equalizing transistor is provided is limited to a small value.

In the present embodiment shown in FIG. 11, as in the first embodiment shown in FIG. 8, the shared switch signal SH is used as the gate input in accordance with the pitch of the bit lines.
Shared switch transistors (2 4a and 4b
2) are arranged in the vertical direction. These shared switch transistors 4a, 4b, 4a, 4b have diffusion regions 10a, 10b on both sides of the common gate electrode 4g,
The diffusion regions 10a and 10b are two bit lines (BIT0, BIT0) and (X
BIT0, XBITR0), (BIT1, BITR0
1) and (XBIT1, XBITR1).

Further, with the equalizing signal EQ as a gate input, four equalizing transistors in the memory cell block (two 11b and two 11c) are arranged vertically. These equalizing transistors 11b, 11
c is a common diffusion region 11e on both sides of the gate electrode 11g.
And a diffusion region 10b. The diffusion region 10b is shared with one diffusion region 10b of the shared switch transistors 4a and 4b. In this embodiment,
The number of shared transistors sharing one diffusion region 10b of the equalizing transistors 11b and 11c is four.
However, the present invention is not limited to this, and may be a large number.

Further, the equalizing transistor 11
A precharge transistor 11a is arranged in parallel with b and 11c. This precharge transistor 11a is
Diffusion regions 11f and 11e are provided on both sides of the gate electrode 13, and one diffusion region 11e is equalizing transistor 1
It is shared with the common diffusion region 11e of 1b and 11c. The other diffusion region 11f of the precharge transistor 11a extends in the direction toward the precharge transistor 11a of the bit line precharge / equalize circuit 11 in another memory cell block and is shared with the diffusion region. The precharge transistors 11a and 11a having the common diffusion region are supplied with the precharge potential VPRE only in the diffusion region 11f. As a result, the metal wiring for supplying the precharge potential VBPRE becomes unnecessary.
Therefore, a layout in which the sense amplifier block can be arranged close to the memory cell plate electrode 15 is possible. Gate electrode 4g to which shared switch signal SH is input and gate electrode 1 to which equalize signal EQ is input
Gate electrode 7 to which 1 g and precharge signal PR are input
The g is arranged in parallel with each other in the same direction as the direction in which the sub word lines extend (vertical direction in the figure).

As described above, with the layout arrangement shown in FIG. 11, it is not necessary to provide element isolation between the diffusion regions of the shared switch transistors 4a and 4b and the diffusion regions of the equalizing transistors 11b and 11c, so that a large area can be obtained. Can be reduced. Further, it is not necessary to provide element isolation between the diffusion regions of the equalize transistors 11b and 11c and the diffusion region of the precharge switch transistor 11a, and the area can be further reduced. Therefore, the areas of the shared switch circuit 4 and the precharge / equalize circuit 11 in the memory cell block in the sense amplifier block circuit of FIG. 6 can be significantly reduced, and the size of the semiconductor chip can be significantly reduced.

(Eighth Embodiment) A semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIG. With the layout configuration of the sense amplifier block as in the first embodiment, the precharge transistors 7a and 7b are turned on during the precharge operation,
Start charging / discharging the bit line that has oscillated to high level and low level. Here, the timing when the precharge transistor turns on will be described. Since the source potential of the precharge transistor (for example, 7a) connected to the low-level bit line is low, the threshold voltage is low, the gate potential to be turned on is low, it starts to turn on quickly, and the amount of transistor current is large. On the other hand, since the source potential of the precharge transistor (for example, 7b) connected to the high-level bit line is at the precharge level, the threshold voltage is high and the precharge transistor is turned on.
Gate potential is high, it is turned on with a delay, and the amount of transistor current is small. Therefore, the current consumption from the precharge power supply becomes large as compared with the case where the bit line pair is only short-circuited by the equalizing transistors 4a and 4b. This hinders the reduction of electricity consumption. The present embodiment proposes a configuration capable of reducing power consumption by reducing current consumption from the precharge power supply.

That is, in this embodiment, the gate electrodes 1 of the equalizing transistors 11b and 11c shown in FIG.
Precharge transistor 11 than gate length of 1g
The gate length PR of the gate electrodes 13 of a and 11a is increased, and the current amount of the equalizing transistors 11b and 11c is increased. As a result, the ratio of the charge / discharge operation of the precharge potential to the bit line using the precharge transistor 11a is reduced, and the ratio of the equalization of the bit line pair potential by the equalization operation is increased to increase the current consumption from the precharge power supply. It is possible to reduce power consumption.

(Ninth Embodiment) Next, a semiconductor memory device according to a ninth embodiment of the present invention will be described. The present embodiment realizes the same purpose as that of the eighth embodiment by a different method. As described above, with the layout configuration of the sense amplifier block according to the first embodiment, the current consumption from the precharge power supply is large and low as compared with the case where only the bit line pair is short-circuited by the equalizing transistors 4a and 4b. Since this hinders power consumption reduction, this embodiment proposes a configuration in which current consumption from the precharge power supply is reduced and power consumption can be reduced.

That is, in the present embodiment, the equalizing transistors 11b and 11c in FIG. 11 are first turned on, and then the precharge transistors 11a and 11a are turned on after a predetermined time has elapsed. Therefore, in this embodiment, as in the eighth embodiment, the equalizing transistors 11b and 11c are first turned on.
Then, the potentials of the bit line pair are set to the same level and then the precharge potential of the bit line pair is charged / discharged. Therefore, the power consumption can be reduced.

(Tenth Embodiment) Finally, a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG. The configuration is as already described in the second embodiment.

As described above, FIG. 8 showing the first embodiment.
In this configuration, the inter-wiring isolation region 14 is required, which hinders the reduction of the area. Therefore, in the present embodiment, a configuration that eliminates the area increase due to the inter-wiring isolation region 14 is adopted, and the equalizing transistors 4a and 4b are used. We propose a structure that can reduce the power consumption by suppressing the increase of the current consumption from the precharge power supply as compared with the case where only the bit line pair is short-circuited.

That is, as shown in FIG. 9, the diffusion regions 10c of the precharge transistors 7a and 7b are shared as diffusion regions of the other precharge transistors 7a and 7b in the sense amplifier array. Furthermore, at the location where the sense amplifier driver SDR of FIG. 3 is arranged, that is, at the intersection of the sense amplifier row and the sub word driver row,
Diffusion region 10c of precharge transistors 7a and 7b
A contact (not shown) that connects the metal wiring for supplying the precharge potential VPRE is arranged to supply the precharge potential VPRE. As a result, it is not necessary to dispose a metal wiring for supplying the precharge potential VPRE in the sense amplifier column, so that it is not necessary to provide an inter-wiring isolation region with the memory cell plate electrode 15, and the area can be reduced. Further, due to the silicide and salicide on the diffusion region 10c, an appropriate resistance is introduced for supplying and diffusing the precharge potential, and the precharge transistors 7a and 7b substantially function as an equalizing transistor. The rate of charging / discharging the bit line due to is decreased, and the rate of equalizing the bit line pair potential by the equalizing operation is increased. Therefore, the current consumption from the precharge power supply can be reduced, and the power consumption can be reduced.

In the present embodiment, an example of the structure of the sub-word line is shown, but the structure described above can be adopted even in the case of a semiconductor memory device having a word line lining region instead of the hierarchical word line structure. is there. That is, the same effect can be obtained by arranging a contact for connecting the metal wiring for supplying the precharge potential to the diffusion area of the precharge transistor at the intersection of the word line lining area and the sense amplifier row. .

[0105]

As described above, according to the semiconductor memory device of the present invention, the gate electrode is provided when the sense amplifier block including the shared switch transistor, the precharge transistor or the equalize transistor is provided. Since it is not necessary to separate the connection contact from the connection contact, the distance between the connection contact and the diffusion region, and the need to provide an element isolation region between the diffusion regions, it is possible to significantly reduce the layout area. Therefore, it is possible to significantly reduce the chip size of a semiconductor memory device having a large number of sense amplifier blocks, and it is possible to exert a great effect on cost reduction.

In particular, in the invention described in claims 10, 11 and 12, in addition to the above effects, the amount of current flowing through the precharge transistor can be increased to speed up the precharge operation.

Further, according to the thirteenth and fourteenth aspects of the present invention, at the time of precharging the bit line pair, the rate of the charge / discharge operation of the bit line by the precharge transistor is reduced and the potential of the bit line pair by the equalizing operation is kept at the same level. Since the ratio of increase in power consumption is increased, it is possible to reduce current consumption that flows from the precharge power supply to the bit line and achieve low power consumption.

In addition, in the invention described in claims 15 and 16, it is necessary to provide a separation between the gate electrode and the connection contact, an overlap margin between the connection contact and the diffusion region, and to secure an element isolation region between the diffusion regions. It is possible to reduce the layout area drastically, and at the time of the precharge operation of the bit line pair, reduce the ratio of the charge / discharge operation of the bit line pair by the precharge transistor to reduce the bit line from the precharge power supply. It is possible to reduce the current consumption flowing to the device and reduce the power consumption.

Further, in the seventeenth aspect of the present invention, since the diffusion layers of the plurality of precharge transistors can be made common, it is possible to reduce the connection contact from the metal wiring having the precharge potential to this common diffusion layer, and to broaden the activation. You can make the area unnecessary.

[Brief description of drawings]

FIG. 1 is a block layout diagram of a dynamic RAM.

FIG. 2 is a block diagram of a large memory cell block included in the dynamic RAM.

FIG. 3 is a block diagram showing the periphery of a sub memory cell array included in the dynamic RAM.

FIG. 4 is a diagram showing an example of a circuit configuration of a sense amplifier block included in the periphery of the sub memory cell array.

FIG. 5 shows another example of the circuit configuration of the same sense amplifier block.

FIG. 6 is a diagram showing another example of the circuit configuration of the same sense amplifier block.

FIG. 7 is a layout diagram of a conventional semiconductor memory device.

FIG. 8 is a layout diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a layout diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a layout diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 11 is a layout diagram of a semiconductor memory device according to a seventh embodiment of the present invention.

[Explanation of symbols]

MB0 to MB3 Large memory cell block MWDB Main word line drive circuit SMA00 to SMAF7 Sub memory cell array SWLB00 to SWLBF8 Sub word line drive circuit SAB00 to SABG7 Sense amplifier row SDR00 to SDRG8 Crossing point 1 Sense amplifier 2 Column switch 3, 4 Shared switch circuit 4a 4b Shared switch transistor 5, bit line precharge / equalize circuit in sense amplifier 6, 7, 11 Memory cell block bit line precharge / equalize circuit 7a, 7b, 11a Precharge transistor 11b, 11c Equalize transistor 12 Gate electrode- Wiring connection area 13 Element isolation area 14 Interwiring isolation area 16 Metal wiring 17 Bit line in memory cell Precharge circuit

Claims (17)

[Claims] 1. A memory cell array in which a plurality of memory cells connected to a bit line are arranged, a sense amplifier row in which a plurality of sense amplifiers provided for each pair of the bit lines are arranged, and a pair of the bit line pairs. A precharge transistor array in which a plurality of precharge transistors for precharging are arranged, and a shared switch transistor array in which a plurality of shared switch transistors that connect the bit line pairs to corresponding sense amplifiers are arranged. 2. A semiconductor memory device, wherein one of the diffusion regions and one of the diffusion regions of the shared switch transistor corresponding to the precharge transistor are shared. 2. The semiconductor memory device according to claim 1, wherein the other diffusion region of the precharge transistor is shared with another diffusion region of another precharge transistor. 3. The semiconductor memory according to claim 1, wherein a gate electrode of the shared transistor and a gate electrode of a precharge transistor corresponding to the shared transistor are arranged so as to extend in the same direction. apparatus. 4. A memory cell array in which a plurality of memory cells connected to a bit line are arranged, a sense amplifier row in which a plurality of sense amplifiers provided for each pair of the bit lines are arranged, and a bit line pair A precharge transistor row in which a plurality of precharge transistors for precharging are arranged, an equalize transistor row in which a plurality of equalize transistors for equalizing the bit line pair are arranged, and a shared line connecting the bit line pair to a corresponding sense amplifier. A shared switch transistor array in which a plurality of switch transistors are arranged is provided, and one diffusion region of the equalizing transistor and one diffusion region of the shared switch transistor corresponding to the equalizing transistor are shared. Semiconductor memory device. 5. The semiconductor memory device according to claim 4, wherein the other diffusion region of the equalizing transistor and one diffusion region of the precharge transistor corresponding to the equalizing transistor are made common. 6. The semiconductor memory device according to claim 4, wherein the other diffusion region of the precharge transistor is shared with the other diffusion region of the other precharge transistor. 7. The gate electrode of the shared transistor and the gate electrodes of the equalize transistor and the precharge transistor corresponding to the shared transistor are arranged so as to extend in the same direction. Alternatively, the semiconductor memory device according to the sixth aspect. 8. The diffusion region shared by the precharge transistor and another precharge transistor,
The common diffusion region of the precharge transistor, which extends in the same direction as the sense amplifier row, is connected to a precharge potential supply wiring arranged in a metal wiring layer through one contact. 7. The semiconductor memory device according to claim 2 or 6. 9. The contact is disposed near an end of a gate electrode of the precharge transistor, and the gate electrode of the precharge transistor is bent so as to bypass the contact in the vicinity of the contact. 9. The semiconductor memory device according to claim 8, which is characterized in that. 10. The semiconductor memory device according to claim 1, wherein the precharge transistor and the shared switch transistor have different gate oxide film thicknesses. 11. The semiconductor memory device according to claim 1, wherein the threshold voltage of the precharge transistor is lower than the threshold voltage of the shared switch transistor. 12. The semiconductor memory device according to claim 1, wherein the gate length of the precharge transistor is shorter than the gate length of the shared switch transistor. 13. The semiconductor memory device according to claim 4, wherein a gate length of the equalizing transistor is shorter than a gate length of the precharge transistor. 14. The semiconductor memory device according to claim 4, wherein the precharge transistor is turned on after the equalizing transistor is turned on. 15. A diffusion region shared by the precharge transistor and another precharge transistor,
5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a precharge potential supply wiring arranged in a metal wiring layer at a position of an intersection of the sense amplifier row and the word line drive circuit. 16. A diffusion region shared by the precharge transistor and another precharge transistor,
5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a wiring for supplying a precharge potential arranged in a metal wiring layer at a position of an intersection of the sense amplifier row and a word line lining area. 17. A memory cell array in which a plurality of memory cells connected to a bit line are arranged, a sense amplifier row in which a plurality of sense amplifiers provided for each pair of the bit lines are arranged, and a pair of the bit line pairs. Each of the bit lines includes a precharge transistor string in which a plurality of precharge transistors for precharging are arranged, and a shared switch transistor string in which a plurality of shared switch transistors that connect the bit line pair to a corresponding sense amplifier are arranged. A semiconductor memory device, wherein a corresponding precharge transistor of the precharge transistor array is directly connected to the pair, and a corresponding bit line pair is precharged from a precharge power supply via each precharge transistor.