TH8047B - Personal computers with processor reset control? - Google Patents

Abstract

This invention relates to personal computers and in particular to personal computers which has the ability to provide continuous processing through the occurrence of reset signals while avoiding falling. The liquid of the personal computer system has a high-speed local processor data bus. An input/output bus for microprocessor reconfigurable data that is directly connected to the local processor bus and a coupling controller connected directly to the local processor bus and connected. directly to the input/output bus. For information to provide communication between the local processor bus and the input/output bus for the local processor bus controller data and the input/output bus for the local processor bus connection controller information. Provides a decision between devices directly connected to the input/output bus for data access to the input/output bus for data and the local processor bus. And to determine between the input/output bus for data and the microprocessor to access the local processor bus, the bus link controller also remembers the reception of the reset signal intended to be used to trigger a reset of the processor. Processes the comma and slows the transmission of the reset signal until the bus connection controller has prohibited access to the local processor bus and the input/output bus by any device that may request such access.

Claims (12)

1. A personal computer system consists of: a high-speed dedicated processor data bus, an input-output data bus, a resettable microprocessor directly connected to the dedicated processor bus, and a bus link controller directly connected to the dedicated processor bus and the input-output data buses to provide communication between the dedicated processor bus and the input-output data buses. The bus link controller also recognizes the hot reset signal received by the bus link controller, which is intended to initiate a reset of the microprocessor and delay the generation of the CPU reset signal for the microprocessor. The system continues until the aforementioned bus link controller gains control of the aforementioned local processor bus and the aforementioned input-output buses from all devices and microprocessors through the exchange of hold signals and hold feedback signals (CPU_HOLD and CPU_HLDA). 2. The personal computer under claim number 1 herein, the bus link controller, will respond to the reconfiguration signal by suspending the control of the aforementioned input-output buses and the aforementioned local processor bus. 3. The personal computer, under claim number 2 herein, the bus link controller shall respond to the reception of reconfiguration signals during a period when the said microprocessor controls the said input-output bus and the said local processor bus by providing a hold signal to the microprocessor and awaiting the release of the said input-output bus and the said local processor bus by the said microprocessor. 4. The personal computer, under claim number 2 herein, whereby the bus link controller responds to the reception of reconfiguration signals at intervals when a device directly connected to the aforementioned input-output data bus controls the aforementioned input-output bus and the aforementioned local processor bus by providing hold signals to the microprocessor and awaits the release of the aforementioned local processor bus by the aforementioned microprocessor. 5. A personal computer system consists of: a high-speed data bus, an input-output data bus, a resettable microprocessor connected to the high-speed data bus, volatile memory connected to the high-speed data bus for storing volatile data, storage memory devices, a storage controller connected to the high-speed data bus and to the storage memory device to control communication with the storage memory device, and a bus link controller connected to the high-speed data bus and the input-output data bus to manage communication between the high-speed data bus and the input-output data bus. The bus link controller makes decisions between the resettable microprocessor and the storage controller for accessing the high-speed data bus, and makes decisions between the high-speed data bus and any devices directly connected to the input-output data buses for accessing the input-output data buses. The bus link controller also recognizes hot reset signals received from the bus link controller. The intention is to initiate a readjustment of the aforementioned microprocessor and delay the generation of the reset signal (CPU_RESET) for the microprocessor until after the aforementioned bus interface controller has gained control of the local processor bus and the input-output buses from all devices and the aforementioned microprocessor through the exchange of hold signals and hold feedback signals (CPU_HOLD and CPU_HLDA). 6. The personal computer, as per claim number 5, whereby the bus link controller responds to the reconfiguration signal by suspending the control of the aforementioned input-output buses and the aforementioned high-speed data bus. 7. The personal computer, under claim number 6 herein, the bus link controller shall respond to the reception of reconfiguration signals during a period when the said microprocessor controls the said input-output bus and the said high-speed data bus by providing a hold signal to the microprocessor and waiting for the release of the said input-output bus and the said high-speed data bus by the said microprocessor. 8. Under claim number 6 herein, the bus link controller responds to the reception of reconfiguration signals at intervals when devices directly connected to the aforementioned input-output buses and the aforementioned high-speed data bus provide a hold signal to the microprocessor and await the release of the aforementioned input-output buses and the aforementioned high-speed data bus by the aforementioned microprocessor. 9. A personal computer system consists of: a high-speed data bus, a microprocessor directly connected to the aforementioned high-speed data bus, a computational processor directly connected to the aforementioned high-speed data bus, volatile memory directly connected to the aforementioned high-speed data bus for storing volatile data, a storage memory device for storing permanent data, a storage controller directly connected to the aforementioned high-speed data bus and connected to the aforementioned storage memory device to control communication with the aforementioned storage memory device, an input-output data bus, an input-output controller directly connected to the aforementioned input-output data bus, a numeric signal processor directly connected to the aforementioned input-output data bus, and a bus linker connected to the aforementioned high-speed data bus and connected to the aforementioned input-output data bus to provide communication between the aforementioned high-speed data bus and the aforementioned input-output data bus. The bus linker controller makes decisions among the microprocessors. The aforementioned bus link controller, and the aforementioned storage controller, which is directly connected to the aforementioned high-speed data bus for access to the aforementioned high-speed data bus, and provides decision-making among the aforementioned input-output controllers, and the aforementioned numeric signal processors, and the aforementioned image signal processors, which are directly connected to the aforementioned input-output data bus and the aforementioned high-speed data bus for access to the aforementioned input-output data bus, also recognizes the receipt of a hot reset signal from the aforementioned bus link controller, which is intended to initiate the reset of the aforementioned microprocessor and delay the generation of a CPU reset signal for the microprocessor until after the aforementioned bus link controller has received control of the local processor bus and the aforementioned input-output buses from all devices and the aforementioned microprocessors by exchanging hold signals and hold acknowledgment signals (CPU_HOLD and CPU_HLDA). 10. The personal computer under claim number 9 herein, the bus link controller, will respond to the recalibration signal by suspending the control of the aforementioned input-output buses and the aforementioned high-speed data bus. 11. The personal computer, under claim number 10 herein, the bus link controller shall respond to the reception of reconfiguration signals during a period when the said microprocessor controls the said input-output bus and the said high-speed data bus by providing a hold signal to the microprocessor and waiting for the release of the said input-output bus and the said high-speed data bus by the said microprocessor. 12. The personal computer, pursuant to claim number 10 herein, the said bus link controller shall respond to the reception of reconfiguration signals during a period when the said microprocessor controls the said input-output buses and the said high-speed data bus with the said microprocessor and awaits the release of the said high-speed data bus.