TH53299A - Digital base band system - Google Patents

Abstract

DC60 (07/02/45) This invention provides a baseband system for short-range radio communication systems that conforms to the Bluetooth baseband characteristics and is well suited for the practical implementation of efficient hardware providing a low-power, small-sized, and low-cost radio subsystem design. The baseband system consists of a transceiver and a buffer unit, which enables efficient gate counting and reduced power consumption. The transceiver design is based on a pipe-based signal processing operation with controlled flow of output data paths. The transceiver processes output and input data sets and consists of multiple signal processing units connected in a sequence, whereby each signal processing unit is clocked by a common clock signal. A pipeline connection is connected to each signal processing unit for switching each signal processing unit between transmit and receive modes. A control connection is used to switch each signal processing unit between transmit and receive modes. Connected by communicating information, the flow is controlled whether in a sending method to one or more sets of pre-processing signals, or in a receiving method to one or more sets of subsequent processing signals. A buffer system comprises a buffer system that applies the concept of flexible memory organization, leading to efficient practical results of buffers or storage elements in terms of gate circuit count and power consumption, and offering the capability of flexible dynamic memory addressing for variable-length user data sets. The buffer system for storing the first and second processing sets consists of multiple storage elements, each storage element having a first and second storage set. A switch subsystem is provided for switching each storage element between the first and second methods. In the first method, each first storage set can be addressed by the first processing set, and each second storage set can be addressed by the second processing set. In the second method, each storage set... The second set can be addressed by the first set of processors, and each of the first set's storage units can be addressed by the second set of processors. This invention provides a baseband system for short-range radio communication systems that conforms to the Bluetooth baseband characteristics and is well-suited for the practical implementation of efficient hardware that provides a small, low-power, and low-cost radio subsystem design. This baseband system consists of a transceiver and a buffer unit, which enables the system to have an efficient gate circuit count and reduced power consumption. The transceiver design is based on a pipe-based signal processing method with controlled flow of output data paths. The transceiver processes the output and input data sets and consists of multiple signal processing units connected in a sequential manner, in which case each signal processing unit is clocked by a common clock signal. A connecting wire is connected to each signal processing unit for switching between signal processing units. The transmit and receive modes of control connections are where each signal processing unit is connected. Communication information controls the flow, whether in the transmit mode to one or more signal processing units prior to one unit, or in the receive mode to one or more subsequent signal processing units. A buffer system comprises a buffering system that applies the concept of flexible memory organization, leading to efficient practical results of buffers or storage elements in terms of gate circuit count and power consumption, and offering the capability of flexible, dynamic memory addressing for variable-length data sets. The buffer system for storing the first and second processing units consists of multiple storage elements, each containing a first and second storage unit. A switch subsystem is provided for switching each storage element between the first and second modes. In the first mode, each first storage unit can be addressed by the first processing unit, and each second storage unit can be addressed by the second processing unit. In the second method, each second storage set can be addressed by the first algorithm set, and each first storage set can be addressed by the second algorithm set.

Claims (20)

1. Communication device (30) for processing outgoing and incoming data sets. The device consists of several signal processing units (40) connected in a sequential manner, each signal processing unit (40) being clocked by a common clock signal (32), a method signal line (34) connected to each signal processing unit (40) for switching each signal processing unit (40) between transmitting and receiving modes, and a control signal line (36) to which each signal processing unit (40) is connected, which communicates flow control information either in transmitting mode to one or more preceding signal processing units or in receiving mode to one or more subsequent signal processing units. 2. Communication device for processing outgoing data sets. An device consisting of multiple signal processing units (40) connected in a sequence. Each signal processing unit (40) is clocked by a common clock signal (32) and a control signal line (36) to which each signal processing unit (40) is connected by a control signal line (36) that communicates flow control information to one or more preceding signal processing units (40). 3. Communication device for processing incoming data sets. An device consisting of multiple signal processing sets (40) connected in a sequential manner that formats the signal processing process in this way. Each signal processing set (40) is clocked by a common clock signal (32) and a control signal line (36) to which each signal processing set (40) is connected by a control signal line (36) that communicates flow control information to one or more subsequent sets of signal processing sets (40) in the signal processing process. 4. Any of the devices under claims 1 through 3 in which each set performs signal processing (40) consists of multiplexers (42,43). 5. Any device under any of the claims 1 through 3 in which each signal processing unit (40) consists of a multiplexer (42) at its input and a multiplexer (43) at its output. 6. Any of the devices under Claims 1 through 3 in which each signal processing unit (40) is connected via logic unit (38) to control signal line (36). 7. Device under claim 6 in which the logic set (38) consists of an OR gate. 8. Any device under any of the claims 1 through 3 in which the flow control information consists of a hold information that indicates a signal processing set (40) that receives the hold information to stop the processing. 9. The device under claim 1 in which each set of signals (40) is operational for the transmission and reception modes. 10. A transceiver set (20) consisting of a transceiver controller (22) and a communication device (30) under either of the two claims 1 through 9, which are interconnected, is adapted to communicate with the buffer set (50) via the bus system (2). 11. A buffer system (60) for storing the data of the first (10,11) and second (20) process sets, consisting of multiple storage elements (65), each consisting of multiple first (61) and second (62) storage sets of the switch subsystem (74), for switching storage elements (65) between the first and second method modes, which are characterized by: in the first mode, each first storage set (61) is addressable by the first process set (10,11) and each second storage set (62) is addressable by the second process set (20); and in the second mode, each second storage set (62) is addressable by the first process set (10,11) and the first storage set (61) is addressable by the second process set (20). 12. The buffer system according to claim 11, in which each component maintains (65) consists of multiple cells. 13. A buffer system based on claim 11, comprising an additional first address decoder (71) for selecting one storage element (65) for writing and reading data by the first set of operations (10,11). 14. A buffer system under claim 11, which includes a second decoder (72) for selecting one storage element (65) for writing and reading data by a second set of processes (20). 15. A buffer system based on claim 11 in which each subsystem of switch (74) consists of multiple access switches (75). 16. A buffer system under either claim 11 and 15 shall be further comprising a controller (52) containing a buffer switch register (76) for controlling each subsystem of switch (74). 17. A baseband system consisting of a communication device (30) under any of the claims 1 to 9 and a buffer system (60) under any of the claims 11 to 16, both of which are connected via a bus system (2). 18. A method for storing the data of the first (10,11) and second (20) algorithm sets in a buffer system (60) consisting of multiple storage elements (65). Each storage element (65) contains the first (61) and second (62) storage sets. The method consists of switching each storage element (65) between the first and second algorithms. In the first algorithm, the address of each first storage set (61) is assigned by the first algorithm (10,11) and the address of each second storage set (62) is assigned by the second algorithm (20), and in the second algorithm, the address of each second storage set (62) is assigned by the first algorithm (10,11) and the address of each first storage set (61) is assigned by the second algorithm (20). 19. The method under claim 18, which is further comprised of selecting multiple storage elements (65) and combining them into one or more storage blocks (66) consisting of the first storage block and the second storage block. 20. The method under claim 19 is further comprising the switching of each storage block (66) between the first method and the second method. In the first method, the address of each storage block is assigned to the first set of operations (10,11), and the address of each storage block is assigned to the second set of operations (20), and in the second method, the address of each storage block is assigned to the second set of operations (10,11), and the address of each storage block is assigned to the first set of operations (20).