KR20050060688A - Dual bus controlling device of the node-b in the umts using a high speed serial line - Google Patents

Abstract

The present invention provides an address and data write FIFO that reads and stores an address and a data signal interfaced by a processor bus slave block of a UMS base station redundant processor in a first-in first-out manner, and an address and data transmitted from a processor board operating from the active. Address and read FIFOs that read and store signals on a first-in, first-out basis; read parallel address and data signals from each address and data write FIFO of the active processor board, convert them into high-speed serial data, and then use a standby processor High-speed serial consisting of a serial conversion module that transmits to the board and converts high-speed serial data received from the active board through a serial data line into parallel address and data signals and outputs them to each address and data read FIFO. Provided is a redundant bus control apparatus of a UMS base station using a line.

As described above, the present invention checks each FIFO of the redundant bus control apparatus through a plurality of TX and RX FIFO interface blocks, and according to the result, a plurality of serial conversion blocks read the stored data and convert the stored data into a serial method. By transmitting to the device, the transmission speed is significantly improved.

Description

Dual bus controlling device of the node-B in the UMTS using a high speed serial line}

The present invention relates to a redundant bus controller of a UMS base station using a high-speed serial line, and in particular, checks each FIFO of the redundant bus controller through a plurality of TX and RX FIFO interface blocks and checks a plurality of serials according to the results. The present invention relates to a redundant bus controller of a UMS base station using a high-speed serial line in which a conversion block reads the stored data, converts the data in a serial manner, and transmits the data to a counterpart device.

In general, UMTS (Universal Mobile Telecommunication System) networks can transmit "third generation", broadband packet-based text, digitized voice or video, and multimedia data at high speeds of more than 2 Mbps, whether mobile or computer users are anywhere in the world. Provide consistent service. This UMTS network allows computer and telephone users to continue to access the Internet while traveling and have the same performance no matter where they are traveling. Users will use this UMTS service through a combination of terrestrial radio and satellite transmission technology.

However, such a UMTS network includes a base station (Node-B), a base station controller (RNC), a core network (Core network), and the like, which are generally configured in a network form to process radio signals transmitted and received from a mobile terminal. Doing. In the node-B as described above, for example, a channel card for call processing of a subscriber station or a processor board for controlling such channel cards is mounted on the back board 300.

In addition, as shown in FIG. 1, the processor board is generally configured to be redundant. Between the processor boards 100 and 200, dual controllers 110 and 210, which are bus controllers, are processed by the CPU 120 of the active side. The data stored in the memory 130 is transferred to the dual controller 210 which is a bus control device operated as a standby side through the PCI bus 400 and backed up to the memory 230 under the control of the CPU 220. It responds so that there is no abnormality in switching.

To do so, referring to FIG. 2 of the bus control apparatus of the conventional redundant board as described above, the processor bus slave block 70 for interfacing the data transmitted through the CPU bus 140 from the active CPU 120 is shown. And an address write FIFO 71 for reading and storing address data interfaced by the processor bus slave block 70 in a first-in first-out manner, and a data signal interfaced by the processor bus slave block 70 in a first-in first-out manner. A data write FIFO 72 for reading and storing the data, a PCI bus arbiter 73 for confirming whether a PCI BUS license is allocated to the standby processor board 200, and the PCI bus arbiter 73) is assigned a PCI BUS license and transmits the data temporarily stored in the address and data FIFO (71, 72) to the MUX (for example, 64 bit PCI bus) PCI bus master block 74, a PCI bus slave block 75 for demuxing and outputting an on muxed address and data signal transmitted from the opposite processor board 200, and the PCI bus slave block ( An address read FIFO 76 for reading and storing the address data demuxed by 75) in a first-in first-out manner; and a data write for reading and storing the data signal demuxed by the PCI bus slave block 75 in a first-in-first-out manner. A processor bus master block for transferring the data read from the FIFO 77 and the address and data write FIFOs 76 and 77 to the memory 130 via the CPU bus 140 under the functional control of the CPU 120 ( 78).

On the other hand, the operation of each bus control device of the conventional redundant board as described above, first, the processor board 100 of the active side (Active Side) (Master) of the CPU Bus 140, the arbitrary arbitrary in their own memory 130 Write the data. In addition, the processor bus slave block 70 of the dual controller 110 in the processor board 100 of the active side interfaces with data transmitted through the CPU bus 140 from the CPU 120 that is active and addresses the address. The data is written to the write FIFO 71 and the data write FIFO 72 in a first-in first-out manner. At this time, the active PCI bus master block 74 checks the storage areas of each of the address write FIFO 71 and the data write FIFO 72, and when the PCI bus master block 74 finds that they are not empty, the PCI bus arbiter 73 ) Arbitration (Arbitration) with the other slave's processor board (200) to obtain the bus license and the address and data signals to the 64Bit PCI Bus to the PCI bus slave block 75 of the standby Send by MUX. Then, the PCI bus slave block 75 in the standby standby state demuxes the data input through the PCI bus 400 so that the address signal is transmitted to the address read FIFO 76 and the data signal is read from the data read FIFO 77. Store each in. Therefore, when the processor bus master block 78 of the standby confirms that the data signals are transmitted to each of the FIFOs 76 and 77, it requests the license of the CPU bus from the CPU 220 of the standby side. Each address and data signal is read from each FIFO 76, 77 and placed on the CPU bus 240. Then, the standby CPU 220 stores and backs up the input data in the memory 230.

In this case, when the boards are switched, the process is repeated.

However, each bus control device of the conventional redundant board is a PCI Bus A / D 64-bit bus and a PCI Control Pin for data transmission between the TX FIFO of the active processor board and the Rx FIFO of the standby processor board. Since these pins must be designed to have many signal pins, etc., these pins caused pin shortage for other functions on the backboard, and also other components connected to the TX and RX FIFOs, that is, PCI bus master blocks. However, data transmission between PCI bus slave blocks has a problem that high-speed data transmission is difficult because the mux or demux method is used.

Accordingly, the present invention has been invented to solve the above-mentioned general problems, and converts the address and data signals in parallel to be read or written into a serial line instead of a muxing method, and thus transmits a transmission rate using a bus. It is an object of the present invention to provide a redundant bus control apparatus of a UMS base station using a high speed serial line which is considerably improved.

Another object of the present invention is because the structure of the bus signal interface block is composed of a serial transmission method rather than a muxing method, it is possible to significantly reduce the number of pins mounted on the back board, accordingly high-speed serial line significantly improves the usefulness of the board design using the back board The present invention provides a redundant bus control apparatus for a UMS base station.

In order to achieve the above object, the present invention provides a redundant bus controller of a UMS base station having a processor bus slave and a master block for transmitting and receiving signals to and from a CPU of a redundant processor board.

An address and data write FIFO for reading and storing an address and a data signal interfaced by the processor bus slave block in a first-in first-out manner, and for reading and storing an address and data signal transmitted from a processor board operating from the active in a first-in first-out manner. Reads parallel address and data signals from the address and read FIFO and the address and data write FIFO of the active processor board, converts them into high-speed serial data, and transmits them to the standby processor board through the serial data line. UTM using a high speed serial line, consisting of a serial conversion module for converting high speed serial data received from the active board into parallel address and data signals and outputting them to each address and data read FIFO. To provide a redundant bus control device for a base station.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The apparatus of the present invention is a processor bus slave block (1) for interfacing data transmitted via the CPU bus 140 from an active CPU (120) as shown in Figure 3, and the processor bus slave block (1) An address write FIFO 2 for reading and storing address data interfaced by the first-in first-out method and a data write FIFO 3 for reading and storing the data signal interfaced by the processor bus slave block 1 in a first-in-first-out manner. And an address read FIFO 4 for reading and storing the address signal transmitted from the active board 100 in a first-in first-out manner, and a data read for reading and storing the data signal transmitted from the active board 100 in a first-in first-out manner. High-speed address and data signals are read from the FIFO 5 and the active addresses and data write FIFOs 2 and 4 in parallel. It converts into real data and transmits it to standby board through serial data line, and converts high-speed serial data received from active board through serial data line into parallel address and data signal to each address and data lead FIFO (5). A processor for transferring the serial conversion module 6 to be output and the data read from the address and the data read FIFOs 4 and 5 to the memory 130 through the CPU bus 140 under the function control of the CPU 100. It consists of a bus master block (7).

Then, the serial conversion module 6 checks the state of the address write FIFO 2 as shown in Fig. 4, and accordingly results in the TX address interface block 8 for interfacing the address signal to be transmitted to the standby side. And a TX data interface block 9 for checking the state of the data write FIFO 3 and interfacing the data signal to be transmitted to the standby side according to the result, and a parallel interfaced from the TX address interface block 8. A first serial conversion block 10 for encoding an address signal, converting it into a high speed serial signal, and then transmitting the same through a serial data line or vice versa, and an interface from the TX data interface block 9; Encodes parallel data signals, converts them into high-speed serial signals, and transmits them through serial data lines Alternatively, the third serial conversion block 11 performing the reverse process and the high speed serial signal transmitted through the serial data line 12 of the active board 100 may be decoded and output as parallel address signals. Alternatively, the second serial conversion block 13 performing the reverse process and the high speed serial signal transmitted through the serial data line of the active board are decoded and output as parallel data signals, or vice versa. Interface the fourth serial conversion block 14 to be performed and the parallel address signal output from the second serial conversion block 13, check the state of the address read FIFO 4, and accordingly, the corresponding address signal. Interface the parallel data signal outputted from the RX address interface block 15 and the fourth serial conversion block 14 and check the state of the data read FIFO 5. The RX data interface block 16 then transmits the data signal according to the result.

Here, one output terminal of the TX address interface block 8 is connected to an input terminal of the second serial conversion block 13, and one output terminal of the RX address interface block 15 is one of the first serial conversion block 10. An output terminal is connected, one output terminal of the TX data interface block 9 is connected to an input terminal of a fourth serial conversion block 14, and one output terminal of the RX data interface block 16 is a fourth serial conversion block 14. One input terminal of) is connected.

In other words, the cross connection of each of the interface blocks 8, 9, 15, and 16 and the serial conversion blocks 10, 11, 13, and 14 means that the input and output data can be transmitted alternately as necessary.

Next, the operation and effects of the apparatus of the present invention as described above will be described.

First, the processor board 100 of the active side becomes the master of the CPU bus 140 and writes arbitrary data to its own memory 130. In addition, the processor bus slave block 1 of the dual controller 110 in the processor board 100 of the active side interfaces the data transmitted through the CPU bus 140 from the CPU 120 that is active and writes the address. The FIFO 2 and the data write FIFO 3 are written on a first-in first-out basis. At this time, the TX address interface block 8 and the TX data interface block 9 of the active serial conversion module 6 check the storage areas of the address write FIFO 2 and the data write FIFO 3. If they find that they are not empty, the first serial conversion block 10 and the third serial conversion block 11 read the corresponding address and data signals from each address write FIFO 2 and the data write FIFO 3, respectively. To interface with each other. Then, each of the first serial conversion block 10 and the third serial conversion block 11 encodes parallel address and data signals read from the TX address interface block 8 and the TX data interface block 9, respectively. Converts it into a high-speed serial signal and transmits it to the opposite standby board through the serial data line 12.

Meanwhile, when high speed serial data is transmitted from the active board through the serial data line 12, the second serial conversion block 13 and the fourth serial conversion of the serial conversion module 6 of the dual controller of the standby board are transmitted. Each block 14 receives and decodes the data to be output to the RX address interface block 15 and the RX data interface block 16 as parallel address and data signals. Then, each of the RX address interface block 15 and the RX data interface block 16 checks the states of the address read FIFO 4 and the data read FIFO 5, and when the normal condition is reached, the second serial The parallel address and data signals output from the conversion block 13 and the fourth serial conversion block 14 are interfaced and stored in each of the address read FIFO 4 and the data read FIFO 5.

Therefore, when the processor bus master block 7 of the standby confirms that the data signal is transmitted to each of the FIFOs 4 and 5, it requests the license of the CPU bus from the CPU 220 on the standby side. Receives each address and data signal from each FIFO (4, 5) and places it on the CPU bus 240. Then, the standby CPU 220 stores and backs up the input data in the memory 230.

In this case, when the boards are switched, the process is repeated.

Therefore, according to the present invention as described above, it is possible to eliminate the bottleneck of the data transfer rate due to the increase in CPU performance and support the redundant concurrent Wrtie method with minimal design changes. In addition, the number of EDGE pins of the serial conversion module 6 matched with the backboard is reduced to 1/4 or less to secure EDGE pin resources so that other functions can be additionally implemented.

As described above, the present invention checks each FIFO of the redundant bus control apparatus through a plurality of TX and RX FIFO interface blocks, and according to the result, a plurality of serial conversion blocks read the stored data and convert them into a serial method. By transmitting to the next counterpart device, the parallel address signal and data signal to be read or written are converted into serial lines rather than a muxing method, and thus the transmission speed is considerably improved by using a bus.

In addition, according to the present invention, since the bus signal interface block is composed of a serial transmission method rather than a muxing method, the number of pins mounted on the back board can be considerably reduced, thereby improving the usefulness of the board design using the back board. have.

1 is an explanatory diagram illustrating a redundant board of a UMTS base station.

2 is an explanatory diagram illustrating a conventional redundant bus control device.

3 is an explanatory diagram illustrating a redundant bus control device of the present invention.

4 is an explanatory diagram illustrating a serial conversion module of the apparatus of the present invention.

<Detailed Description of Codes>

1: Processor bus slave block 2: Address write FIFO

3: data write FIFO 4: address read FIFO

5: Data lead FIFO 6: Serial conversion module

7: Processor Bus Master Block 8: TX Address Interface Block

9: TX data interface block 10: first serial conversion block

11: third serial conversion block 12: serial data line

13: second serial conversion block 14: fourth serial conversion block

15: RX Address Interface Block 16: RX Data Interface Block

Claims (3)

In the redundant bus control apparatus of the UMS base station having a processor bus slave and a master block for transmitting and receiving signals to and from the CPU of the redundant processor board, An address and data write FIFO for reading and storing an address and a data signal interfaced by the processor bus slave block in a first-in first-out manner, and for reading and storing an address and data signal transmitted from a processor board operating from the active in a first-in first-out manner. Reads parallel address and data signals from the address and read FIFO and the address and data write FIFO of the active processor board, converts them into high-speed serial data, and transmits them to the standby processor board through the serial data line. UTM using a high speed serial line, consisting of a serial conversion module for converting high speed serial data received from the active board into parallel address and data signals and outputting them to each address and data read FIFO. Redundant bus control device of a base station. 2. The apparatus of claim 1, wherein the serial conversion module checks the state of the address write FIFO and, according to the result, checks the state of the data write FIFO and a TX address interface block for interfacing the address signal to be transmitted to the standby side. And a first data data stream to which the TX data interface block interfaces the data signal to be transmitted to the standby side, and a parallel address signal interfaced from the TX address interface block to be converted into a high speed serial signal and then transmitted through a serial data line. A serial conversion block, a third serial conversion block which encodes a parallel data signal interfaced from the TX data interface block, converts the serial data signal into a high speed serial signal, and then transmits the same through a serial data line; and a serial data line of the active board. through A second serial conversion block for decoding the transmitted high speed serial signal and outputting the parallel address signal, and a second serial conversion block for decoding the high speed serial signal transmitted through the serial data line of the active board and outputting the parallel data signal. An RX address interface block for interfacing a serial conversion block, a parallel address signal output from the second serial conversion block, checking a state of an address read FIFO, and transmitting a corresponding address signal according to the result; UMS using a high-speed serial line, comprising a RX data interface block for interfacing parallel data signals output from the serial conversion block, checking the state of the data lead FIFO, and transmitting the corresponding data signals according to the result. Redundant bus controller of base station. 3. The output terminal of claim 2, wherein one output terminal of the TX address interface block is connected to an input terminal of a second serial conversion block, and one output terminal of the RX address interface block is connected to one output terminal of a first serial conversion block. One output terminal of the interface block is connected to the input terminal of the fourth serial conversion block, one output terminal of the RX data interface block is connected to the one input terminal of the fourth serial conversion block UMS base station using a high-speed serial line Redundant bus controller.