SU999060A1 - Quadratic equation root computing device - Google Patents

Description

(S) DEVICE FOR CALCULATION OF SQUARE EQUATION ROOTS

The invention relates to computing and can be applied autonomously to systems for automatically controlling dynamically objects or technological processes. A device for calculating roots is known, comprising a result counter, a key, a pulse generator, three germs, a divider, AND, OR elements and two multipliers. A disadvantage of this device is its low speed and limited functionality. The closest in technical essence to the invention is a device containing a (n-1) -th group of series-connected single-digit adders, where n is the output code size, a group of modulo-two adders, a group of elements OR, a group of elements NOT, ( -2) additional groups of i adders modulo two, with the output of each j-ro single-digit adder (the group is connected to the first input of the (j1) th single-bit adder of the t-th group, and the outputs of the adders modulo two of the i-th additional the groups are connected to the second inputs jx one A disadvantage of the known device is a relatively low speed. The aim of the invention is to improve the speed. This goal is achieved by the fact that the device for calculating the roots of the quadratic equation, g contains (n-1) -th a group of series-connected one-bit adders, where n is the output code width, (2 + i) in each i-th group (, 2, ... jh-1), a one-bit adder is added, groups of series-connected one-bit subtractors by (n + 2) in each kth group (, 2, .., n), the nth group of n series-connected single-digit adders and unit generator, with the output of each 1st (, 2,., ,, , n + 2) single-digit adder - subtractor of the k-th group is connected to the first input {} -1) -th single-bit totalizer-subtractor (k + 1) -th group, the second inputs of the single-bit totalizer-subtractors of which are connected and connected to the transfer input of the (n + 2) -th totalizer-subtractor of the same group, the first input of the k-th one-bit adder of the n-th group, the transfer output of the first one-bit adder-subtract atele of the kth group, the first inputs are the J-X. (at) one-digit adders of the i-th (when) group, first inputs (2 + il) -x and (2 + i-2) -x one-digit adders of the i-th group and i-th group, respectively, starting with, i. To the k-ro input of the first input bus, the transfer of the first transfer and the output of the sum of each JTO (, 2, ..., 2 + i) of the one-bit adder of the i-th group are connected respectively with the third input of the first and the third the input (j + l) -ro of a one-bit adder-subtractor (k41) -th group, the first input of the one-bit adder, transfer outputs and the sum of which are connected to the third inputs - the second and the third, respectively About one-digit adders-subtractors of the first group, connected to the second, input of the second one-digit accumulator of each group, the second input of the first one-digit adder of the group and the output of the first bit of the first input bus, output of each (k + 1) -th bit of which is connected to the third input (+3) -th (at). a one-bit adder-subtractor of each k-th group ™ (, 2.-, ..., k), to the second input of () -th. (on) one-bit totalizer of each i-th group (, kH, .., nl) and the second input (k-bT) -ro one-bit sum of a torus of the n-th group connected by its output to (k + l) - My bit of the output bus, the input of the older and first bits of which is connected to the transfer output of the sum of the first one-bit adder of the same group, the second output (2 + il) -ro of the one-bit adder of the i-th group is connected to the third input () - ro and the (24- | -1) single-bit adder (1 + 1) -th group, the first input of the (2 + 1) -th one bit d9 04 Horn adder and the first and third inputs of the third and second one-bit the adders of the first group, the second and third inputs of the one-digit adder and the first adder-subtractor of the first group are connected to the null bus of the device, the second inputs of each single-digit totalizer of the first group are combined and connected to the output of the unit generator and the transfer input (n + 2) - one-digit adder-subtractor of the same group, and the first inputs of each 1st and (n + 2) -th one-bit adders you, respectively, of the first and (+ 1) -th groups are connected to the corresponding bits of the second input tires with each one-bit adder-subtractor. contains a one-bit three-input adder and a modulo-two adder, the output of which is connected to the first input of a one-digit adder, the second input of which and the first and second modulo-two inputs are the first, second and third inputs of the adder; . The transfer output of which is connected to the third input and output of the transfer of a one-bit three input adder. Moreover, the (2 + 1-2) th one-bit adder of each (1 + 1) -and group is maintained by a one-bit three-input adder and an OR element connected by its output to the first input of the one-bit adder, the second input of which is the first and The second inputs of the ElementNTA OR are the second, respectively, the first and the third inputs. FIG. 1 shows a circuit diagram for calculating the roots of the quadratic equation, for the case when FIG. 2 is the (2 + 1-2) -th circuit. a one-bit adder of each (1+ 1) -th group; on fi.g. 3 is a one-bit subtractor-subtractor circuit. .The device (figo 1) contains (p-1) (group 1 consecutively connected one-digit adders of (2 + 1) in each i-th group (, 2, ..., p-1), n groups 2 of series-connected one-bit adders of subtractors of (n + 2) in each k-th group (, 2 ,, .., p) n-th group 3 of n consecutively connected one-bit adders, one-bit adder, generator 5 units, first input bus 6, the second input bus 7g. (, 1,2, ..., 2n), the first output bus 8 and the second output bus 95 (s, 1,2, ..., p). Each G-group 1 is made, for example, on (2 + i) series-connected single 10 total adders, () of the one-bit adder 11 in each (| + T); group 1 and (2 + i-1) -ro one-bit fo of adder 12 in each f-th group 1. K-group 2 performed, for example, from series-connected single-digit adders-subtractors 13. Each (2 + 1-2) single-digit adder 11 (FIG. 2) is made, for example, of a single-digit three-input adder 10 and the OR element 1 connected by its output To the single input of the single bit summatr 10, the second input of which both the first and the third inputs of the element OR 1A are. respectively the second, first and third inputs. A one-bit adder and a subtractor 13 (FIG. 3) are filled, for example, from a one-bit three-way adder 10 and an adder 15 modulo two connected by its output to the first input of a single-bit one. adder 10, the second input of which is the first and second inputs of the adder 15 modulo two. are the first, second and third inputs of the one-bit adder - subtractor 13, respectively. The transfer input and output of the one-bit adder-1 1 reader 13 are connected to the third input and output of the transfer of the one-digit three-input adder 10. Each output of the 1st (1 1, 2., ..., p + 2) of the one-bit adder-subtractor 13 of the k-th group 2 is connected to the first input (1 -1) of the first one-bit adder-subtractor 13 (k + l) -fl of group 2, Second the inputs of one-bit adders-subtractors 13 of each (K + 1) -th group 2 are combined and connected to the transfer input of the (n + 2) -th total 13 subtractor (and + 1) -th group 2, the first input of the k-th single-bit adder 10. group 3 to the transfer output of the first one-bit adder-subtractor 13 of the k-th group 2, the first inputs jx (with) one-bit adders 13 of each | th (for) group 1, first inputs (2 + 1-1) and (2 + 1-2) single-digit adders 12 and 11, respectively, of the i-th group of the 1 and the i-th group 1, starting with i + 2 and to the input of the k-ro bit of the first input bus Sj-, the transfer of the nose of the first one-digit adder 10 and the output of the sum of each J-th (j 1,2,; .., 2 + j) one-bit adder 10, 11, and 12 with j 2tiT2 and j, 2-fi-1), respectively The i-th group 1 is connected respectively to the third 1m input of the first one-bit adder a-you reader 13 and the third input (j + l) -ro of the one-bit one total equal to read 13 (k-ft) -and group 2. The first input one-bit This adder 4, whose transfer outputs and sums are connected to the third inputs of the second and third one-bit adders-subtractors 13 of the first group 2, respectively, is connected to the second input of the second one-bit adder .11 of the second group 1, the second input of the second one-bit adder 10 each 1 th group, the second input of the first one-digit adder of the 10th nth group 3 and the output of the first bit 6, the first input bus 6, The output of each (k + 1) -th: bit of the first input bus 6 is connected to the third input (+3) - go (with) a one-bit adder-subtractor of the 13th k-th group of .2 (when, 2, ..., k), to which the input is (2 + G) -th (with ik) bmultidisc. of the summer 10, one-bit adder 12 (for,), one-bit adder 11 (for) and one-digit adder 10 (LRI jk-3f ..., nl) of each ith group 1 (, k + 1,.,. N-1) and the second input (k + t) -ro of a one-bit adder of the 10th nth group 3 "Transfer output the first one-bit adder 10 and the output of the sum of the k-ro single-bit adder of the 10th group group are connected respectively to the input of the higher (whole) bit 9o and k-ro bit of the second output bus 9d. The second output f2 + il) -ro of the one-bit adder 12 of the 12th group 1 is connected to the third inputs of the (2+ and -2) -th (2 + i-lJ-ro of the one-digit adders 11 and 12 (} +1) - group 1. The first input (2 + 1) -th single-digit adder 10 I-and group 1 and the third input one-bit of the totalizer 12 of the first group 1, and the second and third inputs of the one-bit totalizer 4 and the first summator 13 of the first group 2 are connected with a zero bus device. The second inputs of each adder-subtractor 13 of the first group 2 are combined and connected to the output of the generator 5 units and the transfer input (n + 2) -th one the first adder of each of the 1st and (n + 2) -th one-digit adders of the subtractor 13, respectively, of the first and) groups are connected to the outputs of the corresponding bits 7oi 7.0 ,, ,, ,, ... 72nd second input bus 7f-. The first inputs of the (2nd) single-digit adder of the 10th group 1 and the second input of the single-digit adder are inverse. The operation of the proposed device for calculating square roots. equations X + ax + b 0 for a o, b o, represented in bit form in the form b - () 6, are shown in a specific example,

The process of finding the bits of the desired bit vector x 999060 where the fight to co is

can be represented as single vectors representing the corresponding images of the numbers b, x, 0 correspondingly - the bit matrices representing the bit image x and a with. We write expression 1 in a detailed form for the case when 2, I 3, 2, 2, 4, 3, 3 t + 1 i, where X x, X xvx, x xvx,, i 1 ,, .., n .. Each The i-th bit of the desired vector X is determined by the expression 1 "... 1. ; .- "o p Nl -o iM, 7 .... n, where fH + lP-r is the meaning of the transfer from the high bit of the bit vector of the torus, determined on the basis of the expression; iUH, () value, taking the values of at .0.

When i 1,, -2, and the vectors a (... D (in accordance with U)

SdJ.

S

The second root X2 of quadratic equation 1) is determined by the expression

so

 1100001

)

"10110 V W

eleven

q -010111 o (gp 01 11 o

 HOOO 1111

f

what is represented as the sum calculated by expressions (3-6) values and a, i.e. ) - Consider the above on specific primes, 6875 L -0.355 921875 and respectively, and, 03125 1 I nlxj. y (3) fy- .. - (x Я I 10-11 o 1 01 1010110 101010, l4) - (i F 1 01 0 0 4) V d 10110 1101001 0 0 1 1 0 0 OO (.i 10000 5ЬDO 011001 011 0011 01 10 110 10101 1010101 1011 7) - 00 00 1 000 in accordance with (8 / half of the significance of x, Z 1 011 about XJ-0 1011 (1.0 0001) The device for calculating the roots of the quadratic equation works as follows When applying for the first input bus 6 values of bits a and .., and the vector of the torus and the second input bus 7p. Respectively bits b, b, ..., b of the vector b and after the eye; the transition process in the circuit at the outputs of single-digit adders-subtractors 13 of the first group 2 in accordance with (5) is formed Achen vector L supplied to the first inputs of adders odnorazr dnyh-vychit.ateley 13 the second group 2. At the output of transference

The first one-bit adder-subtractor 13 of the first group 2 according to the expression (k) and, accordingly, the first bit 8 of the first output bus 8- |, forms the st-bit bit of the desired vector. As a result, the sums in one-bit adders — the subtraction of the second group — the value of 2 x 1

(01V (9)

 and vector a ,, incoming torus

from one-bit adders 10, 11 and 12 of the first group; 1, a vector b is formed, and at the output of the second formula of the invention

1. A device for calculating the roots of a quadratic equation containing the (n-1) -th group of series-connected single-digit adders where n is the output code width, by (2-fii) B each 1st group (i-1, 2, ..., p-1), characterized in that, in order to increase the speed of the first output bus 8 bytes / riTj-fi, the value of the second bit x of the vector x is developed. Further, in the same way, at the outputs of the third, fourth, and fifth groups 2 of one-bit adders-subtractors 13, the vectors b, o are formed in accordance with (5), and at the outputs of high-order bits and respectively. Bit 8, 8, .- 8 | j EXIT Tire & in expression1 (g C) - the value of bits And, finally, H X-). - | | vector x. at the outputs of one-bit adders of 10 p-th group 3 and, accordingly, bits SQ,, c ", 9p of the second output bus 9c, by expression (8), the values of bits x, x, x,.", x of the second root Xn of the Kradrat equation (one ). For computed and square-. It is necessary to send a zero signal to the first input bus 6, i.e. , and the second input bus 7p value b. After the end of the transition process in the circuit, on the output bus 8 and, respectively, 9e, in accordance with the expressions), the moduli of values chi X2 are formed similarly to the above described. The use of new elements, as well as new connections between the networks ,. distinguishes the proposed device from iz. . This is known because the proposed device significantly increases the speed, which is determined by the time of the transition process in the circuit due to the fact that the device is combinational. Due to this, the result of calculating the two roots of the quadratic equation is realized per cycle. This fact contributes to the use of the proposed device in computers that implement the computational process on a natural time scale, for example. Controls of technological processes, dynamic objects in the mode of their normal functioning about the action, a one-bit adder was introduced into it, n groups of consecutively connected one-digit totalizer totalizers in (k-1-2) in each k-th group, 2,. . ,, p), the n-th group of n series-connected one-digit adders and generator units, with the output of each 1 st:. (, 2, ..., n + 2) one-bit sum of a torus - subtractor of the k-th goupap connected to the first input of the (1-1) th one-bit adder - subtractor (+1) -th group, second inputs of one-bit the adders-subtractors of which are combined and connected to the transfer input of the (n + 2) -th adder-subtractor of the same group, the first, the input of the k-ro single-digit adder of the n-th group, the transfer output of the first one-bit adder-subtractor of the k-th group , to the first inputs jsx, (with) one-digit adders of each i-and (with is-k) groups, the first inputs (2-4ii-1) -x and (2 + i-2) -x one-bit adders respectively the i-th group and the i-th group, starting with, and k-. the input of the k-ro bit of the first input bus, the output of the transfer of the first and the output of the sum of each j-ro (, 2, ..., 2-hi). the one-digit adder of the t-th group are connected respectively to the third input of the first and third input of the (j + 1) -th single-digit adder-subtractor (k + 1) -th group, the first input of the one-bit adder, the outputs of the nose and the sum of which are connected to the third inputs of the second and third one-digit adders respectively of the first group of readers, the second is connected to the second input of the second single-row adder of each i-th group, the second input of the first one-bit adder of the n-th group and the output of the first digit of the first input bus output every go (k + l) -ro of which is connected to the third input of the (1+ 3) -th (at) one-bit adder and you are the reader as a k-th group (, 2 ,, .., ik), to the second the input (2+ i) -ro (for) of the one-bit adder of each i-th group (, k + l, ..., p-1) and the second input (k + l) -ro of the one-bit adder of the n-th group connected / by its output to the (k + 1) -My discharge of the output bus, the senior and first-bit viod of which is connected to the transfer output of the sum of the first one-digit single-digit adder of the same group, the second output (2 + Ы) -р one-bit one adder of the i-th group is connected to the third input (2 + i-2) -ro and (2 + il) -ro single-digit adder (i +) -th group, the first input of which (2 + i) -ro single-digit adder and the first and third inputs of the third and second single-bit adders of the first group, the second and third inputs of one-bit the adder and the first adder of the first group are connected to the zero bus of the device, the second inputs of each one-digit adder of the first group are combined and connected to the output of the unit generator and the transfer input of the (n + 2) -th. one-bit adder-reciever of the same group, and the first, the inputs of each 1st and (n + 2) -th one-bit adders- “readers, respectively, of the first and () -th groups are connected to the. corresponding, the bit -. dami second input bus,. 2,. The device according to claim 1, of which is, each one-bit adder-slider contains a one-bit three-input adder and a modulo-two adder, the output of KQTOporp is connected to the first input of the one-bit adder, the second in; one; of which both the first and second inputs of the adder modulo two are, respectively. The first, second and third inputs of the adder-subtractor, the transport input and output of which are connected to the third input and output of the one-digit three-input poorenos output. 3 Device on PP. 1 and 2, about t and h. It is due to the fact that, (2-f - 2) -and one-digit adder of each (1 + 1) -and group contains, one-digit three-input adder and the OR element, connected by its output to the first single-bit single-cell accumulator, the second input of which and the first and second inputs of the OR element are, respectively, the second, first third inputs. i Sources of information taken during animation 1, USSR Author's Certificate Vf 710039, cl . G About F 7/38, 1980, 2. USSR author's certificate No. 857981, kp. G 06 F 7/38, 1980 (prototype).

Claims (3)

Claim 1 "A device for calculating the roots of a quadratic equation containing the (n-1) th group of series-connected single-bit adders where η is the bit depth of the output code, by (2 + i) -B of each ί-th group (i-1, 2, ..., n-1), characterized in that, in order to increase the speed of action, a single-digit ”adder is introduced into it, η groups of series-connected single-digit adders-subtractors by (n + 2) in each k-th group ( k = Γ, 2., n), the nth group of η series-connected single-digit adders and a generator of units, and the output of each 1 (1 = 1,2, ..., n + 2) single-digit adder - subtractor k -th group is connected 1 with the first input of the (1-1) -th single-digit adder - subtractor (; <+ 1) of the -th group, the second inputs of the one-bit adders-subtractors of which are combined and are connected to the input 1 of the transfer of the (n + 2) -th adder-subtractor of the same group, the first, input of the k-th single-bit adder of the fifth group, the transfer output of the first single-bit adder-subtractor of the 2nd k-group, the first inputs jzx, (for j = k) one-bit adders of each 'i-th (for i * -k) group, the first inputs of (2 + i-1) -x and (2 + i-2) -x one-bit ... adders respectively, of the i-th group 2: and the i-th group, starting from 1 = 2, and to the input of the k-th category of the first input bus, the transfer output of the first and the output. sums of each j-ro (j = 1,2, ..., 2 + i). the single-bit adder of the i-th corpus is connected respectively to the third input of the first and third input of the (j + 1) -th single-bit adder-subtractor (k + 1) of the first group, the first input of the single-bit adder, outputs ₃ , nose and the sums of which are connected to the third inputs of the second and third single-digit adders-subtractors of the first group, respectively. connected to the second input of the second single-digit adder of each ίth group, the second input of the first single-bit adder of the nth group and the output of the first discharge of the first input bus out q each (k + 1.) th discharge of which _4J swarm is connected to the third input (1 + 3) ~ th (for 1 = k) of a single-bit adder-subtractor of each k-th group (k = 1, 2, ... D), to the second input '(2+ i) -ro (for i = k) of a single-bit the adder of each i-th group (i = k, k + 1, p-1) and the second input of the (k + 1) -th single-bit adder of the p-th group, connected by its output to the (to + 1) -th * discharge bus, the input of the senior and first digits of which is connected to the transfer output of the sum of the first single-bit adder of the same group, the second output (2 + il) -ro of the single-bit adder of the i-th group is connected to the third input (2 + i-2) -ro and (2 + il) / - ro single-digit adder (| +1) -th group, first the first input (2 + i) -ro of a one-bit adder of which both the first and third inputs of the third and second one-bit adders of the first group, the second and third inputs of the one-bit adder and the first adder-subtractor of the first group are connected to the zero bus of the device, the second inputs of each one-bit adder are the subtractors of the first group are combined and connected to the output of the unit generator and the transfer input of the (n + 2) th single-digit adder-subtractor of the same group, and the first. the inputs of each G-th and (l + 2) -th single-digit adders-subtracters of the first and (| +1) th groups, respectively, are connected to the corresponding, bit-. second input bus / .2. The device according to claim 1, with the proviso that each one-bit adder-subtractor contains a one-bit three-input adder and an adder modulo two, the output of which is connected to the first input of the one-bit adder, the second input of which the first and second inputs of the adder modulo two are, respectively. the first, second and third inputs of the adder-subtract. a carrier whose input the transfer output is connected to the third input and output of the peenos of a single-digit three-input adder. · 3 "The device according to PP. 1 and 2, with the exception that the (2 + Ϊ-2) -th single-bit adder of each (i + 1) -th group contains a single-bit three-input adder and an OR element, connected by its output to the first input of a single-bit adder, the second input of which and the first and second inputs of the OR element are, respectively, the second, first · third inputs. ,