SU997046A1 - Device for measuring frequency difference - Google Patents

Description

The invention relates to electrical engineering and can be used in control systems for electric drives, in particular in speed regulators.

A device is known for obtaining a differential pulse repetition rate, comprising a synchronizer, anti-coincidence schemes, a pulse expander and a delay unit £ 1].

The device does not 'provide an analog' signal proportional to the difference frequency.

A device is known for determining the frequency difference 'of two sequences of pulses, containing a trigger, logical circuits AND and AND-NOT [2 The device does not produce at its output an analog signal proportional to the frequency difference taking into account the sign; which limits the scope of the device.

The aim of the invention is to expand the functionality of the device.

This goal is achieved by the fact that in the device containing the first and second triggers and the And element, a serially connected integrating amplifier with a reset key, a correction unit, a serially connected pulse shaper and a delay element, two sign-changing keys, a serial information transmission key and a latch are inserted , element NOT, resistors, and the input of the integrating amplifier through a resistor and a resistor inverter circuit connected to the first contacts of the sign-change keys, respectively, and through adjacent resistors to the output of the first trigger, the second contacts of the reversing keys are connected to the common bus, and the control outputs are connected to the outputs of the second trigger, the second output of the second trigger is connected to the 'input-. pulse generator, the output of which is connected to the first input of the And element, the second input of which is connected to the output of the correction unit, the output of the And element is connected to the control input of the information transmission key, the input of which is connected to the integrator output, the control input of the reset key of which is connected to the input of the delay element .

Moreover, the correction unit consists of a rectifier, a zero-organ and an HB element connected in series.

Figure 1 shows a schematic diagram of a device; figure 2 - timing diagrams of the operation of the device.

The device contains triggers 1 and 2, an inverter 3, resistors 4-8, change keys 9 and 10, a reset key '11, g an information transfer key 12, a pulse shaper 13, an integrating amplifier 14 with a capacitor 15, a correction unit 16, including a rectifier 17, null-organ 18, element u 19 NOT, as well as element 20 AND, delay element 21, latch 22.

The device operates as follows.

An input frequency is fed to one of the inputs of trigger 1 and to trigger 2 with a counting input (figa), another input frequency is fed to the other input of trigger 1 (fig.2b). The output of the trigger ¹ 1 appears equal-polar signal (pigv). At the outputs of the trigger 2 with a counting input, signals appear (Fig. 2d, 2e). 'Even pulses from the first frequency sequence at the output of trigger 2 supply a signal to close the key 9 and the signal from trigger 1 is fed through inverter 3 to the direct input of amplifier 14. Odd pulses from the second frequency sequence from the output of trigger 2 supply a signal to close. key 10 and the signal from the output of trigger 1 is also supplied to the direct input of amplifier 14. At the same time, each odd pulse at the output of trigger 2 generates a short pulse at the output of driver 13 by its leading edge. Resistors 4 and 5 in the device limit the current from the output of trigger 1 when the keys 9 'or 10 are shorted. 40

As a result of alternating ‘their closure, a signal appears at the input of amplifier 14 (Fig. 2e), i.e. the signal arriving at the integrator’s direct input is integrated in one case with a sign corresponding to the input signal, and in the other case (through inverter 3) with the opposite sign. ..

The time interval for which each measurement of the result (the resulting interval) is performed is equal to the period between the two nearest pulses from the output of the shaper 13.

The signal from the integrator (Fig.2zh) is fed to the rectifier 17 (to the correction unit 16 — elimination of the surge in the derivative) and to the first pole of the key 12. The sign of the resulting integral (see Fig.2z) depends on the ratio of input frequencies. The signal from the output of the rectifier's high end is fed to the input of the zero-organ 18, the response threshold of which is determined by the bias voltage E - In normal operation at the moment! the arrival of pulses from the shaper 13 voltage 13 from the output of the rectifier Ug * ^. the zero-organ does not work, at its output there will be a 0 signal, which is converted by the element NOT 19 to 1, i.e. both inputs of AND gate 20 at this time and served I ^d * 1 signal from its output gives a command signal to the integrator circuit 12 and key fiksatsyyu level at this time via latch 22.

However, in the zone of a phase shift equal to zero or a multiple of 2 7G, a short-term surge in the derivative is possible (see Fig. 2g, h). In this case, from the moment of the arrival of the pulses, the drivers 13ϋβ7 гοπ g zero-organ are triggered, 1 appears on the eBo output, then at the output of the logical element NOT 19 there will ^also be a 0 ⁿ signal that goes to the input of the logical element And 20. To the other input of the same element 20 a signal is received from the shaper. 13.

Only the presence of two 1 signals at the inputs of the logic element 20 gives at its output 1, a signal, which gives a command to short-circuit the key 12 for transmitting information. The signal measured by the integrator 1 is transmitted to the latch 22.

The signal from the output of the shaper 13 through the delay line 21 (for a time f) gives a command to the reset key 11, which is short-circuited and the integrating capacitor 15 is discharged to zero.

The time delay Τ 'is necessary so that when the information transmission key is closed, the latch 22 accurately captures and remembers the signal transmitted from the integrator of Fig.2z. The process of converting the input signal is shown in Fig.2e, the output signal of the integrator in Fig.2g, and the whole device in Fig.2y.

The introduction of new nodes and elements: an integrator with a reset key, a sign change key, a correction node, a latch, a delay line - distinguishes the proposed device from the prototype, providing at its output an analog signal proportional to the difference frequency taking into account the difference sign with a ripple factor close to zero (for Af = C0H5-t), and can be included in the closed part, from the no-phase ATS without additional, intermediate nodes (which are necessary when using the prototype).

Claims (2)

The invention relates to electrical and aeronautical engineering and can be used in drive control systems, in particular, in speed controllers. A device is known. For obtaining a difference pulse frequency, comprising a synchronizer, anti-coincidence circuits, a pulse spreader and a delay unit 1}. The device does not provide an analog signal (a signal proportional to the difference frequency. A device is known for determining the difference between the frequencies — two sequences of pulses containing three germs, logic circuits AND and}. The device does not provide an analog signal at its output proportional to the frequency difference c taking into account the mark that limits the scope of the device .. The aim of the invention is to expand the functionality of the device. The goal is achieved by the fact that the device holding the first and second triggers and echo and, serially connected integrations with a reset key, correction unit, serially connected pulse generator and delay element, two keys of sign changes, serially connected information transfer key and latch, element NOT, resistors, and an integrating force input - the body through the resistor and the chain of the resistor are connected to the first contacts of the keys, the sign recurs, respectively, and through the limiting resistors to the output of the first trigger, the second contacts you sign change keys are connected to a common bus, and control outputs .soedineny a second flip-flop outputs, the second output of the second flip-flop is connected to the input of the formation. pulse pulses, the output of which is connected to the first input of the element I, the second input of which is connected to the output of the correction unit, the output of the element And is connected to the control input of the information transfer key, the input of which is connected to the output of the integrator, the control input of the reset key of which is connected to the input delay element. Moreover, the correction node consists of successively connected rectifiers, a null organ, and an NB element. Fig. 1 is a schematic diagram of the device; Fig. 2 shows time diagrams of the device operation. The device contains triggers 1 and inverter 3, resistors 4-8, switch keys 9 and 10, reset key 11 information transfer key 12, pulse generator 13, integrating amplifier 14 with capacitor 15 correction node 16, including rectifier 17, null organ 18 , the element 19 is NOT, as well as the element 20 And, the delay element 21, the latch 22. The device operates as follows. An input frequency (Fig. 2a) is fed to one of the inputs of trigger 1 and to a trigger 2 with a counting input, to the other input of trigger 1, another input frequency is applied (Fig. 2b). At the output of trigger 1, an equipolar signal appears (Figure 2b). Signals appear at the outputs of trigger 2 with a counting input (Fig. 2d, 2HO. Even pulses from the first frequency sequence at the output of trigger 2 give a signal to the closure of key 9 and the signal from trigger 1 is fed through inverter 3 to the direct input of amplifier 14. Odd pulses from the second frequency sequence from the output of flip-flop 2 send a signal to the closure of key 10 and the signal from the output of gigabyte 1 is also fed to the direct input of amplifier 14. At the same time, every odd pulse at the output of flip-flop 2 During the operation, a short pulse shaper 13 is applied. Resistors 4 and 5 in the device limit the current from the output of trigger 1 with shorted keys 10. As a result of their alternating 3s, a signal appears at the input of amplifier 14 (Fig. 2e), i.e. The signal arriving at the direct input of the integrator is integrated in one case with a sign corresponding to the input signal, and in the other case (through inverter 3) with the opposite sign ... Time interval over which each measurement of the result is made (-resulting interval ) is equal to the period between the two nearest pulses from the output of the imager 13. The signal from the integrator (Fig. 2g) is fed to the rectifier 17 (to the correction node 16 - elimination of the derivative spike) and to the first pole of the key 1 The sign of the resulting integral (see Fig. 2z) depends on the ratio of input frequencies. The signal from the output of the rectifier is fed to the input of the zero-body 18, the response threshold of which is determined by the bias voltage E on. In normal operation, at the moment of arrival of the pulses from the former 13, the voltage from the output of the rectifier 0. its output will be O signal, which element NOT 19 is converted to 1, i.e. At both inputs of the I 20 element, at this moment, the 1 and 1 signals are fed from its output, which gives the command to close the key 12 and fix the signal level on the integrator at this moment using the latch 22. However, in the phase shift zone H equal to zero or a multiple of 2 7G, possible short-term surge in the derivative (see Fig.2zh, h). In this case, from the moment the pulses arrive, the EOL drivers, the zero-body is triggered, 1 appears at the output, then the output of the logical element NOT 19 is an O signal, which is fed to the input of the logical element AND 20. The other input of the same element 20 signal from the driver .13. Only the presence of two 1 signals At the inputs of the logic element 20 gives at its output 1, a signal - which gives a command for a short circuit of the key 12 of information transfer. The signal measured by the integrator 1 is transmitted to latch 22. The signal from the output of the imaging unit 13 through the delay line 21 (for the time T) sends a command to the reset key 11, which is briefly closed and the integrating capacitor 15 is discharged to zero. The time delay T is necessary so that when the information transfer key is closed, the latch 22 accurately captures and remembers the signal transmitted from the integrator of FIG. The process of converting the input signal is shown in Fig. 2e, the output signal of the integrator is shown in Fig. 2g, and the entire device is shown in Fig. 2i. The introduction of new nodes and integrator elements with a reset key, keys of sign change, correction node, clamp, delay line - distinguishes the proposed device from the prototype, providing at its output an analog signal reception proportional to the difference frequency taking into account the sign of the difference with the ripple factor close to zero ( for D COH5-fc), and can be included in a closed frequency-phase CAP without additional, intermediate nodes (which are necessary when using the prototype). Claim 1. An apparatus for measuring frequency rasterity, comprising first and second triggers and an AND element, characterized in that extensions of functionality, a sequentially connected integrating amplifier with a reset key, a correction node, are entered into it; 1) successively connected driver-impulses and a delay element, two sign transfer keys, serially connected information transfer key and latch, NOT element, resistors, and the input of the integrating amplifier through the resistor and the circuit of the resistor-inver, the torus is connected to the first contacts of the keys, the sign changes respectively, and through the limiting resistor l - to the output of the first trigger Ser, the second contacts of the switch keys are connected to the common bus, and the control inputs are connected to the outputs of the second trigger, the second output of the second trigger is connected to the input of the pulse generator, the output of which is connected to the first input of the And element, the second input is connected to the output of the correction unit, the output And is connected to the control input of the information transfer key, the input of which is connected to the integrator output, the control input of the reset key of which is connected to the output of the delay element. 2. The device according to claim 1, characterized in that the correction unit consists of successively connected null-organ rectifiers and the element HE. . Sources of information taken into account in the examination 1. Author's certificate of the USSR 213977, cl. G 06 G 7/14, 1964. 2. USSR author's certificate number 377799, cl. G About G 7/14, 1971. BUT // yy h Jvi 4.T fff fug f