SU995358A2 - Code converter - Google Patents

Description

The invention relates to telecommunications and can be used for the generation of codes in transmission systems; chi and processing. discrete information. According to the main author. St. 792605 is a known code converter, which contains serially connected character register, multiplier, adder, control unit and memory block, as well as first and second decoders combined by inputs, KOTQIMX outputs are connected to inputs of multiplier and adder 1, respectively.

However, the known converter does not provide the conversion of non-register codes — into register telegraph codes.

The purpose of the invention is the conversion of non-register codes in the register.

For this, a known code converter, containing successively connected register of symbols, multiplier, adder, control unit and memory block, as well as first and second decoders combined by inputs, the outputs of which are connected, respectively, are entered into the multiplier and adder inputs register generator, block; and, block of elements And, element

OR and two sign registers, the first output of the memory block through the first register of the sign is connected to the inputs of the comparison unit directly and through the serially connected block of the AND elements and the second register of the signs, the output of the block is compared to the corresponding input block of the ynpaJS10 block of laziness, the second output of which is connected to the first input "" of one register, to the second input of which the second fssxoK of the memory unit is connected, and the output of the output register is connected to

15 to the first input of the OR element, the gate of which is the output of the converter of codes, and the cpoigi cTBigowHe inputs of the block of elements AND are combined with the corresponding inputs of the generator

20 register symbols, to the corresponding input of which the third output of the control unit is connected, and the output of the register character generator is connected to the second input of the OR element.

25

The drawing shows a structural electrical circuit converter codes.

The code converter contains a register of 1 characters, the wit nickleader 2,

Claims (1)

30 Suyul & 3, block 4 controls. unit 5 pfmty, two decoder 6 and 7 output {register 8, two registers 9 and 10 signs, unit 11 comparison, generator | 2 register symbols, block of elegant elements AND 13, element OR D4. The code converter works as follows. A code combination arrives at the input and is entered into the register of 1 characters. In parallel, the code type index enters the inputs of the decoder 6 and 7. The decoder b forms the code word corresponding to the value of the combiner received. This code word is fed to multiplier 2 and serves as m4 to extract a valid code pattern from the character register 1. The decoder 7- forms a code word characterizing the position of the area of the required code alphabet in memory block 5. Upon accumulation of a code combination in the register of 1 characters, multiplication in the multiplier 2 of the received code combination by a constant is used, which characterizes the dimension of the elements in the code alphabets placed in memory block 5. The result obtained is summarized in adder 3 with the code word characterizing the position of the desired code alphabet in memory block 5. The result obtained is used to form the address in block 5 of the memory of the code 1 combination in the search alphabet using the combination of the code combination received at the input of the device. The BLOCK 4 control at the address obtained from the adder 3 is selected on the block: 5 memory code combination in the required code. At the same time, in this combination, several bits are reserved for the P key part, characterizing the character to a particular register. The information part of the combination read out from the memory block 5 is recorded in the output register 8, the service part in the first register 9 of the sign, the potentials from the output of which arrive at the comparison block 11. At SECONDS0, the inputs of block 11 compare incoming potentials from the outputs of the second register 10 of the feature, in which the source code stores the code combination corresponding to the service part of the unregistered code. If the service part read from block 5 of the gamma k9Dovoy combination does not coincide with the sign stored in the second register 1C, the output of the comparing unit 1 generates a signal that enters the control unit 4 and the AND 13 element block. implements with overwriting the service part of the code combination from the first register 9 I sign to the second register 0 of the characteristic; The control unit 4 outputs a trigger signal to the generator input 12 register symbols, which, based on the potentials taken from the outputs of the first register 9 and feature generates the proper sequence of the register and through the OR gate 14 outputs it to the communication line. The control unit 4, counting the time interval corresponding to the duration of the formation and output of the register symbol, outputs the shift pulses to the input of the output register 8, providing the output of the information code combination to the input of the OR 14 element and further to the communication channel. If the service part of the code combination read from memory block 5 coincides with the service part — stored in the second register 10 of the feature, the comparison unit 11 generates and the cell gives to the control unit 4 a signal that selects from the output register 8 and issues through the element OR 14 into the communication channel of the transformed code combination without issuing a register character. Thus, the proposed code converter, in contrast to the known one, provides not only the conversion of any registerless code into any registerless or any register code into any register code, but also any registerless code into any register code. In addition, the proposed device can also be used to convert codes with a different number of register symbols, for example a two-register code into a three-register code. At the same time, at the input of the device, when switching from one register to another, the code index changes, leading the procedure for converting two non-register codes into a given register code. Invention Code Converter according to the author. St. 792605, characterized in that, in order to convert non-register codes into register codes, an output register, register symbol generator, comparison unit, AND block, OR element, and two sign registers are entered, the first output of the parity block through the first sign register connected to the inputs of the comparison unit directly and through the serially connected block of elements AND and the second register of the sign, the output of the comparison block is connected to the corresponding input of the block of Elements AND to the input of the control unit, the second output cat This is connected to the first input of the output register, the second input of which is connected to the “second output of the memory unit, and the output of the output register is connected to the first