SU981992A1 - Adder in m from n code - Google Patents

Description

(54) SUMMATOR IN CODE M OF N

The invention relates to computing and is intended to perform arithmetic operations with numbers represented in a code of N, where N is the number of positions in a codeword; M - the number of units in the code word. A two-digit adder in code 2 of 5 is known, containing a local control device, transducers of operand codes, matrixes of AND elements, correction blocks / transfer blocks, low-order encoder, and high-value output blocks of sum 1. The disadvantage of this device is low speed, due to the transformation of the codes of the operands before feeding them to the matrixes of the AND elements, passing the signals corresponding to the sum through the two-step output unit consisting of encoders and discharge circuits, as well as the low speed matrixes of elements I. It is also known a device for summing the numbers j represented in code 1 out of 10, containing an addition matrix and an addition matrix 2. The disadvantage of this device is the absence control over the performance of aa lmetic operations. Moreover, it is not intended to perform these operations with the numbers represented in the M code of N with MVl, as the indicated blocks and the connections between them are not enough to eliminate unacceptable galvanic connections between the individual elements. part of the blocks (connections that arise when using the M code from N, where M is 2 1), the most closest to the invention is a two-way adder in the M code from N, the most significant bit of which contains additions, Ators, control unit and output units, and two. Addition matrix input groups are connected to device input buses, Addition matrix outputs are connected to transfer unit and encoder inputs, Transfer unit outputs are connected to device output buses, encoder outputs are connected to first input groups of corresponding output units, two groups of control unit inputs are connected to input the devices, the outputs of the control unit are connected to the second groups of inputs of the output units. the third inputs of the output units are connected to the corresponding inputs of the device input group, and the steps of these units are the outputs of the device 33. The disadvantages of this device are the relatively low quick action due to the need to pass signals corresponding to the half-sum (from the outputs of the addition matrix) through the two-stage unit, as well as the relatively complex structure of this unit. The purpose of the invention is to increase the speed of the adder in the M code from N. The goal is achieved by the adder in the M code from N containing the addition matrix, the input and output groups of which are connected respectively to the first and second addend device buses and the decoder control. , the first and second groups of inputs of which are connected respectively to the first and second buses of the device control, contains the output matrix of the multi-input elements I, the group of information inputs of which is connected to the group of information x outputs of the addition matrix, and the first and second control inputs of the output matrix of the multi-input elements And are connected to the first and second outputs of the decoder control, respectively, the first and second inputs of the output matrix of the multi-input elements And are respectively connected to the first and second inputs of the transfer from the lower bit of the device , and a switching unit, the group of information inputs of which are connected respectively to the outputs of the group of information outputs of the addition matrix corresponding to the transfer independent The result layer and the second and second control inputs of the switching unit are connected to the first and second outputs of the decoder control, respectively, and the group of outputs of the transfer of the addition matrix is connected to the transfer bus to the most significant bit of the device, the information outputs of the output matrix of multi-input elements And and the information outputs of the switching unit are connected to the device bus, the output matrix of the multi-: input elements H contains multi-input elements AND, which correspond to the transfer-dependent position result code words, the forward inputs of multi-input elements AND are information inputs of the output matrix of multi-input elements And, the second and third inputs of multi-input elements AND are connected respectively to the first and second control inputs of the output matrix many input elements And, the fourth inputs of multi-input elements And, corresponding to single transfers from lower order bits, are connected to the first transfer input of the output matrix of multi-input elements And, the fourth inputs of multi-input elements Corresponding to a zero carry from the least significant bit, a second input connected to the output transfer matrix elements and multi-input. FIG. 1 shows a block diagram of an adder in the M code of N in FIGS. 2 and 3, an output matrix circuit. The device contains an addition matrix 1, a decoder 2 controls, an output matrix of multi-input elements And 3 and a switching unit 4. Groups of inputs of the first and second slug unit 1 are connected to the first and second buses of the 5, 6 devices, the group of information inputs of block 3 is connected to the group of information outputs 6JroKa 1, the first and second control inputs of block 3 are connected to the first and second outputs of block 2, respectively, The group of transfer outputs of block 1 is connected to the transfer bus in the senior bit 7 of the device, the first and second groups of inputs of block 2 are connected to the first and second control buses 8 and 9 of the device, the group of transfer inputs of block 3 is connected to the transfer bus and the lower bit of the device 10, the group of information inputs 4 is connected to the outputs of the group of information outputs of the addition matrix, the corresponding transfer code word positions that are independent of the transfer, and the first and second control inputs of block 4 are connected to the first and second outputs of block 2, respectively; the outputs of blocks 3 and 4 are connected to the device cyMNfj 11 buses. Block 1 is a matrix of multi-input And elements, each of which has two galvanically independent "x outputs Z. The number of inputs for each element And is 2M. The inputs of the elements And the block are connected to the buses of the codes of the operands, - according to the selected alphabet. Bus codes operands connected to the inputs of the components of the block. Tires connecting the first outputs of the elements corresponding to the same half-sum values are connected to the group of information outputs of the block. Tires connecting the second outputs of the elements corresponding to the same transfers to the senior rank are connected to the group of outputs of the block transfer. Block 3 is a rectangular matrix of multiple input elements And 12 (FIG. 2), where Z. signals corresponding to the transfer from

the youngest bit is zero and the unit c is responsible; UKOWB, Unompa control signals; Co ,,, C ,, and Cp., / 2- signals corresponding to half sums equal to 0; i (1) and p-1, respectively, where p is the base of the number system. The matrix contains only those multi-input elements And / that correspond to (N - B - T) th positions of the result code word, where 8 are the numbers of the positions of this word, depending on the transfer from the low order (О g i N). If we take an alphabet in which the code words corresponding to any two adjacent (in the alphabet) digits differ only O from each other (by their position (in terms of the voltage levels in them), then the output $ 1 matrix has minimum dimensions: 2 p, each input of such a matrix is connected only to its one coordinate bus. If an alphabet is accepted, in which the differences between the code words corresponding to the adjacent digits are maximum, then the output matrix also has the maximum size of 3 x R. The Csd element of And is connected to one of the inputs according to . Abusive coding) of the first group of inputs, a second input and a third one of the inputs of the group transfer unit inputs block Vyhosh elements corresponding odimakovym numerals codeword result, you are connected: {odnymi bias tires with information br unit moves.

Block 2 is a control circuit for an M code of N (full Daifirator or threshold scheme), to the inputs of which code words opposite to operands are supplied.

Block 4 is a group of three-input elements I. The first input of each such element is connected to the corresponding input of the group of information inputs, and the second and third inputs are connected to the first and second control inputs of the block. The outputs of the And elements are connected to the information outputs of the block. The block contains only those elements, KOToi i.e. correspond to the knowledge of the result codeword independent of the transfer. If an alphabet is received, in which the code words, corresponding to any adjacent digits, differ from each other only by one position, then the block contains p elements AND, If an alphabet is accepted, in which the differences between the code words of the corresponding neighboring digits are maximum, then the block contains p / 2 elements I.

The proposed device works as follows.

Operands in the M code from W arrive at the input groups of the first and second terms of the addition matrix 1. One time, Signals corresponding to the return coding of the operands arrive at the inputs of the decoder 2 control. The appearance of an uncompensated error leads to the appearance of signals at the outputs of several elements of I matrix. or to absence. signals at their outputs. In the first case, there will be no signal (or both signals) at the output (or at both outputs) of the indicator 2 Control. In both cases, the outputs of the group of outputs 11 of the device will have no signals. If in the code words of operands of length N is exactly N units, the signal from one of the outputs of the first group of outputs of the addition matrix 1 and the signals from both outputs of the decoder

. 2 controls are fed to the corresponding control output matrix of the multi-input elements I 3 and switching unit 4. At the same time, the signal from one of the outputs of the group of outputs of the transfer of matrix 1 of the addition will go to the transfer bus to the high bit 7 of the device, and on one of the transfer lines from the low bit 10 of the device a signal corresponding to zero or one bit from the lower bit, enters the input of the input transfer group of the output matrix 3. After that, one or a group of (not more than M) elements AND of the output matrix 3,; the outputs of the cochors, the signals are sent to the device's sum 11 bus. In block 4 ksmmutation, at the same time, or the corresponding number of elements of the AND is triggered and signals from their outputs are sent to the sum of 11 devices, or (depending on the received

of the alphabet), no element is triggered. .

Consider an example of the construction and operation of a device for code 2 of 4 with p 6. We accept the alphabet: O - UN 3-0110

4- lOlOj

1- OlQlj

2- lOOij

5-100,

where the zero position is right on the right.

The output matrix of multi-input elements I.12, in this case, contains 16 elements AND 13-28 (Fig. 3), and the switching unit contains 4 elements I. The outputs of the elements of the last block, which are supplied with signals C, C}, or C. 4, / g 1Redited to the 0th, 0th, 1st, and .3rd (by the positions of the result code word) by the gangs of the output tire group of the device, respectively.

When adding, for example, the numbers 1 and 3, taking into account the transfer of O from the least significant bit at the corresponding inputs of the output matrix, the tc signals are

C4.il: 0 Kompi com2, as a result, the element H 27 will operate and the signal from its output will go to the output bus of the device, corresponding to the 1-ofl position of the result codeword. At the same time, the corresponding inputs of the switching unit 4 receive signals, UKOHIIJ H, as a result of which the element I is triggered and the signal from its output goes to the output output of the device corresponding to the 3rd position of the code result. The positive effect of the introduction of the device is to increase the speed by 1.5 times, since the signals in the device until the final formation of the result of the operation sequentially passes through two blocks, and in the device, taken as a prototype - through three blocks, and in reducing the nomenclature logical elements to the minimum possible number (only the AND element is used, logical OR functions are implemented by the so-called wired OR) .1

Claims (4)

Invention Formula An adder in the M code of N containing an addition matrix, the input groups of the first and second components of which are connected respectively to the first and second buses of the device's components, and the decoder of the control, the first and second groups of inputs of which are connected respectively to the first. and the second device control bus, characterized in that, in order to increase the speed of the adder, it contains the output matrix of the multi-input elements AND, the group of information inputs of which are connected to the group of information outputs of the addition matrix, and the first and second control inputs of the output matrix of the multi-input elements And connected the first and second outputs of the decoder control, respectively, the first and second inputs of the output matrix of the multi-input elements And are connected respectively to the first and second inputs I will transfer from the lower bit of the device, and the switching unit, the group of information inputs of which are connected respectively to the outputs of the group of information outputs of the addition matrix, corresponding to independent from the transfer to the positions of the code result, and the first and second control inputs of the switching unit are connected to the first and second outputs of the control decoder, respectively, the group of outputs of the transfer of the matrix of addition is connected to the transfer bus to the senior bit of the device, information the output outputs of the output matrix of the multi-input elements And the outputs of the switching unit are connected to the device's sum bus, output1; and the matrix of multi-input elements AND contains multi-input elements AND, which correspond to transfer dependent positions of the result codeword, with the first inputs of multi-input elements. And are the information inputs of the output matrix of the multi-input elements And, the second and third inputs of the multi-input elements And are connected respectively to the first and second control inputs of the output matrix of the multi-input elements And, the fourth inputs of the multi-input elements And corresponding to single transfers from the lower bit, are connected to the first transfer input of the output matrix of multi-input elements And, the fourth inputs of multi-input elements And, corresponding to the zero carry of the younger bit, are connected to the second input of the transfer of the output matrix of multi-input elements I. Sources of information taken into account in the examination 1, USSR author's certificate 259480, cl. G About F 7/50, 1966. 2.Prayigishvili I.V. and others. Microelectronics and homogeneous structures for the construction of logic and computing devices. M., 1967, p. 176, 181. 3.Assignment of the USSR on the application 2681286 / 18-24, cl. G 06 F 7/49, 1978 (prototype). 4. Orange A.M. Hardware methods in digital computing, BSU, them. V. I. Lenin, 1977, p.29. v rsJ "-4 11 hpcdpc N Hfl / 2 fcontr, 1T at i. j I counter 2 CFJT f L "./ 12 " inr - (/ d L, .5 ik $ L. shl Shl 3 22 .1 ift TTf TTF JN Ml TGG Mg, 12 Gg // 2 G, // 2 Tjj // G /,) DG; // 2  id w 17 SHHSH r 26 U TTLJT ".J.