SU1755375A1 - Radix converter between binary-decimal and binary code - Google Patents

Abstract

The invention relates to computing and can be applied to quickly convert numbers from binary to decimal and vice versa. The aim of the invention is to increase speed. The device contains a group of tetrad equivalent shapers, a group of tetrad summation nodes, a group of nodes converting a binary code into a decimal code, a group of switches and a summation unit. 8 il.

Description

The invention relates to computing and can be used to quickly convert a binary-decimal code into a binary code and vice versa.

A device is known for converting a binary-decimal code into a binary code constructed according to a one-step principle and containing a summation block consisting of multiple-input single-bit adders.

The disadvantages of the known device are relatively low speed and limited functionality, due to the impossibility of the inverse transformation of codes.

It is also known a device for converting a binary-decimal code into a binary code and vice versa, constructed according to a single-step principle and containing a binary number register and serially connected conversion stages, each of which contains a unit for selecting the highest unit, an adder, a binary-decimal coder, and a driver. binary equivalent, nine OR elements, nine comparison circuits and a binary-decimal code decoder.

The disadvantages of the known device are relatively low speed and a large number of equipment.

The closest to the present invention is a device for converting a binary-decimal code into a binary code and vice versa, built according to the multi-cycle principle and containing a binary register, two groups of switches, a group of tetrad equivalent equivalents, a summation unit, a comparison unit and a pulse distributor, with the binary the numbers are connected to the first information inputs of the switches of the first group, the second information inputs of which are connected to the outputs of the PULSE distributor, OUTPUTS KOMMVT3TO (L

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The ditch of the first group is connected to the information inputs of the binary register, the outputs of which are connected to the first information inputs of the switches of the second group, the second information inputs of which are connected to the outputs of the pulse distributor, the outputs of the switches of the second group are connected to the inputs of the drivers of equivalents of the group, the outputs of which are connected to the information inputs of the summation unit , the outputs of which are connected to the information inputs of the first group of the comparison unit, the information inputs of the second group of which connected with tires of the binary coded decimal number, the control inputs of the first and second switch groups are connected to the input mode specifying unit.

A disadvantage of the known device is low speed.

The purpose of the invention is to increase the speed of the device

This goal is achieved in that a device for converting a binary code to a binary code and vice versa, containing a group of tetrad equivalent equivalents, a group of switches and a summation unit, the output of the summation unit being the output of the device, the mode setting input of which is connected to the control the inputs of the switches of the group, the group of nodes of the tetrad summation and the group of nodes of conversion of the binary code into the decimal code are entered, and the information inputs of the device group are connected to the information the mapping inputs of the corresponding group tetrad shaper equivalents, the outputs of which are connected to the inputs of the corresponding tetrad cluster summation nodes, the outputs of which are connected to the first information inputs of the corresponding group switches and the inputs of the corresponding binary code conversion nodes into the decimal code of the group, the outputs of which are connected to the second information inputs of the corresponding switches of the group, the outputs of which are connected to the inputs of the corresponding components of the summation unit , Specifying the input mode which is connected to the reference input mode formers tetrad equivalents group and to the input device specifying mode

Figure 1 shows a block diagram of a device for converting a binary-decimal code to a binary code and vice versa, figure 2 shows an order of forming tetrad equivalents for converting binary-decimal codes in the range of 0- 39999 and binary codes in the range of 0- 65535; Figs 3-7 illustrate examples of constructing the formers of tetrad equivalents of a group for tetrads with the first one according to the fifth, respectively; Fig. 8 is a functional diagram of the first tetrad-summing node of the group.

The device for conversion contains a group of shapers of 1i-1m tetrad equivalents, a group of nodes 2i-2m. tetrad summation, a group of nodes 3i-3m converting binary code into a decimal code, a group of switches 4- | -4t,

5 block 5 summation, group 6i-6m of information inputs of the device, input 7 of setting the device mode (when converting the binary-decimal code, the signal of the logical unit is fed to 7i, when converting the binary code to the bus 72 of input 7), output 8 of the device .

Information inputs 6i-6m device groups are connected to the information inputs of the respective drivers

5 1i-1m tetrad equivalents of the group, the outputs of which are connected to the inputs of the corresponding nodes 2i-2m of the tetrad combination group, the outputs of which are connected to the first information inputs of the corresponding switches 4i-4m group and the inputs of the corresponding nodes of the 3i-3m conversion of the binary code to dec the specific code of the group, the outputs of which are connected to the second information

5 inputs of the corresponding switches 4- | -4t groups, the outputs of which are connected to the inputs of the corresponding terms of the summation unit 5, the mode setting input of which is connected to the inputs of the mode setting

0 driver 1i-1m, switches 4i- 4m and input 7 of the device mode setting. The 1i-1m shapers are designed to form binary and binary-decimal tetrad equivalents. In the upper part of the table in Fig. 2, the formation of binary tetrad equivalents for converting a 5-bit binary decimal code whose binary bits are denoted with dashes Hami a, b, c, g,. .., s, p1, in the lower part of the table, the formation of binary-decimal tetrad equivalents for the conversion of a binary code, the binary bits of which are denoted by letters without

5 strokes a, b, c, gp, p. It is assumed

that the range of convertible binary-decimal codes is 0-39999, the range of convertible binary codes is 0-65535. In FIG. 2, the values of those binary bits of the corresponding binary and binary-decimal equivalents, which depend only on the values of the bits of the convertible codes and do not depend on the mode (direction) of the conversion. The values of the other binary bits of the corresponding binary and binary-decimal equivalents depend on both the values of the binary bits of the codes being converted and the conversion mode.

According to the table in FIG. 2, functional circuits of the formers 1i-l5 are constructed. Shaper 1i contains elements AND 9i-9i8 and elements OR 10i-104, shaper 12 elements AND 111-1124 and elements OR 12i-12g, shaper 1h - elements AND 131-1320 and elements OR 141-144, shaper 1-elements AND 15i -15io and OR elements, shaper 1g - elements AND 17h-17z. When a single signal is applied to the bus 7 input 7, the device is configured in the 1i-1s generator with binary tetrad equivalents for the initial convertible binary-decimal code, and when input 7 is fed to the bus-binary decade equivalents for the initial binary conversion code.

The 2t-2m nodes of the tetradic summation of the group carry out the binary summation of arrays of tetrads of equivalents formed at the outputs of the formers, respectively, 1i-1m. Nodes 2i-2m can be built using any known methods and means. Figure 8 shows, as an example, the construction of the tetrad-summing node 2i on single-bit binary adders 18i-18ie. The node 2i performs the summation of the binary digits generated in the imaging unit 1i.

The order of transferring information from imaging device 1i to node 2i is as follows. For example, seven binary digits with a weight of 21 are formed in shaper 11 (two digits come from the d and b buses, and five digits are generated at the outputs of the AND 9i-9si elements. Next, these seven binary digits with a weight of 2 arrive at the inputs of one-bit binary adders weighing 2 nodes 2i, which are used for their binary summation with transfer of the resulting transfers to the next weight position with weight 2 nodes 2i. The order of supply of these seven binary digits to the inputs of single-digit binary adders 18i-18s is arbitrary. For example, to the inputs of one-bit bottom adder 18i You can apply three binary digits formed at the outputs of elements AND shaper 1i, to the inputs of a one-bit binary adder 182 — two binary digits from the outputs of elements AND 94-9s and one binary digit from a bus b shaper 1i, to the input of a single-bit binary adder 18z - single binary digit with

tires d shaper 1i fig.Z. Similarly, other inputs of node 2i are connected to the outputs of the driver 1- |.

The nodes of the group are designed to convert to the decimal code of the results generated in binary code at the outputs of the nodes, respectively, of 2i-2m tetrad group summation. They are combinatorial nodes and can be constructed by any known means.

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Using the 4i-4m rpynm switches, the summation unit 5 is transferred to the equilibrium inputs, or binary result codes from the outputs of nodes 2i-2m tetrad summing (binary-decimal code to binary code conversion mode), or ten result codes from the outputs of nodes 3i-3m converting a binary code into a decimal group code (mode of converting a binary code into a binary decimal code).

Each bit of the 4i-4m switches can be built on a single 2I2IL element.

Block 5 is intended for binary (the mode of converting a binary-decimal code to a binary code) or decimal (the mode of converting a binary code to a binary-decimal) summation

results formed at the outputs of switches 4i-4m group, It can be constructed by any known method.

The device works as follows.

The mode of converting binary-decimal code to binary code. After submitting to the information input 6 of the device the convertible binary-decimal code under

The signals at the output 7 of the device mode setting (a single signal is sent through the bus 7i, a zero signal via the bus 72) the binary tetrad equivalent values are formed in the group of operators, which are then summed up in the tetrad sum nodes 2i-2m according to the rules of binary arithmetic. The binary results formed at the outputs of nodes 2i-2m with the resolution of the signals at input 7 of the device are transmitted through the switches 4i-4m of the group to block 5, where they are binary summed. The result formed at the output of block 5 is the binary equivalent of the binary-decimal code fed to the device.

The mode of converting a binary code into a binary-decimal code.

After the convertible binary code is fed to the information input 6 of the device under the action of signals at the input 7, the device mode is set (a zero signal is supplied via bus 7i, and a single signal is transmitted via bus 1g) in the 1i-1m group of binary tetrad values. equivalents, which are then summed at nodes 2i-2m tetrad summation according to the rules of binary arithmetic. The binary results formed at the outputs of the 2h-2t nodes are then fed to the nodes, respectively, 3i-3m groups, in which the binary codes are converted to decimal codes. With the resolution of the signals at the input 7, the devices formed in the decimal code at the outputs of the nodes 3i-3m are transmitted through the switches 4i-4m to the equilibrium inputs of the unit 5, in which they are decimated. The result formed at the output of block 5 is the binary-decimal equivalent of the binary code device present at the input b.

The proposed reverse conversion device allows fast conversion of a binary-decimal code to a binary code and vice versa at moderate hardware costs, since for converting a binary code into a binary-decimal code, the equipment intended for

converting binary-decimal code to binary code.

Fo rmula and zoopen Device for converting a binary-decimal code into a binary code and back, containing a group of tetrad equivalent equivalents, a switch group and a summation unit, the output of the summation unit a device whose mode setting input is connected to the control inputs of a group of switches, characterized in that, in order to improve speed, it contains a group of tetrad sum nodes and a group of binary code to ten code nodes, and inform The device group inputs are connected to the information inputs of the corresponding group of tetrad equivalent equivalents, the outputs of which are connected to the inputs of the corresponding tetradic group summing nodes, the outputs of which are connected to the first information inputs of the corresponding switches of the group and the inputs of the corresponding nodes converting the binary code into the decimal code of the group, the outputs which are connected to the second information inputs of the corresponding switches of the group, the outputs of which are connected to odes corresponding terms summing block specifying input mode which is connected to the reference input mode formers tetrad equivalents group and with inputs specifying device mode,

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Claims (2)

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