SU980095A1 - Microprogrammme processor - Google Patents

Description

one

The invention relates to digital computing technology and can be used in designing processors for fault-tolerant microprogrammed computing systems.

A two-channel firmware control device of a duplicated computing system is known in which a tactical comparison of micro-instructions is performed. The device contains an address driver, a memory block, a micro-driver, a switch, and a trigger 1.

The disadvantage of this analog is low functional reliability, due to the lack of recovery tools when one of the channels leaves the building block. 20

Known firmware processors with self-diagnostics, containing duplicated processing units.

local memory blocks and main memory block 2,3 j.

The disadvantages of these processors are the large amount of additional backup hardware and the need to develop sophisticated software to reconfigure the processors.

Also known is a firmware with self-diagnostics, containing the first and second information processing units, a switch, a comparison circuit, a trigger, main memory blocks, address and data registers, a block. microprogram memory, address operators and microoperations.

The deficiency of the indicated analogue is a large amount of control means and the complexity of the restoration of working capacity in the event of a failure.

The closest to the proposed technical essence and achievable effect is the processor containing the main memory block, address register, data register, buffer memory block, two local memory blocks, two operational blocks, the first switch, the first b / uk elements And, the comparison circuit, the first driver of the microinstruction address, the microinstructions memory block, the control trigger, the microoperation forger, the first output of the main memory block connected to the data register input, the first output of which is connected to the first input and the first and second blocks of local memory, respectively, the second output is with the first input of the first driver of the micro-instructions address, the third through the address register with the first input of the main memory block, the second input of which is connected to the first input of the buffer memory block and the first output of the driver micro-operations, the second output - with the second input of the buffer memory block and the first input of the micro-operations former; the third input - with the output of the first block of And elements, the first input of which is connected to the output of the first switch, the second input - with The first output of the first microinstructor address shaper, the second input of which is connected to the output of the comparison circuit, the third input is the device sync input, the fourth input is connected to the second output of the microoperations shaper, the second input of which is connected to the output of the microinstruction memory unit, the third output is control inputs of the first switch, the first information input of which is connected to the first input of the comparison circuit and the first output of the first operational unit, the second output of which is connected to the second input the first local memory block, the first output of which is connected to the first input of the first operational block, the second input of the comparison circuit is connected to the second information input of the first switch and the first output of the second operational block, the second output of which is connected to the second input of the second local memory block, the output of which is connected to the first input of the second operation unit 51. The disadvantages of this processor are low fault tolerance and low reliability of operation of the 5 8 prototype is realized as blowing operation of discipline. The results of two parallel processing information processing channels are compared. When they coincide, data is exchanged with the main memory of the processor, with one of the channels being defined as main and the second as backup. In case of discrepancy of results on. the channel output forms a control signal by which the processor is blocked, the contents of the channels are transferred to the buffer memory, and then the failed channel is determined using special diagnostic equipment. Based on the diagnostic results, the contents of the healthy channel are restored and the processor continues to operate in single-channel mode. Low fault tolerance is due to the fact that when there is a second failure (the first failure in another channel J, the processor loses its functionality) This disadvantage limits the possibility of using the processor in systems with an accumulation of failures. Low reliability of operation is due to the fact that if there is one failure, the processor goes into single-channel mode and parity control of the correctness of information processing is not produced. In addition, the prototype has a long diagnostic time, which is due to the fact that in the diagnostics mode, the failed or the element is determined, but not the failed microcommands, and the information is not used for the diagnostics when transferring it to the buffer memory. low reliability of operation and long diagnostic time. Microprocessor processor significantly limits its scope, reduces the efficiency of tasks. The purpose of the invention is to increase the fault tolerance and reliability of the operation of the microprocessor processor. The goal is achieved by a microprocessor processor containing a main memory block, an address register, a data register, a buffer memory block, the first and second local memory blocks, the first and second operational blocks, the first switch, the first block of AND elements, the comparison circuit, the first driver of the micro-command address, the control trigger, the micro-command memory block and the first driver of the micro-operations, the first information output of the main memory block connected to the input of the data register, the first output of which is connected with the first inputs of the first and second local memory blocks, the second output of the data register is connected to the input of the operation code of the first microcommand generator, the control output of which is connected to the inverse inputs of the first block of elements And, the third output of the data register is connected to the input of the address register whose output is connected to the first address input of the main memory block, the second information output of the main memory block is connected to the first information input of the buffer memory block and the first input of the microoperation generator the output of microoperations of which is connected to the control input of the main memory block and the control input of the buffer memory block, the output of the first switch is connected to the input of the first block of elements I, whose output is connected to the information input of the main memory block, the output of the microcommand memory block connected to the second input of the microoperation driver, whose address output is connected to the address input of the first micro-command address driver, the output of the first operating unit is connected to the first information input of the first terminal mmutator and the first input of the comparison circuit, the output of which is connected to the control input of the microinstruction address generator, the output of the second operation unit is connected to the second input of the comparison circuit, and the second information input of the first switch, the forward and inverse control inputs of which are connected micro-operations, the second output of the first operational unit is connected to the second input of the first local storage unit, the output is costly connected to the first information input of the first operational unit The second output of the second operational block is connected to the second input of the second local memory block, the output of which is connected to the first information input of the second OPV block, the synchronization input of the microcommand address generator is connected to the clock input of the device, the second and third switches are introduced, the second, third and the fourth block of the AND elements, trigger mode, the second address generator of microinstructions, the address counter, the first, second and third OR elements, the first and second one-shot, the OR-NOT element, and The output output of the buffer memory unit is connected to the first information inputs of the second and third switches, the output of which is connected to the second inputs of the first and second operating units; the output of the microoperations of the microoperations generator is connected to the second information inputs of the third and second switches, the output of which is connected to the third inputs of the first and the second local memory blocks, the output of the first element OR is connected to the input of the first one-oscillator, the output of which is connected to the first input of the second element This OR, single output of the control trigger is connected to the second input of the second OR element, the output of which is connected to the direct and inverse control inputs of the second and third switches, the second control output of the microoperation driver is connected to the single input of the mode trigger, the single output of which is connected to the first the input of the second block of elements AND, the output of the microoperations of the imaging device is connected to the second input of the second block of elements AND, the output of which is connected to the inputs of the first OR element and the inputs of the second form The micro-address address gate, the output of the second micro-address address generator is connected to the first input of the third block of elements I, the output of which is connected to the information inputs of the address counter; the third block of the AND elements, the second control output of the buffer memory block is connected to the first input of the third element 980 ment OR, the output of which is connected to the installation input of the address counter and Nya Ullevi trigger control input, a third control output j block buffer memory connected to the input of the second monostable and counting input of the address counter, which outputs are connected with the second informational input of the buffer memory and inputs elementals NOR targeted yield per-O

the microinstructor address driver and the output of the OR-NOT element are connected respectively to the first and second inputs of the fourfold block of elements AND whose output is connected to the input of the microinstructions memory block 5, the output of the code of failed microcommands of the microoperations former is connected to the second address input of the main memory block, the output the comparison circuits and the output of the second one-shot are connected respectively with the second and third inputs of the third OR element, the setup input of the device is connected to the zero input of the mode trigger, Entity and The invention consists in increasing the fault tolerance and reliability of the operation of the microprocessor processor by using the functional redundancy of micro-commands and replacing the micro-commands that manage the failed Functional Channel Blocks corresponding to the equivalent micro-command sequences. Mn6: a feature of the micro-commands that form the Microoperative basis of the MD system, as a rule functional redundancy. A multitude of micro-commands MD can be represented by combining a subset of micro-commands of ML, without which all the required operations and subsets of micro-commands M.2, additionally introduced to provide a given level of system performance, cannot be implemented. Therefore, part of the microinstructions of the subset M.1 can be performed by implementing an equivalent sequence of other microinstructions from the subsets .M.1 and M.2. For example, the microcommands of the multiply operation can be replaced by a sequence of add and shift microcommands. This allows for most microinstructions to form equivalent replacement sequences and use them with appropriate failures to restore operability.

compiles a list of failed microinstructions; equivalent buffer sequences of microcommands that can be replenished as faults accumulate are stored in the buffer storage unit; when a failure appears in one of the channels, determining the failed microcommands and masking the corresponding equivalent substitution points. failure of the corresponding functional block (and not the functional blocks themselves; based on the results of microdiagnostics of sequences in the buffer block m ti, the CPU firmware passes the second normal operation mode, which is characterized potaktnym reference to the block buffer memory in order to check the need to perform the equivalent of substitute microinstruction sequence.  In order to implement the invention, the second and third switches, three blocks of AND elements, three OR elements, OR-NOT element, second trigger, second micro-command address generator consisting of a decoder and an encoder, two single-vibrator, and an address counter are added to the microprocessor processor.  I. The code of the microcommand read from the microcommand memory block into the microoperation driver is divided into five fields: the end field of the execution of the diagnostics microprogram; code field of executed micro ops; control label field for outputting processed information from the first or second channel to the main memory block; the address code field of the next micro command; by-; le code of failed microinstructions.  The code of microinstructions introducing into the equivalent substitution of a sequence of microinstructions consists of three fields: the label field. defining the need to perform this equivalent substitution of a sequence of microinstructions by kDc; micro-code field; label field read information.  9 The introduction of the second and third switches and the connections related to them allows one to control the processing of information in both channels either by microcommands from the microoperator, or by microinstructions included in the equivalent substitution sequence of microinstructions and read from the buffer memory block .  The introduction of the fourth block of AND elements, the OR-NOT element, and the links due to them is necessary to control the output of the next address. micro commands in the microinstruction memory block only after the execution is equivalent to replacing the effective sequence of microinstructions executed instead of the failed microcommand.  The introduction of the mode trigger, the second driver of the micro-instruction address, the second block of the AND elements and the connections due to them allows the address of the first micro-command of the equivalent replacement command for the failed micro-command to be written into the address counter.  The second address generator of the micro commands can be made in the form of a programmable logic matrix.  Since the list of micro-instructions that can be replaced by equivalent sequences is known, the operational parts of these micro-instructions set the address of the initial micro-command to the equivalent replacement sequence.  For example, if the complete set of replaceable microinstructions consists of the microcommands R, R,. . . The RK decryption of the second address resolver has K borshoot and H inputs (if is the width of the operating part of the W micro-commands R, i e 1, k).  At each of the outputs of the decoder di, the function r is realized; where is binary variable of j-th bit of the operating part.  The second coder encoder address in this case has the inputs and E.  outputs, where g -} eog-2 Z W, 95 is the number of microinstructions, where f4 | equivalent replacement sequence for the i-th micro-command.  The encoder generates binary codes at its outputs by bit size,.  which correspond to single signals from the output of the decoder.  These codes specify the starting addresses of equivalent replacement sequences.  The introduction of the address counter is necessitated by the need to form the addresses of micro-instructions that are included in the equivalent replacement sequence of micro-instructions, and the reading of the microcommands at these addresses from the buffer memory block.  The connection of the third control output of the buoyer memory unit to the counting input of the address counter and the introduction of the third OR element, the second one-shot and the connections due to them are necessary to increase the contents of the address counter in the micro-command reading process, which is part of the equivalent replacement micro-command sequence, and zero it. upon completion of the sequence or upon failure during its execution, the introduction of the first and second elements of OR, the first one-shot and the relations resulting from them, allows lock the execution of the next micro-command, read from the output of the microoperations former, for the time it is checked whether it belongs to the number of failed micro-commands.  FIG.  1 shows a functional diagram of the firmware processor; in fig.  2 is a functional diagram of local memory blocks executed identically; in fig.  3 is a functional diagram of operating units executed identically; in fig.   - Functional block diagram of the main memory; on league.  5 is a functional block buffer circuit; in fig.  6 is a functional diagram of the first interpreter of microinstructions addresses; in fig.  7 is a functional diagram of a microoperation shaper.  An example of the coding of fields of equivalent replacement sequences of micro-instructions for failed and non-returning micro-instructions is shown in FIG.  eight.  119 FIG.  1, the following symbols are used: the second switch 1, the first local memory block 2, the second local memory block 3, the first operational block k and the second operational block 5 main memory block 6, data register 7, address register 8, third switch 9 , comparison circuit 10, first switch 11, first AND block 12, buffer memory block 13, control trigger 1, first driver of microcommand addresses 15, fourth block of AND 16 elements, microcommand memory block 17, microoperation driver 18, second block 19 ee Andov, second shaper 20 The addresses of microinstructions, 1 st of the decoder 21 and the encoder 22, the third block 23 elements AND, the third element OR 2, the counter 25 of the address of the element OR-NOT 2b, the second one vibrator 27, the trigger 28 mode, the first element OR 29, the first one-wave the torus 30, the second element OR 31, the synchronization input, the input 33 of the installation of the trigger 28 to zero.  FIG.  2, the following designations are used: third input 3 of the local memory block, decoder 35, cipher 36, and switches 37, V first registers 38, Y) second registers 39, first AO input of local memory blocks, output 1 of local memory block , second input 2 local memory blocks.  FIG.  3, the following designations are used: the second input k3 of the operation unit, the decoder kk, encoder, switch 46, adder 7, register 8, the second input 9 of the operation unit, the first 50 and second 51 units of the And elements, the first 52 and second 5 outputs of the operation unit accordingly.  FIG.   The following notation is used: information input 5l of the main memory block, register 55, first storage 5b of information, first address input 57 of the main memory block, control input 58 of the main memory block, first element 59, record 60 input pulses, input 61 read pulses, second element 62, third element 63, the second storage device 6C of information, the second 65 address input, the first 66 and the second 67 information outputs of the main memory, respectively.  5 In FIG. 5, the following symbols are used: control input 68 of the buffer memory block, first AND block 69, OR block 70, information storage 71, first 72 and second 73 information inputs of the buffer memory block, second element block 7 And, the first element OR 75, the input 76 write pulses, the first 77 and second 78 elements AND, respectively, the input 79 of the constant generator generator (the flow of a constant level of a logical unit, the second element OR 80, the third element AND 81, the input 82 of read pulses, the fourth Element AND 83, first control, info mation 85, third 86 and second 87 control outputs block buffer memory, respectively.  In FIG 6, the following designations are used: input 88 of the operation code and control input 89 of the first driver of micro-instructions addresses, respectively, encoder 90, block 91 of elements OR, register 92 of address, first one-shot 93, first block of 9 elements And, third element AND 95, first element And 9b, the second block 97 elements And, fifth. AND block 98, second buffer register 99, third AND block 100, first buffer register 101, OR element 102, comparison circuit 103, second single vibrator 104, And fourth element block 105, And 106 second element, fault counter 107, first 108 and the second 199 triggers, sync and addressable WMO. DY 110 and 111 of the first driver address micro-commands, respectively, address and control outputs 112 and 113 of the first. shaper addresses microinstructions, respectively.  On league.  7, the following designations are used: the second input 114 of the microoperation generator, the register of 115 microinstructions, the group of first decoders 116, the decoder 117, the first input 118 of the formaker, and the element 120, the trigger 120, the first 121 and the second 122 ovibrators, respectively, the address output, the first control output, code-outs of micro-instructions, micro-operations and the second control output of the micro-operations former 123-127, respectively.  8 The following notation is used: 1-3 - columns of the first third fields of microinstructions included in the equivalent replacement sequence of microinstructions, respectively E1 - equivalent replacement sequence for microinstructions Ai, -, j I i-1, i, i + -lj.  The purpose of the main elements of the functional scheme of the microprocessor processor (FIG.  1) consists of the following.  Switch 1 is intended for switching of microoperations coming from the former 18 microoperations or from the block 13 of the buffer memory to the third inputs of the first and second blocks of the local memory 2 and 3, respectively.  BLOCKS 2 and 3 of the local memory are intended for the storage of operands and intermediate results of information processing.  Operational blocks k and perform the conversion of information on microcommand, coming from the switch 9.  Operands are received at the first inputs, operational blocks and 5 from blocks 2 VI 3 of the LOCAL memory, and the corresponding operations are performed on them.  The result of the calculation is provided to the second inputs of the local memory blocks, to the switch 11 and to the comparison circuit 10.  Block 6 of the main memory is intended for storing data and commands and addresses of initial microcommands that are included in equivalent substitutions of the sequence of microinstructions.  The data register 7 is designed to receive and store the next instructions of the program being executed, the incoming ones and the main memory unit 6.  Operands from the first output of register 7 arrive in blocks 2 and 3 of the local memory.  Register B addresses are used to store the address of the next command.  The switch 9 is intended for switching the microoperations coming from the output of the 18 micro-operation generator or from the output of the buffer memory block 13 to the second inputs of the first t and the second 5 operating units, respectively, depending on the operation mode.  / Comparison circuit 10 is intended for comparing the results of information processing in the first t and second 5 operation blocks and outputting a signal at the output in case of a mismatch.  95U Switch 11 is designed to switch information from the first k or second 5 operating unit to main memory unit 6, And 12 elements of the block is designed to transfer the processed information from the output of switch 11 to the input of main memory unit 6 and block this transmission when an occurrence failure in one of the channels of the firmware processor.  The buffer memory unit 13 is designed to store equivalent replacement sequences of micro-instructions.  The trigger k is designed to control through the second element OR 31 switches 1 and 9, depending on the operating mode of the firmware.  Shaper 15 addresses of micro-instructions are designed to generate addresses of micro-instructions and issue control signals to the second input of the first block of 12 elements I.  Block 1b of the And elements is intended to control the reading of micro-instructions from block 17 of the memory of micro-instructions at the address formed in the first driver 15 of the address of the micro-instructions.  Block 17 of the microinstructions memory is intended for storing microinstructions used in processing information and executing the diagnostics firmware.  Micro-operation generator 18 is designed to form micro-operations that process information, to form codes for the numbers of failed micro-instructions, to form the address of the next micro-command, to generate a diagnostic execution end signal and a processor start-up signal after the failure has been restored, to control the outputs of the operating units A and 5.  Block 19 of the And elements is designed to control the issuance of the code of the first microcommand of an equivalent replacement sequence from the output of the microoperations driver 18 to the input of the driver 20 for the microcommand addresses.  The micro-command address builder 20, consisting of a serially connected decoder 21 and an encoder 22, is designed to form the address of the first micro-command equivalent to a replacement sequence of micro-commands, which through block 23.  elements And is fed to the input of the counter ka 25 address.  The address counter 25 is designed to read at the address stored in it from the block 13 of the buffer memory of micro-instructions that are R equivalent to the replacement sequence of micro-instructions.  The OR element is designed to transmit a reset signal to the address counter 25 and the control trigger 14 from the output of the comparison circuit 10, the one-shot.  27 and output of block 13 of the buffer memory.  The element OR-NOT 2b is intended to form control signals for the block of 16 elements I.  A single vibrator 27 is designed to generate a zero signal for the address counter 25.  .  The mode trigger 28 is designed to control the code of the micro-instruction code through the block 19 of the elements AND in the operation mode after the failure has been restored.  The one-vibrator 30, the OR elements 31 and 29, are designed to prohibit the wiring of micro-operations from the output of the micro-operation generator 18 to the inputs of blocks 2 and 3 of the local memory and the inputs of the operating units 4 and 5 for the next micro command to check if it is necessary to replace the equivalent sequence of microinstructions.  The purpose of the main elements of the functional scheme of the local memory block (. Fig, 2) is as follows.  The code converter, consisting of the decoder 35 and the encoder 36, converts the codes of the microoptions arriving at the third input of the local memory block 3f and the control signals that go to the control inputs of the switches 37 and the synchronization input fl / second registers 39 Switches 37 are intended to transfer information from the first input or from the second input 2, from the output of the corresponding second register 39 to the corresponding register 38 (when restoring information).  The registers 39 are designed to store information and issue it to the input of the corresponding registers 39 and the output of the block hi, Block 2 (3) of the local memory operates as follows.  According to the next code of micro-operations, through the corresponding switch 37, the operand from the input of the AO block of the local memory is recorded in the register of pollutants and stored in it or then transmitted to the operating unit.  In this way, we record, store and output information to the operating unit when processing information received at the input k2 of the local memory block or from the output of the corresponding register 39.  If the information is the result of executing the program in the -j -; control point and must be stored until the result of executing the program in the C1 + 1) -th control point, then this information is stored in the corresponding register.  39- Signal. recording information at the control point is fed to the synchronization input of register 39, after which the information from register 38 is rewritten into register 39.  The purpose of the main functional elements of the operating unit (Fig. H) is as follows.  The code converter, consisting of decoder A and encoder 5, is transformed. enters the micro-operation codes arriving at the input 43 of the operation block into the control signal codes controlled by the switch 46 and the blocks 50 and 51 of the elements I.  The switch 46 is designed to transmit information from the output of the register 48 or from the input 49 to the input of the adder 47, depending on the micro-operation code at the control inputs. .  Blocks 50 and 51 of the And elements are intended for issuing information from the operation unit to the local or main processor memory.  Operational unit 4 (5) operates as follows.  By micro-operation codes, a control signal code is generated, by which.  This information from the input 49 through the switch 46 is fed to the input of the adder 47.  Further, control signals are used to supply information from the output of the register 48 to the input of the adder 47 and from its output to the input of the register.  After completion of the processing, the information opens blocks 50 or 51 of the elements AND, and information from the output of the register kB enters the first 52 or second 53 outputs of the operation unit.

The purpose of the main functional elements of the main memory block (Lig. Consists of the following.

Register 55 is designed to receive the processed information from the input and then write to drive 5b.

The drive 56 is designed to store data and commands. The first 59 and second 62 elements And the signals of micro ops arriving at input 58 form the write and read signals, which are used to write to register 5b of register contents 55 and read the next command at the address to input 57

The drive 6 is designed to store the addresses of the first micro-instructions of equivalent replacement sequences of micro-instructions. Element And 63 is intended to form a signal for reading information at the address that is fed to the fourth input 65.

The main memory unit operates in three modes.

1. The recording mode of information received at input S Information from the first 4 or second 5 operation units is fed to the input of block 6 of the main memory and written to register 55.

The micro-operation code opens the AND 59 element. The write pulses through the AND 59 element are fed to the input of the accumulator 5b and the contents of the register 55 are written to it

2, the read mode of the next command.

The code of micro-read operations is fed to the input of element AND 62. The read pulse is transmitted through element AND 62 to the input of accumulator 56 and at the address received at address address 57 of accumulator, the next command is read and sent to first output 66

3 The mode of reading the addresses of initial micro-instructions of equivalent replacement sequences of micro-instructions. The code of micro-read operations enters the input of the element And 63. The read pulses through the element And 63

arrive at the input of the second accumulator b and at the address coming from the input 65 read out at output 67 the address of the initial microcommand equivalent sequence of the failed microcommand,

The purpose of the main functional elements of the buffer memory block (Fig. J) is as follows.

The blocks b9 and 7 elements AND, the block 70 elements OR form the address at which the microcommands are written or read into the equivalent substitution sequence of microcommands.

Element OR 75 first 77 and second. 78 And elements are intended for recording in the first field of micro-instructions at the selected address of a single signal.

The OR 80 element and the AND 81 element are intended to form a read signal at a given microcommand address, which is part of the equivalent substitution sequence of microcommands.

The drive 71 is designed to store equivalent replacement sequences for micro-instructions.

Element 83 is designed to form an address setting signal 25 in the zero state, when reading from the buffer memory block 13 the first micro-command of an equivalent replacement sequence of micro-commands for the non-return micro-command.

The address of the next microcommand entering the equivalent replacement sequence of the microcommand enters through input 72 to the input of block 69 of the elements AND and to the inputs of the element OR 75The microoperational signal enters the input of block b9 of elements I. The address of the microcommand from the output of block b9 of elements enters the input of block 70 of the OR elements and through it further on .Address input of the accumulator 71. The signal from the output of the OR element 75 opens the first 77 and second 78 elements I. And the recording signal enters the input of the element AND 77 and through it to the recording input of the accumulator 71 a a single signal from input 79 through the element And 78 enters the information input of the accumulator and writes one into the first microcommand field. The reading of micro-instructions from the buffer memory block i3 is performed as follows. The micro-command address enters through the AND 7 block of the element block OR 70 and the address input of the accumulator 71, as well as the OR 80 element opens the AND 8K element. The read signal through the AND 81 element enters the read input of the accumulator 71 and reads the microcommand at the selected address. When reading the first micro-command of each equivalent substitute sequence of micro-commands with the help of the element 83, it is checked whether the given micro-command failed. The purpose of the main functional elements of the first driver 15 addresses microcommands (Fig. (Y) consists of D as follows Register 92 is designed to store the address of the next microcommand and output it to the output 112 of the TV builder address microinstructions. Block 9t elements OR is intended to record information address register 92 or from the input 88, or from the output of the encoder 90, or from the outputs of blocks 9, 97, 105 of the elements I. The encoder 90 is intended to form the address of the first microcommand of the diagnostics microprogram upon the appearance of a noncomparison signal. Bubble vibrator 93 is designed to run the encoder 90 when generating the first microcommand microdirectory diagnostics diagnostic program.A blocks 9 and 97 of the And elements are designed to control the transfer of the next microcommand or the address of the next microcommand of the control point to the corresponding points of the microprocessor processor. Buffer 101 is intended to store the address of a micro-command that caused the failure or failure of the microprocessor to perform. The 100 I block is designed to transfer the address of the failed microcommand from the information output of the address register 92 to the input of the first buffer register 101 when the input of the block 100 contains elements AND of the signal from the comparison circuit 10 and the signal does not come from the output of the OR 102 element. storing the address of the microinstruction in the control point. Comparison circuit 103 is designed to compare the address of a micro-command stored in buffer register 1.01 by the address of a micro-command received at input 111 from the microoperator 18 and issue, if these addresses are equal, the signal to the zero input of the trigger 109 and the setting input of the counter 107. The single-oscillator 10 is designed to issuing after the execution of the diagnostics firmware of the pulse, authorizing its transmission of the micro-command address from the buffer register 99 through block 105. elements AND to the input block 91 elements OR. Failure counter 107 is designed to count the number of firmware repetitions. The trigger 108 is designed to put the shaper 15 of the microinstruction addresses and the entire processor into the diagnostic firmware execution mode. A trigger 109 is designed to issue a write blocking signal to block 6 of the main memory of information from operating units and 5 and enable its recording when a failure is eliminated. The first driver 15 addresses of micro-commands operates as follows. The operation code goes through the input 88 to the input of the element block OR 91 and further to the address register 92. Then, via the output 112, the address goes to the micro-command memory block 17, where the first micro-instruction is read. The address of the microcommand via input 111 is fed to the input of block 9 of the elements AND, and after the microcommand has been executed, a synchronization pulse is transmitted to the input of block 91 of the elements OR. Further, the address generator 15 operates in a similar manner. When a microcommand is executed at a control point, its address from the output of address register 92 through AND block 98, opened by the signal from the control output of register of address 92, that signal for information processing microcommands at the control point is equal to one, otherwise remaining), goes to register 99. With

the occurrence of a failure in the operation of the firmware processor at input 89, a signal with 10 comparisons appears. In this case, the address of the microcommand that caused the s to fail, from the output of the register 92 of the address through the block 100 of elements AND opened with a signal from the comparison circuit 10, is written into the buffer register 101. the element AND 9b is closed and the address of the following microcommand is not transmitted to the input of the block 91 of the elements OR. At the same time, the signal from the comparison circuit 10 through element 15 and 96 opens the block of elements 97, through which the address of the information processing micro-command at the control point from the buffer register 99 goes to the input of the block. 107- With this signal, the trigger 109 is set to one.

The firmware starts to run again 25 seconds from the checkpoint according to the algorithm described above. If the address of the next microinstruction and the microinstruction address, during which the failure occurred, coincide and the control input of the comparison circuit 103 does not have a fault signal from input 89, the sweeper 107 and the trigger 109 zero the signal from the comparison circuit 103 and the firmware continues jj If, when performing a next microcommand whose address is located between the addresses of the microcommand at the control point and the microcommand that caused the failure, a malfunction signal is received from the comparison circuit 10, then this signal increases the soda zhimoe counter 107 by one and the address register 92 again zapishets microinstruction address in control- .. hydrochloric point and data processing continues as after the first occurrence of SRB.

If the number of failures exceeds the critical one, then the counter 107 overflows 50 and the output signal sets 6 single state trigger 108, the signal from the single output of which closes the elements 9b and 106, opens the element 95 and starts the one-shot 96. 55 The output signal of the one-shot 93 starts the encoder 90, while closing the block of 9 elements I. From the exit

the encoder 90 "the address of the first micro-command of the diagnostic firmware enters through the block 91 of the elements OR to the address register 92. Next, a diagnostic micro-program is performed to determine the failed microcommands. The signals received from the circuit 10 compared to the 1st input to the second input 89 measure the element AND 95 to the input of the block 91 elements OR modify the address of the following microcommand.

After the diagnostics firmware has been executed, the signal entering input 111 is set to the zero state of the trigger 108. This starts the one-shot 10, the output of which opens 1 block 105 of the elements AND and addresses of the information processing command from the buffer register 99 through the block of 10 elements And 91 elements OR arrive on the Christmas tree. Next, the microinstructor address builder operates in the information processing mode after the failure has been restored. The algorithm of operation in this mode is similar to the algorithm of operation until a failure occurs in the firmware program.

The purpose of the main functional “lx elements of the microoperations former 18 (Fig. 7) is as follows.

Register 115 is intended for storing addressable and operational parts of micro-instructions.

The common -th decryptors 116 are intended to form the operating part of the microinstructions according to the code;

The first decoder 117 is intended to form the code of the numbers of the failed microinstructions in the last step of executing the diagnostics firmware.

The trigger 120, the first and second single vibrators 122 and 121, respectively, are designed to control the decoder 117 to generate a control signal at the output 127 of the microoperation generator 18. Element AND 119 is intended to form the trigger setting signal 120 to the zero state,

Shaper micro-operations 18 works as follows.

When the last microcommand of the diagnostic mode is executed, a single signal from the address field address of the microcommand on the other microcommands stored 1xx Q memory module of microcommands 17 in this field is recorded zero from the register 115 arrives at the output 123 of the microoperation driver 18, sets the trigger 120 to 1 and opens element and 1-19. The signal from the single output of the trigger 120 triggers the one-shot 121, the output of which opens the first decoder 117. The code of the numbers of the failed microcommands from the register 115 output through the decoder 117 is fed to the output 125 of the microoperation driver 18. After sampling and masking the initial address of the equivalent microcode command sequence to the input 118 from the output of the main memory block 6, a control signal is received. In this case the trigger 120 is zeroed out and the output signal of the one-shot 129 through the output 127 sets to one state Trigger trigger 28. The processor operates in the following way. When the program is executed, the instructions are read from block 6 of the main memory into data register 7. The operation code from the output of the register 7 data enters the input of the driver 15 addresses of microinstructions. According to the address developed in this node, the first micax is read from the microcommand memory block 17; :), the command. When executing the firmware of the processing of operands (the microoperation shaper 18 produces control actions, according to which the operands are written simultaneously to the first 2 and second 3 blocks of the local memory. If there are no faults in the processor, then at each given moment of time the first. 2 and second 3 local memory blocks store the same information. I During processing, operands come from the first 2 and second 3 local memory blocks to the first H and second 5 operational blocks in parallel and independently, and for these blocks, the basic by the micro-operation unit 18, the execution of identical operations is performed. The result of processing, depending on the command being executed, writes the first or second block of local memory into the first 2 and second 3 blocks of local memory or to block 6 of the main memory via switch 11. and the second 5 operational units perform parallel processing of data. Depending on the signal from the output of the micro oper generator 18 through the switch 11, the information is allowed to pass either from the first k or from the second 5 operational s units in the unit 6 main memory. Scheme 10 compares the results of processing data in the operating units; if the results coincide, the calculations are continued. If the first k or the second 5 operating units or the first 2 or second 3 local memory blocks fail or fail, the comparison circuit 10 will detect them due to a discrepancy in the processing results and generate an output signal that translates the microprogram The processor is in failing mode. In this case, the address of the microcommand of information processing in the control point is formed in the driver of the address of micro-commands 15. The microcommand address, during the execution of which a failure was detected, is stored in the first driver of the microcommand address 15 and, from its output to the input of the I 12 block cells, a signal of the information recording tamping unit is sent to the main memory unit 6. Information is re-processed, starting at the nearest checkpoint, information about which is stored in the first 2 and second 3 blocks of the local memory. If during and after the execution of microcommands following the microcommand for processing information at the control point, before the microcommand that failed, and also the microcommand, the signal from the output of the comparison circuit 10 is not received, the blocking signal of the 12 element block is removed and the micro - the program is executed further. Otherwise, when a fault occurs, it will again return to the execution of the information processing microcommand at the control point. If after a certain number of repetitions the failure does not disappear, then the signal of noncomparison from the output of the comparison circuit 10 generates the address of the first microcommand of the firmware of diagnostics of the failed microcommands. The determination of the numbers of failed microinstructions is carried out by a diagnostic test, to which the firmware of diagnostics of the failed microcommands passes control. The diagnostic test is performed by transferring the test information to the first 2 and second 3 local memory blocks, to the first k and second 5 operational blocks. The error signal from the output of the comparison circuits 10 modifies the addresses of micro commands of the microprogram for diagnosing failed microcommands. At the final cycle of the microprogram diagnostics, the microoperation driver 18 outputs to the fourth input of block 6 of the main memory the code of the number of the failed microcommand. The address of the initial microcommand according to the signals of the microoperations from the output of the former 18 is read into the buffer memory unit 13, where it masks with an equivalent substitution sequence of microcommands. The process of masking equivalent replacement sequences of microcommands stored in block 13 of the buffer memory consists in masking the first microcommands of the sequences with the corresponding microdata (Fig. 8). So, if there was a failure of a micro-command that corresponds to an equivalent replacement sequence, then a single label is written in the first field of the initial micro-command of the sequence. This label is subsequently a logical condition for the transition to the execution of a sequence of microcommands E instead of the execution of a failed microcommand A. At the end of the formation of the sequences, the signal from the output of block 6 of the main memory, affecting the microoperation driver 18, allows the execution of the command processing microprogram information at the control point, the address of which is stored in the microcommand address driver 15. According to the operational part of the current microcommand supplied from the output of the microoperations generator 18 through the open trigger 28, block 19 of the elements AND, the driver of the address 20 through the block of 23 elements AND records the address of the first microcommand of the equivalent substitute sequence of micro instructions in the account 25 for the address of the first microcommand. At the same time, through the OR 29 element, a single vibrator 30 is given, whose output signal through the OR element 31 is fed to the control inputs of the switches 1 and prohibits the passage of micro-operations signals from the output of the microoperations 18 micro-operations. At the address recorded in the address counter 25, the first microcommand of the equivalent replacement microcode sequence is read and the microcommand is analyzed. If, when the first microcommand of the equivalent replacement sequence is read, zero is written in the first field, then the trigger 1 does not change its state, The address counter 25 with a signal from the output of the buffer memory block 13 through the third element OR 2 is zeroed out after the end of the signal at the output of the micro-operation single-oscillator from the output of the microoperational driver 18 through switches 1 and 9 enters into blocks 2 and 3 of the local memory and operational blocks and 5. The signal from the output of the address counter 25 through the element OR-HE 26 opens the block of elements AND 1b and the next microinstruction Her is read from the block 17 of the micro-instructions memory the execution is performed according to the described algorithm. If the next microinstruction fails, the following algorithm is implemented. The microcommand from the output of the microoperation generator 18 through an open signal from trigger 28, the block 19 of elements AND goes to the driver 20 of the address of microinstructions and through the element OR 29 starts one vibrator 30, which through the element OR 31 supplies a signal to the control inputs of switches 1 and 9, and the code micro-operations from the output of the imaging unit of the micro-operations 18 does not pass through them. The address of the first micro-command of an equivalent replacing sequence of micro-commands, formed by the shaper 20 of the micro-command address, through an AND 23 block of elements opened by a signal from the zero output of the AND trigger, enters the address counter 25. At this address, the address counter 25 reads from the block 13 of the buffer memory. The first micro-instruction of the equivalent replacing sequence of micro-instructions, o. (Fig. 8, a single signal, the first field of a microcommand sets trigger I to a single state. The signal from the single output of the lA trigger through the OR element 31 enters switches 1 and 9 and the micro-operations code from the output of the buffer memory block 13 enters the local memory blocks 2 and 3 and the operating blocks k and 5. The signal from Tpetbero the microcommand field from the buffer memory block 13 goes to the counting input of the address counter 25 and increases its contents by one, thus forming the address of the next microcommand equivalent will follow Since the address counter 25 is not in the zero state, the signal at the output of the element OR NOT 26 is absent, while it is prohibited to read the following microcommands from block 1.7 of the memory microcommand “Next address counter 25 at the new address reads the next micro instruction, input equivalent substitution sequence of microinstructions, from the buffer memory unit 13 "Performing its implementation is similar to executing the first microcommand. When reading from the buffer storage unit 13 of the last micro-command of the equivalent replacing sequence, there is no signal at the output of the buffer storage block 13 from the third field of the micro-command (c), “8). In this case, the one-shot 27 is energized and through the OR element 2k zeroes the trigger and the address counter 25. At the output of the OR-NOT 2b element, a signal appears that permits the passage of the address of the next micro-coder (Yormir 5teltel of the microcomm address through the block of 16 elements AND, At this address, from the micro-memory block 17 the next micro-command is read and executed according to the algorithm described above. If the execution of a microcommand included in the equivalent substitution sequence of microcommands fails in data processing, the signal from the output of the comparison circuit 10 through the OR element 2k will reset the address counter 25 and the It trigger and the processor will go to the fail processing mode, which is described above. If a failure has occurred, the diagnostic firmware is started, the numbers of the failed microcommands are determined, equivalent replacement sequences of microcoids are formed for them and the program is executed further. information processing in the presence of two or more failures in different channels, even under failure conditions, parity monitoring of the processed information is carried out. Consequently, this firmware processor surpasses the prototype in fault tolerance and proper functioning. Using a processor will allow you to build computational and control systems designed for long-term use in the absence of maintenance, according to the invention formula. A microprogrammed processor containing a main memory block, an address register, a data register, a buffer memory block, and the first and second local memory blocks. , the first and second operational blocks, the first switch, the first block of And elements, the comparison circuit, the first driver of the micro-command address trigger control, the micro-command memory block and A micro-operation organizer, the first information output of the main memory block is connected to the data register input, the first output of which is connected to the first inputs of the first and second local memory blocks, the second output of the data register is connected to the input of the operation code of the first micro-command generator, the control output of which is connected with inverse inputs of the first block of elements And, the third output of the data register is connected to the input of the address register, the output of which is connected to the first address input of the main memory block, second the information output of the main memory block is connected to the first information input of the buffer memory block and the first input of the microoperations shaper, the output of the microoperations of which is connected to the control input of the main memory block and the control input of the buffer memory block, the output of the first switch is connected to the input of the first block elements And, the output of which is connected to the information input of the main memory block, the output of the microinstruction memory block is connected to the second input of the microoperations shaper, whose output output is inn with the address 299 input of the first driver of the microinstructions address, the output of the first operational unit is connected to the first information input of the first switch and the first input of the comparison circuit, the output of which is connected to the control input of the microinstructor of the address generator, the output of the second operational unit is connected to the second input of the comparison circuit and the second informational the input of the first switch, the direct and inverse control inputs of which are connected to the first control output of the microoperation driver, the second output of the first The operating unit is connected to the second input of the first local memory block, the output of which is connected to the first information input of the first operational block, the second output of the second operational block is connected to the second input of the second local memory block, the output of which is connected to the first information input of the second operational block, the synchronization input of the microinstructor address driver is connected to the clock input of the device, which is characterized by the fact that, in order to increase the fault tolerance and reliability the firmware processor, the second and third switches, the second, third and fourth blocks of AND elements, the mode trigger, the second shaper of microinstructions, the address counter, the first, second and third elements of OR, the first and second one-mode, the element of OR- NOT, the information output of the buffer memory block is connected to the first information inputs of the second and third switches, the output of which is connected to the second inputs of the first and second operating blocks, the output of microoperations by the formers The operations connected to the second information inputs of the third and second switches, the output of which is connected to the third inputs of the first and second local memory blocks, the output of the first OR element are connected to the input of the first one-oscillator, the output of which is connected to the first input of the second OR element, the single output of the control trigger is connected with the second input of the second element OR, the output of which is connected to direct and inverse up. the second and third 9530 switches, the second control output of the microoperation driver is connected to a single mode trigger input, the single output of which is connected to the first input of the second block of I elements, the output of microoperations of the microoperation driver, is connected to the second input of the second block of I elements, the output of which is connected with the inputs of the first OR element and the inputs of the second shaper of the microinstructor address, the output of the second shaper of the microcommand address is connected to the first input of the third block in And, the output of which is connected to the information inputs of the address reader, the first control output of the buffer memory block is connected to the single input of the control trigger, the zero output of which is connected to the second input of the third block of And elements, the second control output of the buffer memory block is connected to the first the input of the third OR element, the output of which is connected to the installation input of the address estimator and the zero input of the control trigger, the third control output of the buffer memory block tm is connected to the input of the second single rectifier AND stroke address counter. the outputs of which are connected to the second information input of the buffer memory block and the inputs of the OR-NOT element, the output output of the first, the microinstructor address generator, and the output of the OR-NOT element are connected respectively to the first and second inputs of the fourth block of AND elements, the output of which is connected to the input of the memory block these microinstructions, the output of the code of the failed microinstructions of the microoperations driver is connected to the second address input of the main memory unit, the output of the comparison circuit and the output of the second one-vibrator are connected respectively to the second and third inputs of third OR gate, the installation input device connected to the trigger input of a zero mode. Sources of information taken into account in the examination 1. The author's certificate of the USSR fp, cl. G 06 F 15 / PO, 1977. 2. Automatic return methods in the COPRA computer. Ex3198009532

press information Ser. calculator - U. Patent of Great Britain G 141j095, on equipment, K 20, 1978 fi C L, pub. 1978

3. US patent P, 763902, cl. G About F 15/00, 1980

cl. 235-153 LE, published. 1978. 5 (prototype) "

5. USSR author's certificate

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Claims (1)

Claim A microprogram processor containing a main memory block, an address register, a data register, a buffer memory block, the first and second local memory blocks, the first and second operational blocks, the first switch, the first block of AND elements, a comparison circuit, the first Micro command address generator, a control trigger, microcommand memory block and Microoperator, and the first information output of the main memory block is connected to the input of the data register, the first output of which is connected to the first inputs of the first and second blocks of the locale memory, the second output of the data register is connected to the input of the operation code of the first micro-command generator, the control output of which is connected to the inverse inputs of the first block of elements AND, the third output of the data register is connected to the input of the address register, the output of which is connected to the first address input of the main memory block, the second the information output of the main memory block is connected to the first information input of the buffer memory block and the first input of the microoperator, the microoperation of which is connected to the control the main memory block and the control input of the buffer memory block, the output of the first switch is connected to the input of the first block of AND elements, the output of which is connected to the information input of the main memory block, the output of the micro-command memory block is connected to the second input of the microoperator, addressed further. whose output is connected to the address 29 900095 30 by the input of the first driver of the address of the th switch, the second control micro-command, the output of the first operational unit is connected to the first information input of the first switch and the first input of the comparison circuit, the output of which is connected to the control input of the driver of the address of the micro-commands, the output of the second operation unit is connected to the second input of the circuit and comparing the second data ^{input, 0} of the first switch, the forward and inverse control inputs of which are connected with the first control output of the mikroop radios, the second output of the first operation unit ¹⁵ co unified with a second input of said first local memory unit, whose output is connected to a first data input of the first operation unit, the second output of the second operational Bloch ka 20 connected to the second input of the second local memory unit, whose output is connected a first data input of the second operational unit, the synchronization generator input ^{25 of} microinstruction addresses is coupled to the clock input of the device characterized by the fact that, in order to increase fault-tolerant STI and reliability of operation of the micro processor program ^30, it entered the second and third switches, second, third and fourth blocks and elements, trigger mode, a second address generator microinstructions counters E5 snip address, the first, second and third elements or the first and second monostable multivibrator, an OR-HE, wherein the data output buffer memory unit is connected with the first informatsionny- ⁴⁰ mi inputs of the second and third switches, whose output is connected to second inputs of the first and second operating units, micro yield operations of the microoperation generator * 5 is connected to the second information inputs of the third and second switches, the output of which is connected to the third inputs of the first and second blocks of local memory, the output of the first electronic element is connected to the input of the first one-shot, the output of which is connected to the first input of the second OR element, a single output of the control trigger is connected to the second input 55 of the second OR element, the output of which. connected with direct and inverse yn-. equal inputs of the second and third. the output of the microoperation generator is connected to a single input of the mode trigger, the single output of which is connected to the first input of the second block of AND elements, the microoperation output of the microoperation generator is connected to the second input of the second block of elements 11, the output of which is connected to the inputs of the first OR element and the inputs of the second micro-address generator, the output of the second micro-command address generator is connected to the first input of the third block of AND elements, the output of which is connected to the information inputs of the address counter, the first the control output of the buffer memory unit is connected to a single input of the Grigger control, the zero output of which is connected to the second input of the third block of AND elements, the second control output of the buffer memory unit is connected to the first input of the third OR element, the output of which is connected to the installation input of the address counter and the trigger zero input control, the third control output of the buffer memory unit is connected to the input of the second one-shot and the counting input of the address counter, the outputs of which are connected to the second information input ohm of the buffer memory block and the inputs of the OR-HE element, the address output of the first micro-address generator and the output of the OR-HE element are connected respectively to the first and second inputs of the fourth block of AND elements, the output of which is connected to the input of the micro-memory block, the code output of the faulty micro-commands of the former microoperation is connected to the second address input of the main memory block, the output of the comparison circuit and the output of the second one-shot are connected respectively to the second and third inputs of the third OR element, the installation input is troystva connected to the trigger input of a zero mode. .