SU1524063A1 - Multiprocessor system - Google Patents

Abstract

The invention relates to computing and can be used to build reliable multiprocessor systems. A multiprocessor system increases system reliability, since it is possible to rebuild the system in such a way that the failed processor units are replaced with serviceable ones, and after system initialization, it works in the previous mode. A multiprocessor system contains processor devices 1.1, ....., 1.N, system memory 5, I / O devices 6.1, ..., 6.M. The composition of each processor unit includes a processor shutdown trigger 7.I, driver 8.I, element AND 9.I, control trigger 10.I, element OR 11.I, computing unit 12.I. During the operation of the system, the control processor device initializes the system and starts the slave processor devices. In addition, the controlling processor unit (by interruption from its timer) can pass to the subroutine of testing the performance of the slave processor units, analyzing in turn the words of the state of each of them. 14 il.

Description

processor device Kl goes to jc program, which may include

to the subroutine of the health check and launch of the slave processor devices 1,2 ,,,,, 1, p. At the same time, the status words of each processor device 1.2 are read alternately,, о,, 1, п. If in the state word of the next processor device 1.1 (FIG. 10) the unit (i 1) is written to the de Goto bit, and zero (Start i 0) is written to the Start bit, the control unit 4.1 goes to analyzing the status word of the following processor device 1.1 + 1, If there is no signal Goat, -OR there is a unit in the Start deselection, then the slave device is considered failed and is disabled by the command Disconnect the slave processor device. After that, the control processor device

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after the completion of its program, it sets the Goat bit to one in the register 26oi (,

If all processor devices 1,2 ,,, о, are working correctly in the system, then the time diagram of signal exchange between the control device 1.1 and each slave processor device corresponds to FIG. 12,

In the diagram, the signals generated in the control device 1.1 are marked with one stroke, and in the slave - with two lines.

The time period T corresponds to the execution time of the main program in the slave processor device 1.1, and T is the time from the start of the timer slave1, 1 stops the timer 27o1 and the shifting processor device until the next Start command from the controlling processor device 1, 1 ,, T is the estimated time of the timer of the slave processor device 1, This timer should go to the system initialization program. With s-toM, tasks are redistributed for the remaining processor settings. data, loading data and programs into these processor units, ordering the numbers and the number of remaining processor units. Then they are started and the timer of the controlling processor device 1.1 is started, after which the latter switches to the execution of its main program.

If, when executing a subroutine for interrupting the timer of the control device 1, there are no failed processors, then the slave processor units start and return from the subroutine,

Each slave device 1,2, о .., 1оП works in accordance with the algorithm presented in fig.

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handle an interrupt request after a period of time greater than

mr

. Consider the operation of a system when a slave processor device 1.1 fails. A slave processor device failure can occur after it has set the Go signal, or after it has cleared this signal (the corresponding bits of the 26l status register are analyzed).

In the first case, the shutdown of the failed processor unit 1.1 is carried out in accordance with the diagram shown in FIG. 13, in the second case shown in FIG. 14o.

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after the completion of its program, it sets the Goat bit to one in the register 26oi (,

If all processor devices 1,2 ,,, о, are working correctly in the system, then the time diagram of signal exchange between the control device 1.1 and each slave processor device corresponds to FIG. 12,

In the diagram, the signals generated in the control device 1.1 are marked with one stroke, and in the slave - with two lines.

The time period T corresponds to the execution time of the main program in the slave processor device 1.1, and T is the time interval from the moment the timer starts up to slave5

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handle an interrupt request after a period of time greater than

mr

. Consider the operation of a system when a slave processor device 1.1 fails. A slave processor device failure can occur after it has set the Go signal, or after it has cleared this signal (the corresponding bits of the 26l status register are analyzed).

In the first case, the disabling of the failed processor device 1.1 is performed in accordance with the diagram shown in FIG. 13, in the second case shown in FIG. 14o. In obrich cases, the slave goes out of order after the completion of nporpasjMbi in the first cycle

Apparently from diagrams, command. Disable the slave processor device is generated at the beginning of the third cycle, because in the first case the Start signal is not removed, and in the second case the Goat signal is not set, in the 26oi state register (algorithm of the control processor, Fig.10). In the first case (FIG. 13) the timer 27 "i of the failed slave processor unit li through the time interval Tj may expose a request to interrupt the operation of the failed device 1.1, This request does not affect the operation of the entire system, since the failed processor stroystvo l.i off in the next system clock cycle by the control processing unit 1z1,

Thus, the shutdown of a failed slave processor unit lai is accomplished in software by analyzing the word of the state of this processor at the beginning of each system cycle. In the disconnected processor device, a single potential is output at the output of the trigger 7.1 to turn off the processor, which opens one by one input from element 9.1, by outputting 20.1 (by setting the unit to the 3rd digit of register 26.1), thereby providing a signal from input 13.1 to output 18-1 from the seeming processor device 1

In addition, the signal from the output of trigger 7.1 disconnects the computing unit 12.1 from the system information exchange channel 2, entering input 17.1 of this block, and provides a single signal to one of the inputs of element 11 Yes. For this, the failed slave processor unit lai does not affect the state of the signal on the bus 4 is turned off by the control processor.

Failure and replacement of the failed control processor device 1.1 is carried out in the system by software and hardware as follows.

In the initial state, the function of the control processor device is executed by the processor device 1.1, at the input 13-1 of which is present

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logical 1 (fig, 1,2). When the system is turned on, the initial installation of registers 26.1, oe ,, 26, n states is performed. In a schematic way, all bits of these registers, except the fourth, are set to the zero state, and the fourth bit - to the single state. In addition, the outputs

The Q triggers for turning off processors 7.1, ..a, 7.p are set to zero potential (conditional circuits of the initial state are not shown conventionally in Figures 1 and 2).

Then, the 5th bit of the state register register 26.1 of FIG. 6) of the processor device 1.1 is set to one state by a signal at the input 13.4 of the processor device 1.1, which through the input 14il of the computing unit 12-1 goes to the corresponding register bit 26.1 states (for example, to the input of a D-flip-flop, clocking the 1Tc of which is connected to the clock generator). In the remaining processor devices 1о2, ooo, 1.n, at the inputs 13.2, o .., 13.n, there are zero potentials, since all elements 9.1, ..., 9.n are closed, due to which 5th bit the state registers of these devices remain at zero. Only in the processor device 1.1, the trigger lOol is set to one, since, at a single potential from the 2K1 output of the computing unit 12.1, to the clock input of the trigger 10.1, the latter passes a single signal from its information input to the output (for example, as the trigger 10.1, .,., 10.P can be used D-triggers, controlled by the level of the clock signal, which, at a single potential, pass information from the input D

c to the output, and when going to the zero level, the information that is available at the input just before this is latched into the triggers).

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The signal from the trigger output 10.1 is fed to the input 19.1 of the computing unit 12.1 and configures the switch 23.I so that it connects the system information exchange channel 2 to the local information exchange channel 28.1, i.e. The processor unit 1.1 accepts the configuration of the control processor unit (Fig. 7).

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In addition, at the input I6gl of the controlling processor device 1.1 a zero potential is maintained, since the outputs of elements 11.2., ..O, 11dP of all processor devices It2, ..., ln have zero potentials, therefore, to the clock input of trigger 7.1 through the driver 8.1 enters zero potential.

The processor shutdown trigger 7o1 remains as it is, i.e. the output remains zero potential.

Thus, in the course of operation in the control processor device 1.1, the trigger 10.1 is in a single state, and the triggers 10'2, ..., 10.p processor devices 1.2, ..o, 1.n are in the zero state. Therefore , computing blocks 12.2 ..., 12.p have the configuration shown in Fig.8 or Fig9. Toto perform the functions of subordinate processor units.

If control processor device 1.1 goes out of order, it is replaced by a healthy processor.

The processor unit 1.2 accepts the functions of the control processor unit by setting the 4th digit of this register 26.2 to one (as follows from the appliance device, which is first to the right (FIG. 1 and 2) from the control, FIG. 11) . In the rest of the processing processor device 1.1 weed devices 1.3, „.., 1„ n 5th (not counting the disconnected processor bits (OLA) of registers 26 о 3, о о ,,

26.parties remain in zero. These processor units alternately analyze the 5th and 1st bits (UPV and Start) of their registers 26.3 ,, .., 26.11 and after setting the first bit to one, i.e. The arrivals of the Start-up signal from the new control processor device 1,2 perform the functions of the slave processor devices, pre-setting

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devices), If there are no disconnected processor devices, the functions of the control processor device begin to execute processor device 1.2. This is done as follows. The slave processor devices 1.2 ,,, о, 1оП (fig, II) at the beginning of each system clock Q expect a Start signal from the processor device 1.1. At the same time (Figo15)

if the Start signal from the Controller into unit state 4th bits of device 1.1 does not arrive, for example, (LUP) of its registers 26.3, o, at the beginning of the 3rd cycle, subordinate to j 26, n states

the session device 1 proceeds to the interrupt program from its timer 27.1.

Interrupt from timer 27.1 produces a signal about the malfunction of the controlling processor unit at the output of the computing unit + 12.1 (i.e., 4th register bit 26.2 is reset to the zero state). This signal is sent to the triggering inputs of the trigger 10.1 (the trigger lOoi remains in the zero state), as well as to the inverse input of the element ll, ij.

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While in devices I, 3 ,,, o, 1, n, the Start and UPV bits are alternately tested, the control processor initializes the systems (Fig, II) taking into account the failure of the control processor unit 1.1.

If, in the process of further operation of the system, the control processor device 1.2 fails, then it is replaced by the next right-hand (not disabled) processor device. And so on In the system, any processor

ten

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5th bit (UPV) state register 26.1.

Thus, after all slave processor units 1о2, ..., 1.p are set at one of the inputs of element ll.i, the unit potentials are set, the unit potential on line 4 of the control processor unit

Va, which indicates a malfunction of the controlling processor device 1.1 o On input 16.1 of this processor device 1.1, a single signal is sent to the clock input of trigger 7.1 via the driver 8.1. As a result, at the output of trigger 7.1 of the processor shutdown, a single potential is set

At the same time, the processor device 1.1 is turned off and a single potential is set at the input 13.2 of the next device 1.2, which sets the 5th bit (FIGS. 4 and 6) to the unit

The processor unit 1.2 accepts the functions of the control processor unit by setting the 4th digit of this register 26.2 to one (as follows from the algorithm, Fig. 11). In the rest of the processor units 1.3, „.., 1„ n the 5th bits (OLB) of the registers 26 о 3, о о ,,

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While in devices I, 3 ,,, o, 1, n, the Start and UPV bits are alternately tested, the control processor initializes the systems (Fig, II) taking into account the failure of the control processor unit 1.1.

If, in the process of further operation of the system, the control processor device 1.2 fails, then it is replaced by the next right-hand (not disabled) processor device. And so on In the system, any processor

131524063

The characteristics of both the manager and the repaired | does not lead to the release of the entire system, since in the case of a case it is possible to replace the failed processor. If the system has redundant processor devices, the failed processor units can be replaced by redundant,

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In the meantime, pr pi ci ma ni blu p h ora n c i n c y o d i n i l i n i s c i r i p i n r c i m ro ro ti so +

which does not cause a decrease in system performance. In the case when the backup devices are not available, after the next failure, the tasks are redistributed between the remaining processor devices. At the same time, the system continues to perform its functions, although with a lower performance.

Claims (1)

Invention Formula A multiprocessor system containing n processor devices, a system memory and a group of input / output devices, interface inputs / outputs of each processor device are connected via system communication channel to the system memory inputs and input / output devices of the group, each processor device containing a computational The information input-output block of which is an interface input-output of the processor unit, characterized in that, in order to increase the reliability of the system by the possibility of replacing refused as up14 0 five 0 five 0 five equal and slave processor devices operable, it contains in each processor device a shutdown trigger, pulse shaper, control trigger, AND element and OR element, and the control trigger output is connected to the control input of the computing unit and the disconnect trigger information input, the output of which connected to the lock input of the computing unit and the first inputs of the elements AND N OR, the output of the slave processor of the computing unit is connected to the the disconnection trigger input, the synchronization input of which is connected via the pulse shaper to the processor input disable input, the input mode of each processor device is connected to the second inputs of the AND and OR elements and the control trigger information input and the computing unit selection input, the fault output of the computing unit is connected the synchronization input of the flip-flop trigger and the third inverse input of the OR element, the output of which is the output of the processor unit, the inputs off and audio processing unit outputs failure of all processing units form a pin of disconnecting a multiprocessor system, an output of i-ro AND processor unit connected to the input mode (1 + 1) -th processing unit of the repaired processor. Malfunction of the control processor. Selection of the control processor. Access to the local memory. Record Record Read Reading OLP Record L. 6 U dd 28.i one Fie.2 2B. i i / V I razr I I FIG. sh R  Wt - ( iAOKjf M. Il nanoAu ill To Su / ty ISt Us paV A ,, um t, 9ut Z6.t II Fut.5 sh Htutmtrwony MMM I /and: h-) ( hl  one FIG. 6 F / h IJ: L X h / h N 25J. 28. L / h / 26.L one sh Mi gi X years (. I / g 7 I iti 2U 1 m oLloka 13