SU978380A1 - Averaging device with interlocking - Google Patents

Description

(54) INTERLOCKING DEVICE WITH LOCK

one

The invention relates to radio engineering.

A blocking averaging device is known, containing a phase discriminator, the first output of which is connected to the first input of the first reversible counter and to the first input of the first element I, the second input of which is connected to the output of the first trigger, the inputs of which are connected to the first outputs of the first switch and the first reversible counter , the second output of which is connected to the first input of the second; a trigger whose output is connected to the first input of the second element I, the second input of which is connected to the second output of the phase discriminator and to the second input of the first reversing counter, the corresponding outputs of which are connected to one input of the first switch, and the second switch, the first counter and the first connected in series delay element in the second counter C11

However, in the known device accuracy is insufficient.

The purpose of the invention is to increase precisely. when exposed to interference ..

To achieve this goal: to the average second device with a lock containing the phase discriminator, the first output is connected to the first one

10 to the input of the first reversible counter in the first input of the first element I, the second input of which is coy with the output of the first thrgger, to the input (of which the first outputs of the first mutator are connected, and the first reversible switch, the second output of which is connected to the second trigger whose output is connected to the first input.; the second element I, the second input: which is connected to the second output of the phase discriminator and to the second input of the first reversible counter, the corresponding outputs of which are connected to the same inputs The first switch, as well as the second switch, the first counter and the first delay element {ki} and the second counter in series, introduced a second reversible counter, and the second delay element and the third reversible counter connected in series, the outputs of which are connected to the other switches of the first switchboard. pa whose corresponding input is connected to the input of the second delay element and to the output of the second counter, the second input of which is connected to the first input of the phase discriminator, the second input of which is connected to the input the first counter. The output of which is connected to the inputs of the first delay element and the second switch, one input of which is connected to the j outputs of the second reversible counter, to the inputs of which the outputs of the first and second element I are connected, while the second output of the first switch is connected to the second input of the second trigger, the first and second outputs The phase discriminator is connected to the corresponding inputs of the third reversible counter, and the corresponding output of the second counter is connected to the other inputs of the second switch. The drawing shows a structural electrical circuit of the device proposed, Averaged device with blocks. Coy contains triggers 1 and 2, elements IZ and 4, elements 5 and 6 delays, counters 7 and 8, switches 9 and 10, reversible counters 11-13, phase discriminator 14. The device operates as follows: the device generates a sequence of generated clock pulses, the following with a frequency close to the speed of wiring of the received elements of the message, and at the other entrance - the fronts of the received elements of the message. The output signals of the proposed device are designed to correct the frequency and phase generated by the device clock synchronization of clock pulses. The phase discriminator 14 analyzes the mutual location of the clock pulses and the edges of the received message elements and generates additions correction pulses (formed one at a time on the front of the message element at the first output of the phase discriminator if the phase of the clock pulses lags behind the phase of the received message elements) or subtraction ( one on each front of the received message elements at the second output of the -phase discriminator if the phase of the clock pulses is ahead of the phase of the received x message elements). Due to the fact that the elements of: x messages are subjected to distortions in the communication channel, the outputs of the phase discriminator 14 form both true and false correction pulses (both addition and subtraction). A reversible counter 11, whose capacity, based on the speed requirements, is chosen to be very small, performs the first step of averaging the input correction signals. If the number of addition (subtraction) pulses received at its first (second) input exceeds by the value C (where is the conversion factor of the reversible counter 11) the number of subtraction (addition) pulses received at its second (first) input, then at the first ( the second) the output of the reversible counter 11, which is the output of the last bit of addition (subtraction), i.e. after the maximum averaging, a pulse is formed that sets the trigger 1 (2) to one state, as a result of which the subsequent pulses of addition (subtraction) pass to the output of the And 3 (4) element without averaging. This ensures a high response rate of averaging corrective pulses. The flip-flop 1 (2) is reset to zero state through the switch 9 of signals from one of the intermediate bits of the subtraction (addition) of the reversible counter 11 by a signal from one of its third outputs, i.e. partially averaged signal of the opposite corrective action. For both liver accuracy and speed of averaging the output correction pulses of a device, the coefficient of partial averaging of the reset pulses of blocking triggers is chosen automatically varying depending on the mode of operation of the device (stable clock synchronization mode, transmitter and receiver frequency tolerance mode, full coincidence mode of these frequencies, etc.), which is characterized in the first approximation by the ratio of the number of corrective pulses added Formation and subtraction, formed at the outputs of the phase discriminator 14 for a certain period of time. This period should be long enough (to judge the interference of the device’s operation mode, the analysis should be subjected to a minimum number of corrective pulses than The capacitance of the reversing counter is 11. The analysis of the operating mode of the device is carried out in the reversible counter 12 over a period of time determined by the period of the signals following the second output of the counter 7. At the same time The second pulse generated at the second output of the counter 7 rewrites the readings (the number code present at the moment in time) of the reversible counter 12 to the switch 9, and after a delay in the delay element 6 translates the reversible counter 12 º zero, t. e. prepares it for a new process of analyzing the operation mode of the device. The closer the reading of the reversing counter 12 is to zero, the more verbally that the correction pulses generated at the outputs of the phase discriminator 14 are due to interference in the communication channel. Therefore, the switch 9 in this case establishes a small coefficient of averaging the reset pulses of the blocking triggers, i.e. commutes the second inputs of the 1 n 2 flip-flops with the outputs of one of the first bits of the addition and subtraction (or even the inputs of the first bits) of the reversing counter 11. What is more: how does the reversal counter 12 differ from zero, the more likely that corrective the pulses of the predominant sign (e.g., additions) are true and the higher the coefficient of partial averaging of the opposite-sign correction pulses set by the switch 9, i.e. reset pulses of blocking triggers (in this case, subtract pulses). To increase the dynamic accuracy, by measuring with a reversible counter 12, the correlation impulses JCOB of different signs in time, thereby increasing the accuracy and noise immunity of the averaging output; device pulses, the time intervals during which device operation modes are distributed are made dependent on the frequency of the edges of the received message elements on the phase discriminator 14 (it’s necessary to keep in mind that on each edge of the received message element the phase discriminator 14 can be formed one corrective il-shulsa). This dependence of the frequency of influence on the analysis time of the operating mode of the device is realized by means of a counter 7, the clock input of which receives the edges of the received elements of the message, as a result of which c 7 is charged, and at its second output (output of the intermediate bit) the pulses are periodically generated resetting the reversible counter 12 and entering its readings into the switch 9. The frequency of these pulses is determined by the frequency of the edges of the received message elements. The reversing counter 13 provides a second step of averaging corrective pulses, while the frequency of the output corrective pulses is independent of the structure of the received message elements, which improves the accuracy and noise immunity of the averaging, and also creates more favorable conditions for high-precision correction of frequency and phase i generated by the clock device synchronization (which includes the proposed device) clock pulses. This is achieved as follows. The frequency of the clock pulses at the input of the counter 8 and its capacitance determine the period. the time during which the structure of the received elements of the message is analyzed. It is known that the adjustment of the frequency and phase of the clock pulses is made only by the transitions of the received elements of the message from one state to another (from one to the left and back). In addition, it is known that different types of messages have a different structure, i.e. characterized by different average frequency of alternation in the message of single and zero elements and their groups. At the same time, the average statistical structure of the message is preserved for rather large short days of time (from fragments of a codogram to hundreds and thousands of codograms). Accounting for this. the influence is realized by means of a switch 1O and a counter 7. The indication of a counter 7 at the moment of forming a pulse at the output of the counter 8,

characterizing the static structure of the received message elements are rewritten into switch 10, as a result of which the first and second outputs of switch 1O are connected respectively to the outputs of certain bits of addition and subtraction of the reversible counter 13, i.e. a well-defined coefficient of averaging corrective pulses formed at the outputs of elements 3 and 4 is established. The higher the readout of counter 7, the greater the coefficient of average D1: the output of correction pulses is established by the switch 1O, resulting in an almost complete independence of the output pulse frequency of the device from message receiving structures. The counter 7 is reset to the zero state by a signal from the output of the delay element 5, i.e. following the introduction of the readings of the counter 7 into the switch 10.

The proposed device provides, in comparison with the prototype, an increase in the accuracy and noise immunity of equilibrium.

Claims (1)

1. USSR author's certificate number 896785, cl. H 04 L 17 / OO, 198O (prototype).