SU978141A1 - Device for digital data logic processing - Google Patents

Description

The invention relates to computing and is intended for the processing of digital data.

A device for logical 5 digital data processing, made in the form of a multifunctional logic module containing AND elements, the outputs of which are connected to the inputs of the OR element, and the inputs are connected to the input buses directly and through inverters [1].

When constructing a device with internal memory for the logical processing of digital data (automatic machines) when using such a multifunctional logic module ^13, it is necessary to introduce memory elements into the device, due to the large redundancy of the equipment that implements the equipment, the device jn is complicated.

Discrete devices are known - automata with the so-called standard structure. They consist of a part of the device with memory elements and a combination part, in which the logical elements of the logic converter are concentrated. In each clock cycle of the discrete device, at the outputs of the logic converter, depending on the input signals and 50 signals at the outputs of the memory elements, signals are generated, some of which are the output signals of the discrete device in this clock cycle, the other part of the signals is transmitted to the inputs of the memory elements and will be used in the next clock cycle of the discrete device [2].

With binary coding of the internal states of an automaton, in the general case, the logical converter is significantly complicated, and with a single or anti-race coding of internal states, the logical converter is complicated and the number of memory elements increases. The device as a whole is difficult due to the large number of elements of the implementing equipment and the relationships between the elements.

The closest in technical essence to the proposed one is a device for the logical processing of digital data on programmable logic matrices (PIM) with a logical AND-OR structure. It contains triggers, AND elements (AND matrix), OR elements (OR matrix), the information input of each trigger is connected to the output of the corresponding element

OR, the inputs of which are connected to the outputs of the AND elements, the trigger synchronization input is connected to the time signal bus, which is the highest synchronization device [3].

The disadvantage of such a device lies in the large redundancy of the AND elements in the PLM, which are not used when implemented in a particular device, which complicates the device as a whole. , This is explained by the fact that the manufactured 10 PLM prior to its programming represents a rather universal structure oriented towards the simultaneous implementation of the largest possible number of zero Functions represented in disjunctive normal form. After programming the PLM for a specific application, its reconfiguration and reconfiguration of the entire device to perform other functions are difficult or impossible.

The purpose of the invention is to simplify and ensure the versatility of the device.

This goal is achieved by the fact that in the device for the logical processing of digital data containing AND, OR, triggers, and the information input of each trigger is connected to the output of the corresponding OR element, the inputs of which are connected to the outputs of the AND elements of the corresponding group, trigger synchronization inputs are connected to the synchronization bus devices, the first inputs of AND elements of each group are connected to the outputs of the triggers and input buses of the device, respectively, and the second inputs are connected to the device setup buses Twa.

o In FIG. 1 shows a diagram of the proposed device for logical processing of digital data; FIG. 2 is a timing diagram of the operation of the device in an example of settings for performing a code conversion function. 45

The device (Fig. 1) consists of AND elements 1, OR elements 2, triggers 3, input buses 4 of the device, tires 5-9 for setting the device, and bus 10 for synchronizing the device. The information input of each trigger 3 is connected to the output of the corresponding element OR 2, the inputs of which are connected to the outputs of the elements AND 1 of the corresponding group. The synchronization input of each of the triggers 3 is connected to the device synchronization bus 10. The first inputs of the elements And 1 of each group are connected respectively with the outputs of the triggers 3 and the input buses 4 of the device. The second input of each element And 80 is connected to its corresponding one separate bus: 5,6,7,8 or 9 device settings. The device synchronization bus 10 is designed to simultaneously transmit signals to triggers 3 via AND 1, OR 2 elements from direct, inverse, outputs of triggers 3 and input buses 4 of the device depending on the signals on buses 5-9 of the device settings.

As signals on buses 5-9, the device settings can be either Signals of a constant value (enable - units, inhibit - zeros), and signals of variable value (binary sequences). The signals on the input bus 4 of the device can be signals of constant or variable value, both independent (external but relative to this device), and dependent (from the outputs of triggers 3). Each next signal on the device synchronization bus 10 can be applied after the end of the transient in the device from the previous signal on this bus, i.e. the minimum cycle should be longer than the response time and the establishment of the signal in the sequential circuit of elements I 1, OR 2, trigger

3. Changing signals on buses 5–9 to play the device and changing independent signals on the input buses 4 of the device, leading to a change in the signal at the information inputs of triggers 3, must be carried out outside the time interval of the active signal on the bus 10 of the device synchronization, i.e. outside the current edge of the signal pulse on the synchronization bus 10 of the device for triggers 3 with dynamic synchronization inputs and outside the enable level of the signal on the bus 10 of the synchronization device for triggers 3 with potential synchronization inputs. The fulfillment of these conditions is necessary to ensure the uniqueness of the device.

The set of states of the triggers 3 forms the internal state of the device. Under the action of the next signal on the device synchronization bus 10, the device goes into the next internal state, while the output signals of the device are signals on one or more outputs of the triggers 3. The signals on the input buses 4 of the device and on the buses 5-9 of the device settings configure the device to perform specific functions of logical processing of digital data.

Let us consider in more detail the operation of the device by the example of its configuration to perform the function of synchronous code conversion of input binary Data into a known modified phase modulation code. To do this, it is necessary to send device signal 5 to the device settings bus 5, apply an input data signal to device device bus 8 (Fig. 26), to device settings buses 7 and 9 and apply a logically inverted input signal (Fig. 2c), all other device configuration buses send signals of logical 0, to the sync bus 10 of the device’s synchronization ³ send signals of doubled frequency, in comparison with the frequency of input data signals (figa). If we use triggers with 3 Е triggers with a dynamic 1θ synchronization course along the signal front and take for a logical 1 signal. 'positive Voltage, then at the direct outputs of the triggers 3 there will be signals shown in FIG. 2d, d, e (2d - 15 for trigger 3 of the first on the left, 2e - for trigger 3 of the last on the left).

At the beginning of each cycle of the device’s operation (the beginning of the cycle corresponds to the leading edge of the signal on the device synchronization bus 10 20, Fig. 2a; the state of the first trigger 3 on the left is reversed; the second trigger 3 on the left is set to a single state if in a single 25 state on the left, trigger 3 and on the device settings bus 7, the signal is one, otherwise the second on the left, trigger 3 is set to zero, the last hardly 3θ trigger 3 (its direct output is the device’s output in this example) anavlivaetsya in one state if the signal on the bus 9 ediyaichnomu setting device corresponds to the set condition at the second leftmost flip-flop 3, or signal bus -8 setting device corresponds to a single state at a single first left trigger 3, in other cases, the last _paragraph on the left trigger 3 is set to zero state. As shown in Fig. 2, the input data sequence 1010011 (corresponds to the doubled sampling frequency of the sequence 65 ^; 11 00 11 00 00 11 11) is converted to the desired sequence

01000100100101 with the specified device setting.

If it is necessary to perform logical processing of digital data in the device in accordance with another Function, it is enough to change the signals on the input buses 4 of the device and on the buses 5-9 of the device settings.

The connection of the first inputs of the elements And 1 of each group with the outputs of the triggers 3 and the input buses' 4 devices, respectively, and the second input. Dov elements And 1 - with tires 5-9 settings of the device simplifies the proposed device in the General case by significantly reducing the number of elements And 1 with a slight increase or preservation of the number of triggers 3. The presence of tires 5-9 settings of the device provides multifunctionality of the device.

Claims (3)

The invention relates to computing and is intended for processing digital data. A device for logical processing of digital data is known, made in the form of a multifunctional logical module containing AND elements, whose outputs are connected to the inputs of the OR element, and the inputs are connected to input buses directly and through inverters 1. When building a device with internal memory for logic processing digital data (automata) when using such a multifunctional logic module, it is necessary to insert memory elements into the device, due to the large redundancy of the implementing equipment Reality is complicated. Known discrete devices machines with the so-called standard structure. They consist of a part of a device with memory elements and a combination part in which the logic elements of a logic converter are concentrated. In each cycle of operation of a discrete device at the outputs of the logic converter, depending on the input signals and signals at the outputs of the memory elements, signals are generated, some of which are output signals of the discrete device during this operation cycle, another part of the signals is transmitted to the memory element inputs and used in the next cycle of operation of the discrete device 2. When binary coding of the internal states of the automaton, in general, the logic converter is much more complicated, and with unit protivogonochnom-border or internal encoding conditions is complicated logic converter and increases the number of memory elements. The device as a whole is distinguished by complexity due to the large number of elements of the implementing equipment and the connections between the elements. The closest in technical essence to the present invention is a device for logical processing of digital data on programmable logic arrays (PLA) with a logical structure of AND-OR. It contains triggers, AND elements (AND matrix), OR elements (OR matrix), the information input of each trigger is connected to the output of the corresponding OR element, whose inputs are connected to the outputs of the AND elements, the trigger synchronization inputs are connected to the time signal bus, which is device synchronization 3. The disadvantage of such a device lies in the large redundancy of the elements AND in the PLM, which are not used in the implementation of a particular device, which complicates the device as a whole. This is due to the fact that A PLA before programming is a fairly universal structure oriented towards the simultaneous implementation of the largest possible number of null Functions represented in a disjunctive normal form. After programming the PLA for a specific application, reconfiguring and reconfiguring the entire device. To perform other functions, it is difficult or impossible. The purpose of the invention is to simplify and provide multi-functionality of the device. This goal is achieved by the fact that in the device for logical processing of digital data containing the elements AND, OR, triggers, and the information input is given. the trigger is connected to the output of the corresponding OR element, whose inputs are connected to the outputs of the AND elements of the corresponding group, the trigger timing synchronization is connected to the device synchronization bus, the first inputs of the AND elements of each group are connected to the trigger outputs and input device buses, respectively, and the second the inputs are connected to the device configuration buses. o In FIG. Figure 1 shows a schematic diagram of a proposed device for logical processing of digital data, Figure 2 shows a time diagram of the operation of the device; in the example of setting, for performing the code conversion function. The device (Fig. 1) consists of elements AND 1, elements OR 2, triggers 3, input buses 4 devices, tires 5-9 device settings and bus 10 device synchronization. The information input of each trigger 3 is connected to the output of the corresponding element OR 2, whose inputs are connected to the outputs of the And 1 elements of the corresponding group. The synchronization input of each of the triggers 3 is connected to the device synchronization bus 10. The first inputs of the elements And 1 of each group are connected respectively with the outputs of the triggers 3 and the input buses 4 devices. The second input of each element And 1 is connected to the corresponding one separate bus: 5,6,7,8 or 9 device settings. The device sync bus 10 is designed to provide simultaneous transmission of signals to triggers 3 through AND 1, OR 2 elements from forward, inverse outputs of trigger 3 and device input buses 4, depending on the signals on device tuning buses 5-9. As signals on buses 5-9, device settings can be either Signals of a constant value (allowing - units, prohibiting - zeros), and signals of variable value (binary sequences). The signals on the input buses of the 4 devices can be either constant or variable signal signals, both independent (external to the device) and dependent (from the outputs of the flip-flops 3). Each follow-up signal on the device synchronization bus 10 can be supplied after the transient process in the device completes from the previous signal on this bus, i.e. the minimum clock cycle must be greater than the response time and the signal is established in a series circuit of AND 1, OR 2, trigger 3 elements. Signal change, on buses 5–9 of our device, and changing independent signals on input buses 4 of the device, leading to a change in signal the information inputs of the flip-flops 3, should be carried out outside the time interval of the active signal on the bus 10 synchronization device, i.e. outside the effective edge of the signal pulse on bus 10; syncronization of the device for triggers 3 with dynamic synchronization inputs; and out of the allowable signal level on bus 10; device synchronization for triggers 3 with potential synchronization inputs. These conditions are necessary to ensure uniqueness in the operation of the device. The set of states of the triggers 3 forms the internal state of the device. Under the action of the next signal on the device synchronization bus 10, the device enters the next internal state, and the output signals of the device are signals on one or several outputs of the trigger 3. The signals on the input buses -4 of the device and on the tires 5-9, the device settings configure the device to perform specific functions of logical processing of digital data. Let us consider in more detail the operation of the device using the example of setting it up to perform the function of synchronous code conversion of input binary data into the known code of modified phase modulation. To do this, on the device setting bus 5, send a logical 1 signal, send a device configuration bus 8, send an input data signal of FIG. 26), device settings 7 and 9 bus and send a logical inverted input data signal (fig.2b), to all other device tuning buses to send signals of logic O, to the device synchronization bus 10 to send signals of doubled frequency, compared with the frequency of input data signals (Fig. 2a). In case of triggers 3, apply triggers with a dynamic synchronization input on the signal front and take the logical 1 signal. positive voltage, then the direct outputs of the triggers 3 will be the signals shown in FIG. 2d, d, e (2d for trigger 3 of the first left, 2e for trigger 3 of the last left). At the beginning of each clock cycle of the device (the beginning of the clock cycle corresponds to the leading edge of the signal on the bus 10 of the device synchronization, Fig. 2a / the state of the first left trigger 3 is reversed; the second left trigger 3 is set to one if the first left trigger 3 and the unit signal on unit bus 7; otherwise, the second left trigger 3 is set to the zero state, the last target trigger 3 (its direct output is in this example the output of the device) is cast to the unit state if the signal on the device setting bus 9 corresponds to a unit one when the second left trigger 3 is single, or the signal on the device setup bus-8 corresponds to one when the state one of the left trigger 3 is one, in other cases the last trigger 3 is set to the zero state. As shown in Fig. 2, the input to the data sequence 101001 (corresponds to the sequence gating frequency twice; il 00 11 00 00 11 11) is converted, the desired sequence l 1000100100101 at the specified device configuration. If it is necessary to perform logical processing of digital data in accordance with another function, it is enough to change the signals on the input buses 4 of the device and on the tires 5-9 of the device settings. The connection of the first inputs of elements And 1 of each group with the outputs of the flip-flops 3 and the input buses 4 devices, respectively, and the second input. DI elements I 1 - with tires 5–9 device settings simplifies the proposed device in the general case by significantly reducing the number of elements I 1 while slightly increasing or maintaining the number of triggers 3. The presence of tires 5–9 device settings provides multifunctional; device availability. An apparatus for logical processing of digital data containing AND, OR elements, triggers, the information content of each trigger is connected to the output of the corresponding OR element, whose inputs are connected to the outputs of the AND elements of the corresponding group, the trigger synchronization inputs are connected to the synchronization bus of the device, different that, with the purpose of simplification, the first inputs of elements AND of each group are connected to the outputs of the flip-flops and input buses of the device, respectively, and the second inputs are connected to the bus s device settings. Sources of information taken into account in the examination 1. The author's certificate of the USSR 500525, cl. Gi 06 F 7/00, 1976. 2. Lazarev V.G. et al., Synthesis of control automata. M., Energie, 1978, p. 18-19. 3. Automation and computer technology, 1980, 4, p. 24, FIG. 2 (prototype).