SU972523A1 - Device for determination of vector argument and modulus - Google Patents

Description

The invention relates to computing.

A device for determining the modulus and argument vectors, wherein said parameters representing the amplitude and phase ^{garmonichesko-:} th oscillation. Sine and cosine voltage is supplied to the inputs of the corresponding digital controlled resistors, the value of which is regulated by! depending on the values of the rectangular coordinates. Totalizer fluctuation. This signal is fed to the input of the phasemeter, in which its phase is determined relative to the oscillation of the generator. At the same time, depending on the values of the rectangular coordinates, the scale of the digital controlled resistors C ί J.

. 2

However, the measurement of the scale of the · components of the vector has a one-sided ха. rakter (only upward). Therefore, expansion is not provided.

'dynamic range of the device in case of overflow of input registers. The closest to the invention in technical essence is a device for determining the polar coordinates' of a vector in which the argument and module are generated using a sum-difference block connected to the outputs of digital controlled resistors and a phase meter associated with it [2 ]. A disadvantage of the known device is the limited dynamic range, the expansion of which by increasing the number of discharges and control inputs of digital controlled resistors is associated with a loss of accuracy of the device on small signals.

The purpose of the invention is the expansion of the dynamic range.

This goal is achieved by the fact that the device for determining the modulus and argument of the vector, containing a generator of quadrature harmonic voltages, sine and cosine outputs

972523 4 of which each is connected through a phase inverter and directly to the inputs of the corresponding switch, the output of each switch is connected via a digital controlled resistor to the corresponding 5 input of the summing-subtracting unit, the first and second outputs of which are connected to the corresponding inputs of the digital phase meter, the control inputs of the switches are connected to 10 corresponding bus signs of the rectangular coordinates of the vector, one of which is connected to the installation input of the digital phase meter, additionally contains a plate detector, ana-15 logo-digital converter, delay element, first and second decoders, pulse generator, first and second keys, reversible counter, first and second controlled dividers, controlled jq multiplier and memory register, with buses codes of the first and second rectangular coordinates of the device vector are connected to the information input of the first and second controlled divisors, the outputs of which are connected to the control inputs of the first and second digital controlled resistors, respectively, the first output of the sums The output-subtracting unit is connected through an amplitude- ₃₀ detector to the information input of an analog-to-digital converter, the output of which is connected to the inputs of the first decoder and the controlled multiplier, the first output of the first decoder is connected to the first control input of the first key, and the second output of the first decoder is connected to. the first control input of the second key, the output of the pulse generator through the first and second keys is connected to the summing and subtracting inputs of the reverse counter, the output of which is connected to the input of the second decoder, the group of n outputs of which is connected to - ^^ responsibly with the group of η control inputs of the controlled multiplier and with groups of η control inputs of the first and second controlled dividers, the output of the controlled multiplier is connected to the information input of the memory register ⁵⁰ , the first output of the second decoder is connected to the second th second switch control input, n-th output of the second decoder coupled to a second control input of the first switch, you are a pulse generator ⁵⁵ is connected to the stroke timing input of the digital phase meter, memory and register through the element 'delays to the synchronization input of the analog-to-digital converter.

The drawing shows a diagram of the device.

The device comprises a quadrature harmonic voltage generator 1, phase inverters 2 and 3> switches 4 and 5, digital controlled resistors 6 and 7, a sum-subtracting unit 8, a digital phase meter 9, an amplitude detector 10, an analog-to-digital converter 11, a delay element 12, a decoder 13, pulse generator 14, keys 15 and 16, reversible counter 17, controlled dividers 18 and 19, controlled multiplier 20, memory register 21, decoder 22. Counter 17 and decoder 22 form a control unit.

The device operates as follows.

The signals U ^ = U _m s incut and U ^ U ^ cosiPt of the sine and cosine outputs of the generator 1 are fed to digital controlled resistors 6 and 7 directly or through phase inverters 2 and 3 depending on the position of the switches 4 and 5, which are set by signals of signs of rectangular coordinates vectors ZN _x and ZN-y. The latter determine the quadrant in which the vector is located on the coordinate plane.

Codes N _x and N _{5 of the} rectangular coordinates of the vector are fed to the control inputs of digital resistors 6 and 7 through controlled dividers 18 and 19, each of which has η stages of division with transmission coefficients to _A = i / d ¹ ₀ ^>

where 1 = 1, 2, .... η is the number of the division level;

th ₀ > 1 is a constant value equal to the dynamic range of digital • resistors 6 and /.

The output signals of digital controlled resistors 6 and 7 are fed to the inputs of block 8, at the outputs of which we obtain harmonic signals Uj and U ₄ corresponding to the vector difference and the vector sum.

The phase shift Ψ between the signals Uj and U _{4 is} converted by the digital phase meter 9 into the vector argument code equal to Νφ = 4/2 in the case when the vector is in the first and second quadrants, and ify = * # / 2 + 180 ° in the case when the vector is in the third and fourth quadrants.

The addition of a phase shift of 180 ** in the latter case is carried out by the initial installation of the phasemeter 9 counter in the corresponding state by the ZNu signal. 5

One of the signals Uj or ^ is detected by an amplitude detector 10, the output signal of which is converted by an analog-to-digital converter 11 into a code of the number * 0 where К ^ is a constant coefficient.

The number N is multiplied in a controlled multiplier 20, which has η multiplication steps, increases in by the value —and write the memory register 21, at the output of which we obtain the code of the vector module ^Ν ιτΜ ^Ν1 χ · ^Ν 3 ·

The inclusion of the required stages of division of the controlled dividers 18 and 19, as well as the steps of multiplying the controlled multiplier 20 is carried out by a signal- ²⁵ mi from the outputs of the decoder 22, which, together with the dividers 18 and 19, are digital. with resistors 6 and 7, block 8, an amplitude detector 10, an analog-to-digital converter 11, an EO delay element 12, a decoder 13, a pulse generator 14, a reversible counter 17, and keys 15 and 16 form a closed automatic control system that operates as follows 06 -35 at a time.

When the condition Ν <Ν _{0 is} fulfilled, where Ν _ο is the lower threshold value of the number Ν, the signal unlocking the key 16 appears at the output of the decoder 13. Each pulse of the generator 14 passes through the key 16 and through the counter 17 and switches the decoder 22 to -being, which corresponds to an increase in transmission ratio dividers ₄₅ and 18, 19 and decrease the gain multiplier 20 in the ₀ ° time. As a result, the number N increases by 0θ times.

Similar switchings occur until the condition N ₀ <N <D _Q N ₀ is satisfied, upon which the decoder 13 does not generate signals, unlocking keys 15 and 16, and there are no switches in the device _JS DIT.

When a control signal appears at the first output of the decoder 22, which corresponds to the inclusion of the de-step.

dividers 18 and 19 with the highest transfer coefficient Kd = 1, the key 16 closes and disconnects the counter 17 from the generator 14, protecting the device from cyclic switching under the condition N <N ₀ .

In this state, the device will remain until the condition Ν ·> ϋ ₀ Ν ₀ is satisfied. At the output of the decoder 13 a signal appears, the lock releasing key 15. Each pulse generator 14 passes through the switch 15 and the decoder 22 switches to a state which corresponds to a reduction ratio transmission dividers 18 and 19 and increasing the gain of the multiplier 20 to 0 _{on the} time. As a result, the number N decreases by D _o times.

Similar switching occurs until the condition n _o <n <d _o n _o is satisfied.

When a control signal appears at the last ηth output of the decoder 22, which corresponds to the inclusion of the division stage of the dividers 18 and 19 with the lowest transmission coefficient 1 ^ = 1 / 0р ' ⁴ , the key 15 closes and disconnects the counter 17 from the generator 14, protecting the device from cyclic switching under the condition N> D ₀ N _o .

In this state, the device will remain until condition N <N ₀ is satisfied. Further, the device works similarly.

Thus, during operation of the scale Apparatus rectangular coordinates N _x and the vector changes automatically controllable dividers 18 and 19 so that the number N at the output of analog-to-digital converter 11 is held in a limited dynamic range _of 0.

The synchronization of the operation of the analog-to-digital converter 11, the memory register 21 and the digital phasemeter 9 is carried out by the pulses of the generator 14. The delay element 12 provides a delay in starting the analog-to-digital converter 11 by the time required to establish the signal at the output of the detector 10 when switching the device elements once.

The pulse repetition period of the generator 14 is chosen to take longer than necessary to establish the signal at the output of the detector 10 and convert it to the analog-to-digital converter / 972523 at once switching the device elements.

If the rectangular coordinates Νχ and the vector are represented by binary codes, then the value of D _{o is} chosen equal to 0 _about «2 ^t , where m is an integer. In this case, the division of the binary number by the value is introduced to the shift; the numbers by m (il) of the binary bits in the direction of the least significant bits, and the multiplication by the shift of the number by m (il) of the binary bits in the direction of the highest bits. In this case, the controlled dividers 18 and 19 and the multiplier 20 are re * lized in the form of controlled switches providing the required number shift.

The technical and economic effect of the use of the invention is determined by the possibility of coordinating a wide dynamic range of changes direct. • angular coordinates with a limited • dynamic range of digital controlled resistors.

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Claims (2)

The invention relates to computing technology. A device is known for determining a modulus and a vector argument in which said parameters are represented by the amplitude and phase of the harmonic oscillation. The sine and cosine voltages are fed to the inputs of the corresponding digital controlled resistors, the value of which adjusts with depending on the values of the rectangular coordinates. Totalizer oscillation. It enters the phase meter input, in which its phase is determined relative to the oscillator oscillations. In this case, depending on the values of the rectangular coordinates, the scale of the digital controlled resistors 1 is changed. However, the measurement of the scale-components of the vector is one-sided (only upwards). Therefore, it is not possible to expand the dynamic range of the device in the overflow of the input registers. Closest to the invention by technical essence is a device for determining the polar coordinates of a vector, in which the argument and the module are generated using a sum-difference block connected to the outputs of the Digital Controlled Resistors and the associated C2 phase meter. A disadvantage of the known device is the limited dynamic range, the expansion of which by increasing the number of bits and control inputs of digital controlled resistors is associated with a loss of accuracy of the device on small signals. The purpose of the invention is to expand the dynamic range. The goal is achieved by the fact that the device for determining the modulus and vector argument, containing a quadrature harmonic voltage generator, the sine and cosine outputs 39 of which are each connected via an inverter phase and directly to the inputs of the corresponding switch, the output of each switch is connected via a digital controlled resistor the corresponding input of the summing-subtracting unit, the first and second outputs of which are connected to the corresponding inputs of the digital phase meter, the control inputs of the switch The connectors are connected to the corresponding tires of the rectangular vector coordinates, one of which is connected to the digital phase meter installation input, additionally contains an amplitude detector, an analog-to-digital converter, delay element, first and second decoder pulse generator, first and second keys, reversible counter, the first and second controlled dividers, the controlled multiplier and the memory register, and the bus codes of the first and second rectangular coordinates of the device vector are connected to the information input The first and second controlled dividers, the outputs of which are connected to the control inputs of the first and second digital controlled resistors, respectively, the first output of the summation-subtraction unit through an amplitude detector connected to the information input of the analog-digital converter, the output of which is connected to the inputs of the first decoder and a controlled multiplier, the first output of the first decoder is connected to the first control input of the first key, the second output of the first decoder is connected to the first control input to key, the output of the pulse generator through the first and second keys is connected to the summing and subtracting inputs of the reversible counter, the output of which is connected to the input of the second decoder, the group of n outputs of which is connected, respectively, with a group of n control inputs of the controlled multiplier and groups of n control inputs of the first and second controlled dividers, the output of the controlled multiplier is connected to the information input of the memory register, the first output of the second decoder is connected to the second control input of the second The second key, the pth output of the second decoder is connected to the second control input of the first key, the output of the pulse generator is connected to the clock input of the digital phase meter, memory register and through an electronic delay with the clock input of the analog-digital converter. The drawing shows a diagram of the device. The device contains a generator of quadrature harmonic voltages, phase inverters 2 and 3. Switches 4 and 5 digital controlled resistors 6 and 7, summing and subtracting unit 8, digital phase meter 9, amplitude detector 10, analog-to-digital converter 11, delay element 12, decoder 13, generator of pulses, keys 15 and 16, reversible counter 17, controlled dividers 18 and 19, controlled multiplier 20 memory register 21, decoder 22. Counter 17 and decoder 22 constitute a control node. The device works as follows. The signals UU siniot and the sine and cosine outputs of generator 1 are fed to digital controlled resistors 6 and 7 directly or through phase inverters 2 and 3, depending on the position of the switches k and 5, which are set by the signs of the rectangular coordinates of the 3N vector X and the latter determine the quadrant in which there is a vector on the coordinate plane. The codes N X and ti at the rectangular coordinates of the vector are fed to the control inputs of digital resistors 6 and 7 through controlled dividers 18 and 19 each of which has n division stages with transmission coefficients where, 2, the division stage number; constant value equal to the dynamic range of digital resistors 6 and 7 The output signals of digital controlled resistors 6 and 7 are fed to the inputs of block 8, the outputs of which will give harmonic signals Uj and 1C corresponding to the vector difference and vector sum. The phase shift between the signals UJ and 1) 4 is converted by digital phase meter 9 into the vector argument code, equal to MC, H / 2 in the case when the vector is in the first and second quadrants, and Nj # / 2 + l80 ° in the case when the vector is in the third and fourth quadrants. The latter case is carried out by the initial installation of the counter of the phase meter 9 in the appropriate state by the signal ZN. One of the signals L), or Z is detected by an amplitude detector 10, the output of which is converted by analog-digital converter 11 to the code of the number MgC, where K. is a constant coefficient. The number N is multiplied in the controllable multiplier 20, which has n steps of intelligence, by the value of K / 5-g; -and is written to memory register 21, at the output of which we get the code of the vector module VNt N Enabling the required division levels of the controlled divisors 18 and 19, as well as the multiplication steps of the controlled multiplier 20, are carried out by signals from the outputs of the decoder 22 ,. which, together with dividers 18 and 19, digital resistors 6 and 7, block 8, amplitude detector 10, analog-digital converter 11, delay element 12, decoder 13, pulse generator 1, reversible counter 17, and keys 15 and 16 forms a closed system of automatic regulation, working next time. When the condition where NO is the lower threshold value of N, the output of the decoder 13 is a signal that unlocks the key 16. Each pulse of the generator AND passes through the key 16 and through the reversible counter 17 and switches the decoder 22 to a state that corresponds to an increase the ratio of the transmission of dividers 18 and 19 and a decrease in the ratio of the multiplier 20 to Dg times. As a result, the number N is increased by a factor of. Similar switchings occur until the condition is fulfilled, during which the decoder 13 does not generate signals that unlock the keys 15 and 16, and switches in the device do not occur. When a control signal appears at the first output of the decoder 22, which corresponds to the inclusion of a division stage. the transmission effect, the key 16 is closed and disconnects the counter 17 from the generator C, protecting the device from cyclic switching when the condition is met. In this state, the device will remain until the condition, NO, is met. At the output of the decoder 13, a signal appears that unlocks the key 15. Each generator pulse C passes through the key 15 and switches the decoder 22 to a state that corresponds to a decrease in the transfer ratio of dividers 18 and 19 and an increase in the ratio of the gear multiplier 20 to Dg . As a result, the number N is reduced by DQ times. Similar switchings occur until the condition, j, is satisfied. When a control signal appears at the last nth output of the decoder 22, which corresponds to the inclusion of the dividing ratio cty of dividers 18 and 19 with the lowest transmission ratio 1, the key 15 closes and turns off the counter 17 from the generator 14, protecting the device from cyclic switching (jNo. In this state, the device will remain until the condition is fulfilled. Then the device works in a similar way. Thus, during operation of the device, the scale of rectangular coordinates N and N of the vector The controlled dividers 18 and 19 are changed so that the number N at the output of the analog-digital converter 11 is kept in a limited dynamic range DQ. Synchronization of the operation of the analog-digital converter 11, the memory register 21 and the digital phase meter 9 is carried out by generator pulses 1. Element the delay 12 provides a trigger delay for the analog-digital converter 11 for the time it takes for the signal to be set at the output of the detector 10 when the device elements are switched once. The repetition period of the generator pulses It is chosen longer than the time required for setting the signal at the output of the detector 10 and converting it into an analog-digital converter / 9 gate 11 with a single switch, the scientific research institute of the device elements. If the rectangular coordinates N and H of the vector are represented by binary Dgs, they are chosen as codes, then the value is, where m is an integer. In this case, dividing a binary number by the value leads to a shift, numbers by m (i-l) binary bits in the direction of the lower digits, and multiplication - by a shift of the number by m (i-l) binary bits in the direction of the higher bits. In this case, the controllable dividers 18 and 19 and the multiplier 20 are pea in the form of controllable switches providing the required number shift. The technical and economic effect of the use of the invention is determined by the possibility of matching a wide dynamic range of ave. Coordinated coordinates with a limited dynamic range of digital controlled resistors Formula of the Invention A device for determining the modulus and argument of a vector, comprising a quadrature harmonic voltage generator, the sine and cosine outputs of which are connected each via a phase inverter and directly to the inputs of the corresponding switch, the output of each switch is connected through a digital controlled resistor with a corresponding input of the summing-subtracting unit, the first and second outputs of which Connected to the corresponding inputs of a digital phase meter, the control inputs of the switches are connected to the corresponding buses of the signs of the rectangular coordinates of the vector, one of which is connected to the installation input of the digital phase meter, characterized in that, in order to expand the dynamic range, the device contains an amplitude detector, analog-to-digital converter, delay element, first and second decoders, pulse generator 3, first and second keys | Chi, reversible counter, first and second controlled dividers, controlled multiplier and memory register, while the bus codes of the first and second rectangular coordinates of the device vector are connected to the information input of the first and second controlled dividers, the outputs of which are connected to the control inputs of the first and second digital controlled resistors, respectively, the first output is summing -exciting unit through an amplitude detector connected to the information input of an analog-digital converter, the output of which is connected to the inputs of the first decoder and controllable multiplier, the first The first output of the first decoder is connected to the first control input of the first key, the second output of the first decoder is connected to the first control input of the second key, the output of the pulse generator is connected to the summing and subtracting inputs of the reversible counter through the first and second keys the decoder, a group of n outputs of which is connected respectively, but with a group of n control inputs of a controllable multiplier and with groups of n control inputs of the first and second controllable dividers, you od controlled multiplier connected to the data input of a memory register. The first output of the second decoder is connected to the second control input of the second key, the pth output of the second decoder is connected to the second control input of the first key, the output of the pulse generator is connected to the clock input of the digital Phasometer, memory register and through the delay element to the clock input of the analog-digital converter . Sources of information taken into account in the examination 1. USSR author's certificate number, cl. G About G 7/22, 1978. 2. USSR author's certificate №, cl. G About G 7/22, (prototype).