SU964455A2 - Ultrasonic flowmeter - Google Patents

Description

The invention relates to the technique of ultrasonic measurements, and more specifically to the field of measuring the speed and flow of substances, and can be used in land reclamation, oil, chemical, hydrometallurgical and other industrial sectors.

According to the main auth. 802792 is known for an ultrasonic flow meter, including two synchrosets, consisting of series-connected prohibition circuits, a driver, and an acoustic transducer and a receiver common to the synchroable, and two trigger units connected to the synchroholes, each of which consists of a search and auto-tuning phase, which is connected through an auto-oscillator to the frequency divider, and the inputs to one of the inputs of the storage element and the I scheme, while the output of the storage element is connected to the input of the AND circuit, the output of which is connected to the second with the inputs of the imager and the inhibit circuit, the output of the storage element connected to the second INPUT, and the measuring block consisting of a mixer, the inputs of which are connected to the outputs of two autogenerators, and the output to

an input indicator, the first sync ring is provided with a working pulse shaper, the input of which is connected to the output of the frequency divider, and the output is connected to the inputs of the AND circuit and the storage element, and the second synchro ring is equipped with a working shaper of the pulse that is in / out connected to K | output frequency divider to his

10 outputs are connected by one of the inputs to the analysis unit, the other input of which is connected to the BTOpoNv output of the former synchroable operating pulse former, and the outputs one to the inputs

15 of the circuit And and the storage element, and the second to the third input of the driver 1.

In a known flow meter, it is impossible to implement a high-speed analysis unit, which leads to a decrease in

20 measurement accuracy.

The purpose of the invention is to improve the measurement accuracy by providing a fast operation of the analysis unit.

The goal is achieved

25 in that, in a known ultrasonic flow meter, the analysis unit contains a frequency divider, a first circuit AND connected by a first input to the output of a frequency divider, a second circuit AND,

30 connected by the first input to the output of the first circuit And, the third circuit I. connected by the first input to the output of the first circuit And, the first memory element connected by the first input to the output of the third And circuit, the second memory element connected by the first input to the first output of the first element memory, the fourth And circuit, connected by the first input to the first output of the second memory element, and the fifth And circuit, connected by the first input to the Second output of the first memory element, the second input to the second, the first input of the first memory element and to the second output sec memory element and the output to the second input of the frequency divider, the first input of which is combined with the second input of the first AND circuit and the second input of the second memory element, as well as the second input of the second I circuit, the second input of the fourth circuit Both and the second input of the third circuit AND are the inputs of the analysis unit, and the outputs of the second and fourth circuit AND are its outputs. FIG. 1 is a block diagram of an ultrasonic flow meter; in fig. 2 is a block diagram of the analysis unit; in fig. 3 - voltage diagrams showing the operation of one synchro-ring with the trigger unit; in fig. 4 voltage diagrams for simultaneous operation of two sync rings in one acoustic channel. The ultrasonic flow meter contains an acoustic transducer 1 (Fig. 1) with piezoelements 2 and 3, autogenerators 4 and 5, dividers 6 and frequencies, drivers 8 and 9 working pulses, search and auto-tuning circuit 10 and 11, phase, block 12 of circuit analysis I 13 and 14, memorize the elements 15 and 16, the prohibition schemes 17 and 18, the formers 19 and 20, the receiver .21, the mixer 22 and the indicator 23, the first synchro-ring (which is the master) consists of serially connected common for the synchro rings of the receiver 21 , schemes 18 ban shaper 20 and common to sync rings aku A static converter is connected to the first synchronizing ring by a block consisting of the search 11 circuit and an auto-tuning phase connected by its output to the input of the auto-oscillator 5, the output of which through the frequency divider 7 and the imaging unit 9 operating pulses are connected to the first inputs of the search circuit 11 and the phase auto-tuning of the I circuit 14 and the memory element 16, the output of the circuit I.14 is connected to the second inputs of the imaging unit 20 and the prohibition circuit / u 18, the output of which is connected to the second input of the storage element 16, the output of which is connected to the second inputs of the circuits l 11 searching for 1A phase-locking and shields AND 14. | W; a sync ring (which is slave consists of a series-connected receiver 21, cxe№i 17 inhibition, shaper 19 and acoustic transducer 1, to the second synchro ring; the start-up unit, consisting from the search and auto-tuning circuit 10, connected by its output to the input of the auto-oscillator 4, the output of which is through a frequency divider 6, a driver 8 operating pulses and a block 12 c1 Nali and connected to the first inputs of the search and auto-tuning circuit of Phase 10, the And 13 circuit and the memory element 15, the output of the circuit 13 is connected to the second barr of the prohibition pcheme 17, the output of which is connected to the second input of the storage element 15, the output of which is connected to the second inputs of the search circuit 1 and auto-tuning of phase 10 and the circuit 13, | the input of the analysis unit 12 is connected to the second output of the imaging unit 9 of the working pulses of the first sync ring, and its second output is connected to the third input of the imaging unit 19 of the first sync ring, the measuring unit consists of a mixer 22, the inputs of which are connected to the outputs of two autogenerators 4 and 5, and the output to the input of the indicator 23. Analysis unit 12 contains a frequency divider 24. 2), the output of which is connected to the first input of the first AND 25 circuit, connected by its output to the first input of the second circuit J 26 and the first input of the third PG 21 connected to the installation input of the first element 28 of the memory whose first output is connected with the information input of the second memory element 29, the first output of which is connected to the first input of the fourth AND 30 circuit. The inverse output of the memory element 29 is connected to the second input of the fifth circuit and 31 and to the erase input of the memory element 28, the inverse output of which is connected to first in Odom AND gate; 31, connected to its output to the setup input of the splitter 24 frequency. The first input of the frequency divider 24, combined with the second input of the AND circuit 25 and the clock input of the memory element 29, as well as the second input of the AND circuit 26 and the second input of the AND circuit 30 are one of the inputs of the analysis unit 12. The second input of AND circuit 27 is the other input of analysis block 12. The outputs of the circuits And 26 and 30 are respectively the one and the second output of the analysis device. The device works as follows. The voltage from the output of the search and auto-tuning circuit 11 of the phase {FIG. 3 e) is fed to the input of the controlled oscillator 5, rearranging its frequency. At the time of submission of pytagacal

the voltage at the output of search 11 and phase self-tuning is zero. Before this, the period of the following pulses is that of the control of its own oscillator 5 is minimal. 3 a). In addition, the condition must be fulfilled so that the pulse period from the output of the frequency divider 7 with the division factor K is shorter than the minimum propagation time of the signal through the electroacoustic channel. The tuning of the period of the controlled oscillator 5 is chosen so that the maximum period of the pulses at the output of the frequency divider 7 is greater than the maximum time of propagation of the signal through the electroacoustic channel. At the moment of supplying the supply voltage, there is no pulse at the output of the oscillator 5, therefore there are no pulses and at the outputs of the frequency divider 7 and the driver 9 operating pulses. In this case, the output of the imager 9 working pulses is low. This level is fixed by the memory element 16, for which P, 5-flip-flop can be used, with a high level at its output. At the output of the prohibition scheme 18, in which quality the AND-NES scheme can be used, the initial state is high.

Since the output of the storage element 16 is connected to the input of the schema f / s AND 14, the first positive impulse from the output of the imaging unit 9 of the working impulses (FIG. 3 b) through the AND circuit 14 (FIG. 3 c) goes to the prohibition circuit 18, opening it, and to start the shaper 20. The forglier 20 starts. The back edge is a positive impulse a, i.e. by negative differential. The impulse of the driver 20 (Fig. 3 g) arrives at the piezoelectric element 3, is converted into an ultrasonic signal which passes through a controlled medium and is received by the piezoelectric element 2, which transforms it into an electrical signal. This signal arrives at the receiver 21, where it is amplified and formed into a rectangular impulse (Fig. 3 d, after which it goes to the prohibition circuit 18.

The pulse at the output of the receiver 21 is delayed relative to the pulse from the output of the imaging unit 20 for the time zld. Since the pulse period from the output of the imaging device 9 is working pulses is yutimal and less than 1-5 earlier than the pulse from the output of receiver 21; and the inhibitor circuit 18 is closed by the time of arrival of the pulse from receiver 21. However, the second pulse from the output of circuit 14 will pass

on the electro-acoustic channel is similar to the first one, etc.

At the same time, positive pulses from the output of the imager 9 working pulses are fed to the circuit 1

5 search and auto-tuning phase, increasing the voltage on her} you. At the same time, the period of the controlled auto-generator 5 is increased until by the moment of arrival of the pulse from the receiver 21 to the prohibition circuit 18 the prohibition circuit 18 is not an open pulse from the output of the circuit H 14. Then the pulse from the receiver 21 passes through the prohibition circuit to the input of the driver 20 of the excitation pulses, to start it with the leading edge of the negative pulse - the leading synchronous ring of the flow meter is started. One-time — ieHHo negative output pulse

2Q of the prohibition circuit 18 is fed to the input of the storage element 16, setting a low level at its output, so that a ban is applied to the circuit 14 and this leads to a restriction on the output pulse (time moment fig, Sv). In this case, the leading edge of the positive pulse at the output of the circuit AND 14 will coincide with the leading edge of the negative

Q pulse at the output of the circuit 18 prohibition ie The further operation of the controlled oscillator 7 does not affect {the operation of the synchrock, hence the controlled oscillator 5 is automatically switched off. Further

35 master synchro-ring runs continuously.

After that, the circuit 11 of the search and auto-tuning phase from the search mode goes into auto-tuning mode

40 phases of controlled autogenerator 5 with synchro-autocirculation pulses. A high level at the output of the storage element 16 is again set at the falling edge of the positive impulse from the output of the imaging unit 9 operating pulses. The impulses from the output of the imaging unit 9 working pulses arrive at the input of the search and auto-tuning circuit 11, and

jQHa Its other input is received by pulses from the output of the storage element 16, the leading edge of which coincides with the leading edge of the synchro-ring pulse, passed 1; lego prohibition scheme 18.

The circuit 11 for searching and auto-tuning the phase selects the time error between the pulse from the output of the 9 operating pulses and the leading edge of the autocirculation pulse of the sync ring, converts the error into the control signal that controls the frequency and phase of the oscillator 5. Moreover, the adjustment is made so that the leading edge of the autocirculation pulse

65syncholes, .pro time was

inside the pulse from the output, 9 working pulse pulses form, preferably in its middle. Then the prohibition circuit 18 and, therefore, the leading synchro-ring will open on the leading edge of the pulse from the output of the driver 9 working pulses, and close on the leading edge of the pulse of the single ring, i.e. open synchroclock time will be half the pulse duration from the generator of 9 working pulses. From the point of view of the noise immunity of the pulse duration from the output of the imaging unit, 9 working pulses are chosen equal to (from the period of the autocirculation pulses.

In case of violation of the electroacoustic channel, the pulses from the output of the former 9 working pulses will continue to enter the input of the search and auto-tuning circuit 11 of the phase, increasing the voltage by its% 1X € Sj. 11; In this case, the pulse period at the output of the imaging unit 9 of the operating pulses will increase. When the voltage at the output of the circuit 11 of the bus terminal and the auto-tuning of the phase is this, the period will be maximum, the circuit 11 of the search and the auto-tuning of the phase will discharge this voltage to zero, after which the device will work as described above. Thus, in the master sync pulse, the pulses from the output of the oscillator 5 are connected in frequency and phase with the sync pulse pulses, but the frequency of these pulses is K times higher than the frequency of the synchro pulse pulses, where K is the division ratio of the pulse frequency divider. In order to start the flow meter in the first cycle of changing the pulse period of the autogenerator 5, the every single pulse period from the output of the imaging unit 9 working pulses is changed by no more than: pulse duration from the output of the imaging unit.

Similarly, the launch and recovery of the slave synchro-ring operation takes place.

With simultaneous two synchroclic diagrams, the stresses on the tricks of individual blocks would appear in the following way. FIG. 4a shows the pulses at the output of the pulse frequency divider 7, in FIG. 4c - pulses j arriving from the imager 9 working pulses, on the circuit And 14; in fig. 4d - signals of the leading sync ring received by the receiver; and in fig. 4D - the pulses emitted by the shaper 20. As can be seen from FIG. 4d and FIG. 4e, the master sync ring operates continuously and its period is equal to T leading.

The division factor of the divider .6 frequencies are chosen in such a way that

the frequency of the pulses at its output was an integer number of times higher than the frequency of the pulses of the driven sync ring (in Fig. 4e - two paSa | and Fig. 46).

; Since the oscillators 4 and 5 are rigidly connected in frequency and phase with the sequences of pulses of the corresponding sync rings, it is easy to fulfill the prohibition impulses to cover signals received by piez sensors. The presence of impulses of protection is necessary to ensure the elimination of moments of coincidence of the sync ring pulses. In addition, a rigid connection in frequency and phase of the oscillator 4 with the pulses of the driven synchrool allows the former 8 working pulses to generate pulses (Fig. 4i) whose fronts coincide with the fronts of the pulses radiated by the fordvar 19 (Fig. 4n). These pulses (Fig. 4i) will be referred to as the stored phase pulses. Since the frequency of the pulses from the output of the frequency divider 6 is an integer number of times higher than the frequency of the driven synchro-ring, the driver 8 of the working pulses generates prohibition pulse sequences (Fig. 4g), the stored phase pulses (Fig 4i) pulses that must arrive at the AND circuit 13, the storage element 15 and the search and auto-tuning circuit 10. The phase (Fig. 4h) with a frequency is also an integer number of times higher than the frequency of the driven synchro ring (in the considered case twice Therefore, each of the formed sequences can be considered as the result of superposition of two sequences of pulses (even and odd) with a frequency equal to the Slaughter Frequency of the synchroable but shifted from each other in phase by a half-period of the driven synchroable. .ti, coincide with the phases of the pulses emitted by shaper 19, i.e. syn} phonons with slave synchro ring pulses. The even-sequence prohibitions cover the received 1F1 signal (Fig. 4m), and only even-sequence pulses are received through the analysis device 12 to the AND 13 circuit, the storage element 15 and the search and auto-adjust phase circuit 10.

Claims (1)

Since the master and slave of the sync ring have a frequency difference, their signals inevitably gradually approach each other. In order to exclude the moment of coincidence of these signals, they give priority to the leading sync-ring - it p & b ate continuously. In addition, analysis block 12 controls the coincidence and even banning mycos from the generator 8 working and inhibiting pulses from the generator 9 working pulses. After a match has occurred, analysis block 12 provides a phase shift in the autocirculation pulses of the slave sync ring by half a period. This is achieved by the fact that the analysis unit ceases to skip, on the AND-13 scheme, the pulses of an even sequence and begin to pass pulses of an odd sequence that is shifted by half a square with respect to the even one. In this case, the interlocking circuit 17 is closed to pulses. synchro rings corresponding to even sequences and. open for pulses corresponding to odd. At the same time, the block Aval for skips to launching the former 19 a single pulse of the stored phases from an odd sequence (FIG. 4l), which restores the work of the driven synchro-ring by a period shift. Further phase self-tuning occurs on odd pulses. - After this, analysis block 12 begins to control the coincidence of the prohibition pulses of the master sync rings with the interdiction pulses of the slave odd-sequence synchronous ring (Fig. 4 ". As the synchroc signal approaches, the autocirculation pulses phase shift in the half-cycle slave sync, etc. The pulses of the auto-oscillators 4 and 5 are fed to the mixer 22, which separates the difference frequency K times higher than the frequency difference of the synchro-ring, which is proportional to the flow velocity. The normal operation of the duration of the inhibit pulses is chosen from the condition: where T is the minimum period of the sync ring N is the ratio of the frequency of the pulses at the output of the frequency divider to the frequency of the driven sync ring. For the case in question and the value is chosen from the condition Now consider the work of the analysis unit 12 (FIG. 2). The pulses (Fig. 4g) of the prohibition of the Vedog synchro-ring with a frequency twice as large as that of the synchro-ring come from the output of the driver 8 to the first input of the frequency divider 24 and the second input of the AND 25 circuit. lku first input of AND gate 25 is connected to the output of the divider 24, the output of AND gate 25 will be released. every second impulse to prohibit a slave sync ring (for example, an even sequence). The frequency of these pulses is equal to the frequency of the slave sync ring. These pulses arrive at the first input of the circuit AND 26. The second input of the circuit AND 26 receives the pulses (Fig. 4h) from the output of the imager 8. The frequency of these pulses is also twice the frequency of the driven synchro-ring. Since these pulses are inside the inhibit pulses, every second pulse from the AND 26 circuit output will be separated from the AND 26 circuit arriving at the second input, which are fed to one output of the block 12. The AND 25 pulses from the output of the AND 25 circuit also arrive at the first input of the AND circuit. 27 to the second input of which is fed from the second output of the imaging unit 9 pulses of FIG. 4 b) the prohibition of the leading syncator. If there is no coincidence of the inhibit pulses of the sync rings in the AND 27 circuit, the first output of memory element 28 is low. This level is fed to the information input of the memory element 29; Therefore, at the first output of the memory element 29, the memory 29 will be constantly low. the level closes at the first input the AND 30 circuit and the pulses (Fig. 4i) of the stored phase, which arrive at the second input of the AND 30 circuit from the output of the imaging unit 8, do not pass to the output of the analysis unit 12. With the coincidence of the inhibitory pulses of the synchrocall in the AND 27 circuit, at its output, a pulse, which will go to the installation input of the 28 Ps1m TI element, is set at its first output to a high level. This level arrives at the information input of the memory element 29, preparing it for recording information about the presence of prohibition pulses. This information is recorded in memory element 29 on the leading edge of the pulse (FIG. 4k) prohibiting the slave sync ring arriving at the clock input of memory element 29 from the output of the driver 8, And to restore the work of the driven synchronizer from the driver 8 through the AND circuit 30 (Fig. 4i) of the stored phase. Simultaneously, after the coincidence of the inhibit pulses, the sync ring is low; The level of the second output of the frame element 28 is passed through the circuit AND 31 on. The installation input of the memory element 24 will set a low level at its output. verse At the same time, the selection of even-numbered pulses to prohibit the slave sync ring at the output of AND 25 circuit stops. On the front front of pulse 32 (Fig. 4k low level from the inverse output of memory element 29 arriving at the erasing input of memory element 28, memory element 28 erases the information about the coincidence of the inhibit pulses of the sync ring, and the information input of the memory element 2 is lowered again.The next prohibition pulse from the output of the imaging unit 8 translates the memory element 29 of the memory into the opposite link, and the And 30 circuit closes The first input and the circuit 11 will open at the second input. The low level from the installation input of the memory element 24 is removed, and the inhibit pulses start to stand out at the output of the circuit 25, but now they are shifted by half a period, i.e. sequences, and so on. The proposed ultrasonic flow meter has a higher measurement accuracy than the known flow meters, is simple to implement, and can be made on the basis of radio elements that are currently widely used. Claims of the invention Ultrasonic flow meter according to auth. No. 802792, characterized in that, for the purpose of measuring accuracy, the analysis device contains a frequency divider, the first AND circuit connected by the first input to the output of the frequency divider, the second, AND circuit connected by the first input to the output of the first AND circuit, the third And connected by the first input to the output of the first And circuit, the first memory element connected by the first input to the output of the third And circuit, the second memory element connected by the first input to the first output of the first memory element, the fourth And circuit connected by the first input to the firstoutput of the second memory element and the fifth circuit and connected by the first input to the second output of the first memory element, the second input to the second input of the first memory element, the second input to the second input of the first memory element and to the second output of the second memory element These two outputs and the output to the second input are a frequency divider, the first input of which is combined with the second input of the first AND and the second input of the second memory element, as well as the second input of the second scheme K, the second input of the third AND circuit and the second input of the third AND are the inputs of the analysis unit , but the outputs of the second and fourth circuit AND are its outputs. Sources of information taken into account in the examination, 1. USSR certificate of author 802792, cl. G 01 F 1/66, 1978. / nineteen 79 rs -one P. Xf / J / f ff r l w H // -fj Ff 70v fug. Tftffft / I H