SU962909A2 - Information exchange device - Google Patents

Description

The invention relates to computing and can be used in systems for the exchange of information between computers and subscribers.

RO main auth. 451076, a device for exchanging information is known, which contains a synchronization block whose outputs are connected to the first inputs of serial connection blocks, blocks for connecting parallel channels, priority block, buffer memory block, node block, channel registers, free ae block search unit. time accounts and a control unit connected by a group of inputs and outputs, respectively, with inputs / outputs of the buffer memory block, channel register block block, free zone search block, time counter block, serial channel connection block, and parallel kangshov connection block and priority block output , the inputs of the requests in which are connected to the output of the block of time, the outputs of the blocks connecting the serial and parallel channels, loop innnnh information inputs-outputs with the inputs-outputs of the block of nodes registers kanshov, KO

The latter is connected by two-way communications with the free zone search unit and the e5ufer memory block tl.

The disadvantage of this device is the limited scope of application due to the fact that the device does not provide for the rapid transmission of a computer connected to one of the parallel channels of the exchange device,

10 information in accordance with its priority and information consisting of several messages. In addition, the time zone is rigidly fixed and this leads to the need

15 it is enough to repeat the input of messages to the computer frequently.

The purpose of the invention is to expand the scope of application of the device.

The goal is achieved

20 by the fact that a message analysis block, a message storage time monitoring block and a zone selection block are entered into the device, with the first output of the message analysis block and the output of the message storage time control block connected to the corresponding inputs from the input group of the control unit, the corresponding outputs from the group whose outputs are connected to the first input of the message analysis block to the first and second inputs of the zone selection unit, the first and second inputs of the message storage time control block are connected to the first one and the second ones m outputs of the zone selection unit, and a group of inputs. with the first group of outputs of the message analysis block, a torus group of outputs and the first group of inputs of which are connected respectively to the group of inputs and the group of outputs of the zone selection unit, and the second inputs and outputs respectively to the first output and input the buffer memory block, the second and third inputs of which are connected respectively to the third and fourth outputs of the zone selection unit, and also the fact that the message analysis block contains a switch, whose inputs are connected to the trigger output, respectively and the attribute entries. and the first outputs of the receiving register of symbols and the first and second outputs, respectively, to the inputs of the first and second registers of message priority signs, the first and second registers of the sender’s addressee, and the first and second registers of the message part numbers, the outputs of which are connected respectively to the first and second inputs The first element And the first and second comparison circuits, the first and second outputs of the first comparison circuit are connected respectively to the first inputs of the first, second OR element, the first output The first element And is connected to the first inputs of the second and third elements And, and the second output - to the first inputs of the fourth and fifth elements And, the second input of the second and fourth elements And connected to the first output of the second comparison circuit, the second output connected to the second inputs and the third and fifth elements AND, the outputs of which are connected respectively to the second inputs of the second and first elements OR, the third inputs connected respectively to the outputs of the fourth and second elements AND, and the outputs respectively to the first input The sixth and seventh elements are And, the second inputs of which are connected to the corresponding outputs of the result indication trigger, the outputs of the switch of the time code registers are connected to the input of the storage time code register, the output group of which is the first group of outputs of the block and the output is connected to the first input the third comparison circuit, the second input of the time code reference register connected to the output, the outputs of the sixth and seventh And elements and the third comparison circuit are the corresponding outputs from the second group of outputs a, the first inputs and outputs of which are connected respectively to the first input of the switch of the time code registers and the output of the zone number register, the inputs of the write flag trigger, the zone number register, the result flag trigger and the first and second switches of the switch are connected to the corresponding inputs from the group of block inputs, the input of the receiving register of symbols is connected to the second input of the block, and the second output to the input of the symbol counter, the second output of which is the second output of the block, and the fact that the zone selection unit contains a zone number counter, The address register, the zone definition node with the specified channel address, including the first AND element, the destination register and the address register switch, and the polled zone polling node consisting of the second AND element and the zone number decoder, the output of the address register being connected to the first input of the first And, the second input connected through the register of the recipient with the switch output of the address registers, the first and second inputs of which are connected respectively to the first output of the zone number decoder and the output of the second element AND, and the third progress - with. the second input of the first, the second m the second inputs of the second element And are connected respectively to the first input of the block and the second output of the decoder of the zone number, the input connected to the first output of the zone number counter, the group of inputs of which is the group of inputs of the block, and the first and second outputs. - the first and third outputs of the block, respectively; the first and second outputs of the first element I are the second and fourth outputs of the block, respectively; the third outputs of the zone number counter, the zone number decoder and the first element I are the corresponding outputs from the group of outputs of the block, and that the storage time monitoring unit contains the register of the zone number, the first and second inputs and the output of which are connected respectively to the first and second inputs of the block and the first input of the decoder of registers of time, the output and the second input of The first is connected respectively to the output of the block and the output of the register for inverting the storage time code, the first input connected to the output of the first element I, the first and second inputs of which are connected respectively to the outputs of the zone number counter and the second element AND, the first input of the time code connected to the output of the register , the second inputs of the register, the inversion of the time code of the storage and the second element AND, the input of the counting of the number of zones and the third

the input of the first element And are the corresponding inputs from the group of inputs of the block.

FIG. 1 is a block diagram of the device; in fig. 2-5 are functional diagrams of the zone selection unit (message analysis unit, message storage time control unit and control unit).

The device contains (Fig. 1) blocks 1 for connecting serial channels, blocks 2 for connecting parallel channels, block 3 for priority, block 4 for channel register nodes, block 5 for control, block for searching for free zones, block 7 for timing, block 8 for buffer memory , the zone selection unit 9, the message analysis unit 10, the message storage time control unit 11 and the synchronization unit 12.

The buffer memory unit 8 is designed to accumulate incoming messages and store them until transmission. For this, in block 8 a certain number of zones are allocated, having a fixed number of addresses

The serial connection units 1 and the parallel channel connection units 2 are designed to interface the device for exchanging information with peripheral devices.

The priority unit 3, which determines the priority order of the peripheral devices, receives the service demand signals and prioritizes their service by the control unit 5 and the buffer-unit 8. Noah memory.

The unit 4 of the channel register nodes is intended for organizing the exchange of information between the serial and parallel channel connection units and the buffer memory unit.

The control unit 5 provides the necessary modes of operation when passing messages through the device. Peripheral devices are serviced by unit 5 by providing a short supply. the time of the entire apparatus of block 5 and block 8 to one device. The control unit provides storage and determination of addresses for issuing messages from the buffer memory zones, data on the filled zones, storing the time code and organizes time monitoring of the state of the zones of the block 8.

The block b of the search for free zones is designed to search for free zlny Zloka buffer memory.

The timing unit 7 provides for issuing time intervals (tags) used by the control unit to temporarily monitor the passage of messages through the information exchange device. .

The zone selection block 9 is designed to allocate addresses of the filled zones of the buffer memory block, messages from which are to be transferred to a computer. Vlok 10 ANALYSIS OF CONNECTIONS SERVES to populate the zone number of the buffer memory block, the message from which is to be transferred to the computer first.

The message storage time control unit 11 determines the control over the storage duration of messages to be transferred to the computer in the areas of the buffer memory block.

Block 12 sync generates

5 clock pulses to synchronize all processes occurring in all blocks of the device.

The zone selection unit 9 (Fig. -2) contains a zone number counter 13, a parallel channel address register 14, a zone definition node 15 with a predetermined channel address, which includes the first AND 16 element, the destination zone register 17 and the switchboard) 18 address registers, node 19 defining the division of the filled zone into which

enter the decoder 20 zone numbers and the second element And 21 .;

Block 10 analysis of messages (Fig. C) contains the trigger 22 sign write

0 receiving register 23 characters, score-. chik 24 characters, switch 25, registers 26 and 27 signs; priority of the comparison circuit messages 28-30 and the registers 31 and 32 signs of the address 5 and the sender, the fourth, sixth, first, fifth, third, seventh and second elements AND 33-39, the elements OR 40 and 41, the registers 42 and 43 signs of the part number messages, register

0 44 control time code, register 45 storage time code, switch 46 registers of the code, time, result sign trigger 47 and zone number register 48.

five

The unit 11 for monitoring the storage time of messages (FIG. 4) contains a decoder 49 of the time code registers, the register 50 of the zone number, the register 51 of the inverted time storage code, the first element I 52, the counter

0 53 the number of zones, the second element And 54. and a control code register 55 of time.

The control unit 5 (Fig. 5} contains the node 56 synchronization, register

5 57 acknowledgments, register of 58 filled zones, decoding node 59 of the end of receiving or transmitting, a message, confirmation synchronization node 60, time counter 61, node

0 62 address decryption, 63 zone register nodes (by the number of zones in the buffer memory block), including the time register 64 and the address register 65.

The node 56 is intended for synchronizing and executing sequences of micro-operations of service modes. Register 57 serves to memorize the zone number of the buffer memory block from which the message and the indications were transmitted, the transmission quality of this message to the peripheral device.

Register 58 provides for memorizing the zone number that is filled with the message and the message from which it is necessary to transmit the peripheral device.

Node 59 is designed to decipher the character end of the message in the block of nodes of the channel register registers to record the n-omer of the filled zone in register 58 and in case of termination of message reception and impact on node 60 and register 57 in case of termination of message transmission.

The node 60 serves to prioritize a micro-operation when writing acknowledgment symbols to the zone of the buffer memory block.

Time control counter 61 determines the order of micro-operations that control the state of registers 64. Node 62 provides analysis of the message and the establishment of the channel through which the message must be transmitted, and register 64 the time codes defining the duration of message storage in the zone of block 8 Register 65 serves to store the address of the peripheral device to which the message accumulated in the zone is intended.

The device works as follows. Blocks 1 interact with peripheral devices (not shown), 1 which transmit (receive) messages with symbols, successively over bits; blocks 2 interact with peripheral devices (not shown) that transmit (receive) messages in parallel with symbols. .

On demand service, issued by blocks 1 and 2 in. block 3, the latter allocates a priority channel and transfers control to block 5, which performs the service mode of this channel connection block.

In the process of servicing, in block 4, the current symbol is accumulated, after accumulation of which, block 6 analyzes it. If the received symbol is the symbol of the beginning of the message, the block b searches for a free zone, into which the entire message is taken symbol by symbol. If the first character is not the beginning of the message, then it is discarded, and the search and occupation of the zone of block 8 is not performed.

After the free zone is occupied and assigned to a specific block of connection of channels 1 or 2, a message is recorded in this zone of block 8, in which the accumulation of symbols is made before the character is received, the end of the message, which is also placed in the zone. After receiving the symbol, the end of the message the number of the filled zone is stored in block 5.

According to the message structure, the first character of the message indicates the address of the peripheral device to which the message is addressed, the second to the priority of the message, the third to the addressee of the sender and the fourth to the part number of the message.

During and after the end of receiving messages, the address of the peripheral device is stored in block 5, which analyzes the address and switches on the transmission mode the channel connection block of the peripheral device to which the message is addressed.

The message is output from the zone of block B until the control unit detects the symbol end of the message. After the message has been output to the peripheral device, the control unit generates a confirmation that the message has been issued and writes it to the same zone of the buffer memory from which the message was transmitted.

The generated acknowledgment is transmitted to the device that transmitted the message in the same way as a normal message. After sending the confirmation in block 5 and in the free zone search block, the vacated zone is noted. Block 5 monitors the state of the zones of block 8 by counting time stamps (intervals) generated by block 1. If the time limit is exceeded (time limit), the buffer memory block zone is cleared and added to the number of freed ones.

With the arrival of a message intended for a computer, block 5 organizes its output to the channel in accordance with the order defined by block 9 and 10. Block 9 selects the addresses of the filled zones of the buffer memory block, the messages from which are to be transferred to the computer;

Counter 13 sequentially generates all the zone addresses of the buffer memory block, node 19, and at each address identifies those zones that are occupied by information. When a filled zone is detected through switch 18, the value of the destination of the message is rewritten into register 17. Node 15, by comparing the contents of register 14 and register 17, determines whether the message of this zone is to be transferred to a computer. When the codes in registers 14 and 17 coincide, the message is to be transferred to a computer and information from the buffer memory area containing the 2,3,4th characters of the soobsen is sequentially copied to the receiving register 23.

The message analysis block determines the zone number of the buffer memory block, the message from which is to be transferred to the computer in the first place, analyzing the 2nd, 3rd, 4th message symbols and. the value of the storage time code of this message. The characters 2,3,4 from receiving register 23 through the switch 25 are sequentially overwritten either to registers 26, 31 and 42, or to registers 27, 32 and 43. The sequence of writing characters to register; The code is determined by the contents of the cipher 23-, and the selection of a group of registers is determined by the trigger 22. The counter code 24 corresponds to the sequence number of the message symbol rewritten from the receiving register 21. The trigger status of the recording flag indicates the group of registers 26, 31 and 42 or 27 32 and 43, in which symbols of a less important message from among those received at the previous stage of analysis are located. Simultaneously with the recording of the 2, 3, 4th characters of the message, the code-time for storing the same message from block 5 is written through the switch 46 to the register 45.

After writing the characters of 2,3,4 and storage time code to the corresponding registers, these signs are analyzed by comparison circuits 28, 29 and 30, which can be used with conventional adders, and an AND 3S element. In comparison circuits 28 and 29, the signs are larger than less in the comparison diagram 30 - the sign is greater than or equal to the element AND the signs are equal and not equal.

Comparison circuit 28 compares the contents of registers 26 and 27, which contain signs of the priority of the message, and in the case of a higher priority of the contents of the register 26, sends a signal to the OR element 40, and in the case of a higher priority of the contents of the register 27 - N. element OR 41.

When the comparison circuit produces 28 one of these signals, which are the result of the analysis, the further comparison of the remaining indications of messages by the element 35 and the comparison circuit 30 is not performed. The 28 signal selected by comparison is;; through the element OR 40 or the element OR 41, it arrives at the element AND 34 or the element AND 39. The signal passing through the AND 34 element or the AND 38 element depends on the state of the trigger 47. The state of the trigger 47 corresponds to the presence of 2, 3, 4, 4 characters previously in the block in registers 26, 31 and 42 or in registers 27, 32 and 43. In the event that the 2,3,4th symbols previously received in block 10 are in registers 26, 31 and 42, trigger 47 holds AND 34 in a closed state, and I 38 in an open state: if earlier The received 2,3,4 characters are in registers 27, 32 and 43. Triggers 47 contain an AND 34 element.

0 in the open state, and AND 38 in the closed state. When a signal passes through an element 34 and element 38 to register 48, which is connected to the input 13 of the zone number of the zone selection block 9, and the output of the control unit is entered, the zone number of the buffer memory block is entered. messages from which are in registers 26, 31 and 42 or in registers 27, 32 and 43, at the same time the states of the triggers 22 and 47 are changed to opposites. When the signal does not pass through the element And 34 or the element and 39 in. - register 48 record

5 is not produced, and the states of the triggers 22 and 47 are unchanged.

Element And 35, comparing the contents of registers 32 and 31, and the comparison circuit 29, comparing the contents of registers 43 and 42, operate simultaneously. When the element 35 is selected and the indicator is equal depending on the results of the comparison, the comparison circuit 29 occurs as follows: if the contents of register 42 are greater than the contents of register 42, then SJieMeHT OR 41 generates a signal, which is the result of the analysis, if it is less, then the signal is output per element OR 40. When highlighting

0 by the element AND 35 of the attribute not depending on the results of the comparison by the comparison circuit 29, the following occurs: if the contents of register 42 are greater than the contents of register 43, then an OR 40 signal is output to the element resulting from the analysis; if less, then the signal is output to element OR 41. When the element 35 is issued and the circuit compares 29 of one of the four signals that are the result of the analysis, when they work together, the storage time codes are not compared by the comparison circuit 30. The output of signals, which are the result of the analysis during the joint operation of the element I 35. and the comparison circuit 29, at ele. cops OR 40 and 41 are implemented through AND 39, 33, 36 and 37 elements.

0 The passage of the signal that is the result of the analysis when the element 35 and the comparison circuit 29 work together through the element 34 and element 38 is dependent on the state of the trigger 47

5 and is produced in the same way as when a signal is output by a comparison circuit 2 When a signal passes, which is the result of the analysis during the joint operation of the element 35 and the comparison circuit 29 through the element 34 and the element 38 as well as when the signals from the circuit are compared with 28, the zones of the buffer memory block are entered into the register 48 of the counter 13. At the same time, the states of the triggers 22 and 47 are reversed. If the signal does not pass through the AND 34 element or the AND 38 element to the register 48, the recording is not performed and the state of the flip-flops 22 and 47 do not change. The comparison circuit 43 compares the contents of the register 45 with the contents of the register — 44. A register time code is recorded in the register 44, exceeding which by the amount of the full cycle of the counter 13 operation releases the buffer memory block zone. The comparison circuit 30 outputs a signal,. resulting from the analysis, if the contents of register 45 are equal to or greater than the contents of register 44. With the output of the signal from the comparison circuit, 30 is the same as when passing signals from the comparison circuit 28 through the AND 34 element or the AND 38 element to the register 48 from the counter 13 sets the zone number of the buffer memory block at the same time as the states of the flip-flops 22 and the sign 47 are reversed. In the absence of a signal from the comparison circuit 30 to the .48 recorder, no entry is made and the status of the triggers 22 and 47 are not modified. Upon completion of the full cycle of operation of the counter 13, the zone number,: recorded in resistor 48, is transmitted to block 5 to arrange for issuing a message from it to the computer. Unit 11 controls the storage time. zones of the block of buffer memory of messages which are subject to transfers to the computer. During the operation of block 9 and 10, block 11 modifies the contents of the storage time code, thereby increasing the length of stay of messages in the zones. As the scientific research institute increases the number of messages in the buffer memory zones, the change in the storage time code stops. The current value of the counter code 14 is entered into the register 50 in the control unit for the storage of messages. Counter 53, consisting of two alternates. new meters (not shown), alternately for each full cycle of operation of the counter 13 performs under. account of the number of filled zones, information. qi of which is subject to transfer to a computer. Counter When Achieved; the code values prevent the storage time code from changing during the full cycle of the counter 13. The element 54 compares the contents of register 45 with the contents of register 55. From the results of this comparison, the element 54 generates a gripe. sign is not equal. The change in storage code is performed when this feature is not equal, and at the output of the element 54 and the absence of overflow in the counter 53. In this case, the inverted value (additional code) of the register 45 is entered into register 51, and the additional impulse to form the additional code passes to the register 51 through the element AND 52. If there is no sign that the element 54 is not equal and the indication of the overflow of the counter 53 overflow into the register 51, the inverted value (the return code) of the contents of the register 45 is entered into the register 51. The inverted The value (reverse code) of the contents of register 51, the corrected storage time code in accordance with the contents of register 50, is entered into block 5 via the decoder 49. Thus, the device provides an increase in the speed of transmission of information to be processed in a computer, increasing the number and expansion of the types of connected channels, volumes of information and degree of loading of the device. The control unit 5 operates as follows. According to the service requirements issued by blocks 1 and 2 to block 3, the latter allocates a priority channel and transfers control to block 5, affecting node 56. Node 56 ensures the operation of the entire hardware of block 5 . The service mode of the same channel is transferred to block 4 of the nodes of the channel registers and block b of the search for free zones. When servicing a dedicated channel in receive mode, the character received by block 4 is analyzed by node 59, when the end of the message arrives, the node 59 decrypts it AND writes the number of the zone to which it is written to register 58. After the indicated actions are completed, the node 62 analyzes the address message, which is stored in register 65 since receiving the first character of the message. As a result of the analysis, the node 62 through the node 56 turns on the transfer mode blocks 1 and 2 of the device to which the message is addressed. When servicing the selected message according to the address

the channel in the transfer mode, the character output to the channel through block 4 is also analyzed by node 59. When the symbol passes the end of the message, node 59 decrypts it and, after completion, the message is sent to the peripheral device

room

 Address of the sending device

Confirmation Sign

Address of the device receiving the message

Message quality indication

End message

60 and in register 57 records the number of the zone from which the message was output, with a sign of the transmission quality of this message.

The node 60 of the contents of the register 57 forms a confirmation, which has the form according to the table.

Characters

Value

Confirmation is generated in the same zone of the buffer memory block 8 from which the message has been sent. The confirmation generated in the zone of block 8 is transmitted to the device that transmitted the message in the same way as a normal message. After transmitting the acknowledgment, in the register 58 and in block 6, the vacated zone is noted.

During operation of the device, when receiving or transmitting messages, the time counter 61 controls the monitoring of the residence time of messages in the zones of block 8 of the buffer memory. The monitoring is carried out by zones, taking into account their states of receiving messages and waiting for the output of messages, and when messages are output from the zone.

When the buffer storage zone is transitioned in these states, a certain time stamp indication is written to the corresponding register 64. At the request of the service provided by the timing unit 7, the priority unit 3, through the node 56, acts on the counter 61. At the same time, the unit 7 issues time stamps to the counter 61. If the time stamp in register 64 coincides with the time stamp coming from block 7, one is added to the content of a time counter (not shown) that is in the same node 63. When the content of this time counter reaches the set value, it is considered that the specified time limit has elapsed, after which the counter 61 in the event of overexposure of the zone while waiting for the output of the message output message writes the number of the overexposed zone to the register 57 with a message non-passage sign; in case of overexposure

ZONES in message receive state

5, the counter 61 ejects the accumulated message portion, freeing the zone by inserting the appropriate mark, into the free zone search block.

0

With the arrival of a message intended for a computer, block 5 organizes its output to the channel in accordance with the order defined by the zone selection unit 9 and the message analysis block 10. Blocks .9 and 10 for-. In the next cycle of operation, the number of the zone is determined, the message from which is to be transferred to the computer in the first place. The value of the zone number, allocated on the register 48 of block 10, goes to the node 62, in which it is stored. The thread is on a special register (not shown) and is corrected in subsequent cycles of blocks 9 and 10. Node 62 uses this value of the no. 5 measure of the buffer memory block zone to determine the messages that need to be transmitted to the channel connected to the computer.

0

According to the results of the operation of block 11, the control of the storage time of messages acting in the same diciles with blocks 9 and 10, the values of the codes of the time meters of the nodes are corrected

5 63 for those zones in which messages are received in full and these messages are to be transferred to a computer. Corrected codes for the time of storage of the post. Get out of register 51 through a decoder

0 9 time registers.

Thus, the device provides an increase in the speed of transmission of information to be processed in a computer, an increase in the number and expansion of types of connected channels.

the amount of information and the load on the device.

Claims (1)

Invention Formula 1. A device for the exchange of information - according to the author, No. 451076, which is applied so that, in order to expand the area, the message analysis block, the message storage time control block and the zone selection block are entered into it, and The first output of the message analysis unit fH The output of the message storage time control unit is connected to the corresponding inputs from the control unit input group, the corresponding outputs from the output group of which are connected to the first input of the message analysis unit and the first and second inputs of the zone selection unit, the first The second and second inputs of the message storage time control unit are connected respectively to the first and second outputs of the zone selection unit, and the group of inputs to the first group of outputs of the message analysis unit, the second group of outputs and the first group of inputs of which are connected respectively to the group of inputs and output group of the selection unit zones, and the second input and output, respectively, to the first output and input of the buffer memory unit, the second and third inputs of which are connected respectively to the third and fourth outputs of the zone selection unit. S. The device according to claim 1, characterized in that the message analysis block comprises a switch, the inputs of which are connected respectively to the output of the recording indication trigger and the first outputs of the receiving character register, and the first and second outputs respectively to the inputs of the first and second registers of priority signs of messages, first and second registers of addressee of the sender and first and second registers of the number of the message, the outputs of which are connected respectively to the first and second inputs of the first element And the first and the second comparison circuit, the first and second outputs of the first comparison circuit are connected respectively to the first inputs of the first and second element OR, the first output of the first element AND is connected to the first inputs of the second and third elements And, and the second, output - with the first inputs of the fourth and n of the elements And, the second inputs of the second and fourth elements And connected to the first output of the second comparison circuit, the second output connected to the second inputs of the third and fifth elements And, the outputs of which connected respectively to the second inputs of the second and first elements OR, the third inputs connected respectively to the outputs of the fourth and second elements AND, and the outputs respectively to the first inputs of the sixth and seventh elements AND, the second inputs of which are connected to the corresponding outputs of the result symptom switch outputs Q registers of the time code are connected to the input of the register of the storage time code, the group of outputs of which is the first group of outputs of the block, and the output is connected to the first input , the third comparison circuit, the second input of the time control code connected to the output, the outputs of the sixth and seventh And elements and the third comparison circuit are the corresponding outputs from the second 0 groups of block outputs, the first input and output of .KOTOpQiro are connected respectively to the switch input of the time code registers and the output of the zone number register, trigger inputs 5 of the write attribute, the zone number register, the result sign trigger and the first and second switches of the switch are connected to the corresponding inputs from the block input group, the input register of the characters is connected to the second block input, and the second output is connected to the input of the symbol counter, the second output of which is The second output of the block is. 5 3. The device according to claim 1, characterized in that the zone selection unit comprises a zone number counter, an address register, a zone definition node with a predetermined channel address, 0 including the first AND element, the destination register and the address register switchboard, and the polled zone polling node consisting of the second AND element and the zone number decoder, 5 wherein, the output of the address register is connected to the first input of the first element AND, the second input connected to the addressee’s register c. the switch output of the address registers, the first and second inputs of which are connected respectively to the first output of the decoder of the zone number and the output of the second element I, and the third input to the second input of the block, the first and second inputs of the second element I connected respectively to the first input of the block and the second output of the decoder of the zone number, the input connected to the first output of the zone number counter, the group of inputs of which is the group of block inputs, and the first and second outputs, respectively, the first and third outputs of the block, the first and second outputs of the first And element are accordingly 5 second and fourth block outputs. the third outputs of the zone number counter, the zone number decoder and the first element I are the corresponding outputs from the group of outputs of the block. 4. Device according to claim 1, characterized in that the storage time monitoring unit contains a register of the zone number, the first and second inputs and the output of which are connected respectively to the first and second inputs of the block and the first input of the decoder of the time code registers, the output and second input of which connected, respectively, to the output of the block and the output of the register for inverting the storage time code, the first input connected to the output of the first ele / iS / roMyS / ffj7Oftyff / i S / GOK / o And, the first and second inputs of which are connected respectively to the outputs of the counter of the number of zones and the second element I, are first input connected to the output of the control register. the time code, the second inputs of the register for inverting the time code of the storage and the second element AND, the input of the counter of the number of zones and the third input of the first element AND are the corresponding inputs from the group of inputs of the block. Sources of information taken into account in the examination. 1. USSR author's certificate 451076, cl. Ci 06 F 3/04, 1970 (prototype) .- (rig i 962909 f / rr / romf S fff / fony 9 ffm / f Offer fO  S ffffy 5 O / Tf S770fia3 ffm S / ro / ro fO (pua.4