SU960653A1 - Device for measuring frequency signal fluctuation - Google Patents

Description

The invention relates to electrical measuring equipment and can be used in systems for measuring fluctuations of frequency signals in a wide frequency range.

Known percentage frequency meter containing the reference frequency generator, a frequency divider, a counter, two e frequency divider, two pulse shaper 1.

The disadvantage of this frequency meter is its complexity, due to the presence of two frequency dividers and two pulse formers.

The closest to the proposed device is a frequency signal fluctuation fluctuation meter, comprising a clock pulse generator, a counter, and a static register.

The device allows binary code to receive signal fluctuations from the sensors in accordance with the following expressions G

+ KG,

fcpT

ufT G / 2, where fpp is the average input frequency

T is the pulse duration of the master multivibrator

G is the capacity of the full-length one

binary counter; K - integer overflow

counter;

af is the input fluctuation. signal 2.

The main disadvantages of the meter include the ability to use the full capacity of the meter.

10 only in the case of the multiplicity of the fluctuation part of the signal to its center frequency, fcp (1 + 2K) df, but this is a special case, and in the rest - if the inequality of if-T G / 2,

15 i.e. measurement accuracy is reduced; the same speed for signals with different frequency fluctuations due to the impossibility of adjusting the pulse duration: waiting for the multivibrator and the generator frequency (in the known scheme), as a result of which the number of measurements per unit time is determined by the signal with the smallest fluctuation

25 for signals in a wide frequency range are characterized by losses in speed, the presence of redundant elements in the circuit.

The purpose of the invention is to improve the measurement accuracy.

The goal is achieved by the fact that a device for measuring fluctuations of frequency signals, containing a clock-pulse generator, a counter and a static register, the information inputs of which are connected to the outputs of the counter, and the outputs of the static register are connected to the output buses of the device, the element e, holders and a controlled frequency divider whose input is connected to the output of a clock pulse generator, and the output to a control input of a static register and to the input of a delay element whose output is connected to ravl yuschemu entry counter, the count input of which is connected with an input device bus.

The drawing shows a block diagram of the device.

The device consists of a generator of 1 clock pulses, a controlled divider 2, a delay element 3, a counter 4, a static register 5, a driver block b.

The device works as follows.

The sequence of clock pulses from generator 1 is fed to the input of controlled divider 2, the division factor of which is chosen so that the average frequency of the input signal corresponds to the fillings of half the capacity of counter 4, and the entire range of deviations of the frequency of full capacity of counter 4, i.e.

  G / 2,

where uf is the fluctuation of the measured input signal; TD is the measurement time specified by

j divider;

G 2 - the capacity of the binary counter; N is the number of counter bits.

On-the-counter input of the counter 4 receives a frequency signal, and on the information inputs there is an additional binary code of the number A defined by the following expression

+ A

K-G +

GSR

where K is an integer overflow

counter selected from the ratio

G

f-t

fcp -TA - G + 1

SR A

fKf G

substitution of extreme values

- one.

 0-, A,

-g

When a controlled de-energizer 2 is triggered, a pulse is formed at its output, which through the delay element 3 is fed to the control input of counter 4. The outputs of counter 4 are set in accordance with the level at the information inputs and for a time Td goes direct several counter overflows occur 4. Signal from controlled

the divider 2, arriving at the control input of the static register 5, transfers information from counter 4 to it for each previous measurement cycle.

Thus, it is recorded

only the fluctuation part of the measured signal, and the measurement accuracy is improved by using the full capacitance counter, adjusting the division factor, which determines the number of measurements per second, ensures maximum performance in a wide frequency range and increases reliability

by simplifying the scheme.

Claims (2)

1. Ermolov R.S. Digital frequency meters. L., Energie, 1973, p. 2b. 2. Authors certificate of the USSR 533878, cl. G 01 R 23/10, 1974. fex oInputs