SU959111A1 - Device for registering single-occurance processes - Google Patents

Description

(54) DEVICE FOR REGISTRATION OF SINGLE. PROCESSES 1 The invention relates to computing and measuring technology and can be used to investigate the form of a single process and measure its parameters. A device for registering single processes is known, comprising an amplifier whose output is connected to the input of an analog-digital converter, a first memory block whose input is connected to the first output of the control unit, and the outputs are connected to the inputs of the decoder whose outputs are connected to the inputs of the first group of the display unit , the inputs of the second rpiynnbi of which are connected to the outputs of the scanner, the input of which is connected to the first output of the clock generator and the first input of the control unit, the second output of which is soy Dinen with the input of the clock pulse generator, the second output of which is connected to the input of the sweep duration indicator 1. The disadvantage of this device is the large error in the registration of the one-time process form, when the experimental conditions are aggravated by the presence of noise components, i.e. during the recording of the signal and noise on the unit the displays are outputted with discrete readings from which it is difficult to judge the shape of the process under study, and all the more so to measure its parameters. Closest to the present invention is a device comprising an amplifier, the output of which is connected to the input of an analog-digital converter and the input of a message boundary selection block, the first and second switches, the group inputs of which are connected to the outputs of the analog digital converter and the first memory block inputs, group inputs of which connected to the outputs of the third switch, the inputs of the group of the third switch. connected to the outputs of the second and third memory blocks, the inputs of the groups of which are connected respectively to the outputs of ne first- and second-koymutatorov, inputs of the first, second and third storage units, the first, second and third switches are connected to the outputs of groups of the control unit respectively, outputs of the first memory block connected to

the inputs of the decoder, the outputs of which are connected to the inputs of the first group of the display unit, the inputs of the second group of which are connected to the outputs of the scanner, whose input is connected to the first output of the clock generator and the first input of the control unit, the second input of which is connected to the output of the message boundary selection block, output the control unit is connected to the input of the clock generator, the second output of which is connected to the indicator of the sweep duration 2.

A disadvantage of this device is the loss of half of the information in the process of registering the signal under investigation due to the exclusion of individual samples due to the limited amount of memory, which also introduces an additional error.

The purpose of the invention is to increase the reliability of the device by restoring signals in the process of adaptation to their duration.

The goal is achieved by the fact that in the device containing an amplifier connected to an analog-digital converter and a message boundary selection block, the first and second memory blocks, the first and second switches, the first inputs of which are connected to the first and second outputs of the decoder control block, the outputs which are connected to one input of the display unit, the other inputs of which are connected to the outputs of the scanner, the input of which is connected to the first output of the clock generator and to the first input of the control unit, the second input of which is connected to the output of the message boundary selection unit, and the third output of the control unit is connected to the input of the clock pulse generator, the second output of which is connected to the input of the sweep duration indicator, the first, second, third and fourth registers, the first and second adders, the formation unit are entered address code, the outputs of the analog-digital converter connected to the inputs of the groups of inputs of the first and second registers, the inputs of which are connected to the fourth and fifth outputs of the control unit, the outputs of the first and the second registers are connected to the corresponding inputs of the first adder, the outputs of which are connected to the inputs of the first group of the first switch, the inputs of the second group of the first switch are connected to the outputs of the second adder, the outputs of the first switch are connected to the inputs of the first groups of the first and second memory blocks, the inputs of the second groups which are connected to the outputs of the first and second groups of the block forming the address code, respectively, the third output of the block forming the address code with the third input of the control block, the sixth output of which o connected to the input of the address code generation unit; the outputs of the first and second memory blocks are connected to the outputs of the first and second groups of the second switch, the outputs of which are connected to the inputs of the decoder and to the inputs of the groups of inputs of the third and fourth registers whose inputs are connected to the seventh and eighth outputs the control unit, the outputs of the third and fourth registers are connected to the corresponding inputs of the second adder.

In addition, the address code generation unit contains the first and second triggers, the third and fourth switches and the first and second counters, with the inputs of the first and second triggers, the first input of the third switch and the first input of the first and second counters being the inputs of the code generation unit, the first output the first trigger is connected to the second input of the third switch and the first input

the fourth switch, the second output of the first trigger is connected to the third input of the third switch and the second input of the fourth switch, the first output of the second trigger is connected to the third input of the fourth switch, the fourth and fifth inputs of which are connected to the first output of the first and second counters, the second output of the second trigger connected to the fourth input of the third switch, the outputs of which are connected to the second input of the first and second counters, the outputs of the group of the first counter and the first output of the fourth switch in The first output of the address code generation unit, the outputs of the second counter group and the second output of the fourth switch are

5, the second output of the address code generation unit, and the first outputs of the first and second counters are the third output of the address code generation unit.

FIG. 1 shows the structural scheme of the proposed device; in fig. 2 is a block diagram of an address code generation unit; in fig. 3 is a block diagram of the control unit.

A device for registering one-time processes contains an amplifier 1, an analog-to-digital converter 2, a message boundary selection block 3, a first register 4, a second register 5, a first, an adder 6, a first switch 7, a first memory block 8, a second memory block 9, unit 10 ° of forming the address code, second switch 11, third register 12, fourth register 13, second adder 14, first decoder 15, display unit 16, scanner unit 17, control unit 18, clock generator 19, sweep duration indicator 20, first trigger 21, second trigger ger 22, third switch 23, first counter 24, second counter 25, fourth switch 26, third trigger 27, fourth trigger 28, fifth trigger 29, second decoder 30, third counter 31, first driver 32, second driver 33, third driver 34, element OR 35, the sixth trigger 36, the elements And 37 and 38, the fourth counter 39.

The principle of operation of the device is as follows.

The input signal, together with interference, amplified by amplifier 1, is fed to analog-to-digital converter 2 and, simultaneously, to block 3 for extracting messages. The signal characterizing the start of the process, from the message boundary selection block 3, is set through the control block 18, the clock pulse generator 19 to the maximum frequency generation mode. This frequency passes to control unit 18, where it is temporarily allocated to the cycles of writing the encoded values of the input signal from the outputs of the analog-digital converter 2 to memory registers 4 and 5. The average values of the pair of samples taken are from the outputs of the first the adder 6 averager through the first switch 7 to the inputs of both blocks 8 and 9 of the memory. In this case, the control unit 18 sets the first memory block 8 to the information recording mode with the help of the address code generation unit 10, and the second memory block 9 into the read mode. From this moment on, the first memory block 8 is filled with average values of successively taken in pairs adjacent ordinates of the recorded process with the maximum possible frequency of the clock pulse generator 19.

The impulse, indicating the beginning of a single signal, comes from block 3 messages and sets the third trigger 27 to one state on the forward output. This command enables the clock pulse generator 19 and the arrival of the maximum recording frequency. At the same time, the fourth trigger 28, which by its output sets the first trigger 21 and fifth flip-flop 29 to the direct outputs and keeps them in this state until the first overflow of the memory block 8, is switched by the start pulse. In this way, passing through the first switch 7 to the inputs of the block 8 tsia through the first switch 7 only the mean values of the new samples and selecting the address by the counter 24 as a sequence of 1, 2, 3, 4, 5, ..., 16 during the initial period of averaging in the operation mode “Record 8 memory block. Taking new samples is performed using the clock from the decoder 30, spaced apart by one period of the fundamental frequency. The frequency comes from the clock pulse generator 19 and ensures the operation of the counter 31. The operation mode of the memory blocks 8 and 9 is set by the sixth trigger 36, which is triggered at the first moment from the start pulse coming from the first imager 32 through the OR 35 element. the pulse confirms the state of the first trigger 21 at the counting input and records the first range in the fourth counter 39. The latter is used both to control the clock pulse generator 19, i.e., a sample of the averaging interval, and to determine the duration range in which the signal under study is located.

With the arrival of the first overflow pulse from the memory block 8 supplied through the second driver 33 to the fourth trigger 28, the prohibition on the first trigger 21 and the fifth trigger 29 is lifted and the operation of their counting inputs is allowed. The fifth trigger 29, with its outputs, starts to switch the first switch 7, passes the average values of the new samples to the memory input, then the average values of the average samples. Switching is carried out in the middle of the averaging interval. The first trigger 21 is switched by the overflow pulses of the first and second counters 24 and 25, thereby alternating their function or address selection sequence. These same overflow pulses, coming from the outputs of the second and third drivers 33 and 34, through one of the AND schemes and the OR 35 circuit, alternately switch the sixth flip-flop 36 and change the range of the fourth counter 39. The outputs of the fifth flip-flop 29 control the second switch 11, passing information from one or the other of blocks 8 and 9 of memory.

Claims (2)

Simultaneously with the control unit 18, the unit for generating the address code 10 is operating. The impulse corresponding to the beginning of the input signal coming from the control unit 18 sets the first trigger 21 to a single state on the forward output, which allows the maximum frequency to pass through the third switch 23 to the input of the first counter 24 and connect the high bit of the first counter 24 through the fourth switch 26 to memory block 8. In this mode, the usual, sequential enumeration of the addresses O, 1, 2, 3, 4, 5, ..., 16 is performed. In this case, the memory block 8 operates in the information recording mode. After selecting the last address 16, the operation mode of the memory blocks 8 and 9 is changed. The memory unit 8 is switched to the information reading mode, and the memory unit 9 is in the write mode. The first trigger 21 remains in its previous state, which ensures the same sequence of address selection by the first counter 24 and another for the second counter 25. The latter in this case operates from the second trigger 22, which switches with the maximum frequency. It turns out that the low-order bit of the second counter 25 changes twice as slowly as the main recording frequency, while the most significant bit, on the contrary, with each beat of this frequency. This mode is applied to the input of the second counter 25 through the third switch 23 of the frequency from the output of the second trigger 22 instead of the maximum frequency and replacing the high bit of the second counter 25 with the output signal of the second trigger 22. Thus, the address selection sequence is provided by the second counter 25 of the form 9; one; ten; 2; eleven; 3; ..., .16, 8. After the next memory overflow, the operation mode of the counters 24 and 25 changes. The first counter 24 gives the sequence of selecting the address 9; one; ten; 2; eleven; 3, ..., 16, 8, and the second counter 25 sequence of the form 1; 2; 3; four; five; 6, ..., 16. In this case, the memory block 8 operates in the information recording mode, and the memory block 9 in the read mode. And such a sequence for changing the r -: - the first and second counts are shown;;: ixoB 24 and 25 occur after each memory full. It should be borne in mind that each overflow reduces the frequency of recording twice The indicated algorithm of operation is repeated until the impulse of the end of the input signal comes from block 3 of the selection of message boundaries. It switches the third trigger 27 to the zero state on the forward output and thereby switches the device from the registration mode to the information display mode, and in block 20 the sweep duration is indicated. Improving the reliability of recording single signals is ensured by the fact that, along with filtering at each averaging interval, it is possible to completely record the input signal evenly throughout the memory length and thus avoid information losses associated with overshoot. Claim 1. A device for registering one-time processes, comprising an amplifier connected to an analog-digital converter and a message boundary extraction unit, first and second memory blocks, first and second switches, the first inputs of which are connected to the first and second outputs of the block, control, the decoder, the outputs of which are connected to one input of the display unit, the other inputs of which are connected to the outputs of the scanner, the input of which is connected to the first output of the clock generator and to the first in One control unit, the second input of which is connected to the output of the message boundary selection unit, and the third output of the control unit is connected to the input of the clock generator, the second output of which is connected to the input of the sweep duration indicator, characterized in that, in order to increase the reliability of the device, the first, second, third and fourth registers are entered, the first and second adders, an address code generation unit, the outputs of the analog-to-digital converter connected to the inputs of the input groups of the first and second regis The inputs of which are connected to the fourth and fifth outputs of the control unit, the outputs of the first and second registers are connected to the corresponding inputs of the first adder, the outputs of which are connected to the inputs of the first group of the first switch, the inputs of the second group of the first switch are connected to the outputs of the second sum-ator, outputs the first switch is connected to the inputs of the first groups of the first and second memory blocks, the inputs of the second groups of which are connected to the outputs of the first and second groups of the address code generation unit, respectively, t The output of the address code generation unit is connected to the third input of the control unit, the sixth output of which is connected to the input of the address code generation unit, the outputs of the first and second memory blocks are connected to the inputs of the first and second groups of the second switch, the outputs of which are connected to the decoder inputs and to the inputs groups of inputs of the third and fourth registers, the inputs of which are connected to the seventh and eighth outputs of the control unit, the outputs of the third and fourth registers are connected to the corresponding inputs of the second adder. 2. The device according to claim 1, characterized in that the block for generating the address code comprises first and second triggers, third and fourth switches and first and second counters, with the inputs of the first and second triggers, the first input of the third switch and the first input of the first and second counters are the inputs of the address code generation unit, the first output of the first trigger is connected to the second input of the third switch and the first input of the fourth switch, the second output of the first trigger is connected to the third input of the third switch and to the second in In the course of the fourth switch, the first output of the second trigger is connected to the third input of the fourth switch, the fourth and fifth inputs of which are connected to the first output of the first and second counters, the second output of the second trigger is connected to the fourth input of the third switch. the outputs of which are connected to the second input of the first and second counters, the outputs of the first counter group and the first output of the fourth switch are the first output of the address code generation unit, the outputs of the second counter group and the second output of the fourth switch are the second output of the address code generation block, and the first outputs The first and second counters are the third output of the address code generation unit. Sources of information taken into account in the examination 1. Hormon, Connelly. A simple system for digitally recording data from a pulsed experiment to study the kinetics of chemical reactions. - "Instruments for Scientific Research, 1978, No. 8. 2. USSR author's certificate number 557392, cl. G About K 15/18, 1975 (prototype). 6s) d 1 Gm b / ya Iffig .g K ffjiOMy 6 J r Nblonu 7