SU983742A1 - Device for registering single signals - Google Patents

Description

(5) DEVICE FOR REGISTRATION OF SINGLE SIGNALS

Claims (2)

The invention relates to information and measurement technology and can be used to study single signals.  A device for recording single-signal signals is known, comprising an analog-to-digital converter, memory blocks, counters, circuits. clock pulse generator 1.  A disadvantage of this device is that the registration of single signals with a wide range of changes in the duration t leads either to a loss of information (misses) when the duration of the recorded signal t is longer than the duration of the sweep tp, or to a decrease in accuracy when the duration of the sweep tp is longer Close to the proposed technical entity is a device for recording single signals, containing an analog-converter converter, a control unit, circuits Alignment, counters, and memory blocks C2j pulse generator.  A disadvantage of the known device is the loss of information (miss) caused by a single one. the selection of the end of the signal when it appears multiple times under conditions of a priori uncertainty about the duration and spectrum of the signal under study.  The aim of the invention is to improve the accuracy of the device.  The goal is achieved by the device for registering single signals containing a level quantizing unit whose output is connected to the input of an analog-digital converter, a control unit whose first and second outputs are: connected to the First input of the first memory unit and the input of the first counter, respectively and the first input is with the output of the pulse generator, and the display unit, the inputs of which are connected to the outputs of the first memory block and the first counter, contains the first comparison circuit, the first input and output which are connected to the output of the analog-to-digital converter and the second input of the control unit, respectively, the first register whose inputs are connected to the outputs of the analog-digital converter and the first comparison circuit, and the output to the second inputs of the first comparison circuit and the first memory block, respectively, the second the counter, the inputs of which are connected to the output of the pulse generator and the third output of the control unit; the second memory block, the first and second inputs of which are connected to the first output of the control unit and the output of the second counter ka, the second comparison circuit, the first input and output of which are connected to the output of the first counter and the third input of the control unit, respectively, the subtractor, the first input and output of which are connected to the output of the second memory unit and the second input of the second comparison circuit, respectively, the third counter, the input and output of which are connected to the fourth output of the control unit and the second input of the subtraction unit and the sampling unit, the inputs and output of which are connected to the third output of the control unit, the outputs of the first and second comparison circuits and three im inputs of the first and second memory blocks, respectively.  In addition, the sampling unit contains a fourth counter, the first input of which is connected to the first inputs of the fifth counter, first switch, second register, frequency divider, second switch, reversible counter and is the first input of the block, the second input is with the second input p of the counter and the output of the third comparison circuit, and the output with the second input of the frequency divider and the input of the first decoder, the outputs of which are connected to the first inputs of the first adder and the third comparison circuit and the first and second inputs of the third comm The third input of which is connected to the first input of the third register, the second input of the reversing estimator and the output of the fourth comparison circuit, the fourth input of the switch is connected to the third input of the reversible counter and the output of the second decoder, and the output to the first input of the third adder whose output is connected with the second input of the second switch, and the second input with the second input of the third register, the first input of the fourth adder and the output of the reversible counter, the fourth and fifth inputs of which are connected to the output of the second the switch and the first output of the frequency divider, the third return of the second switch is connected to the output of the third register, the third and fourth inputs of the frequency splitter are the second and third inputs of the block, respectively, and the second output is connected to the third input of the fifth counter, the output of which is connected to the input of the second accumulator whose output is connected to the second input of the first adder, the output of the first adder is connected to the second input of the third comparison circuit and the second input of the first switch, which is connected to the second input of the tvertogo adder whose output is connected to the input of the second decoder, the first input of the fourth comparing circuit, the second input and the second register unit is output, and the output of second register is coupled to the second input of the fourth comparing circuit. .  FIG.  1 shows a block diagram of the device; in fig.  2 - the waveform and the process of its registration; FIG. 3 is a table of values; in fig.  signal reproduction example.  The device contains a level 1 quantization unit (input) signal, an analog-digital converter 2, a first comparison circuit 3, a first register, a first memory block 5, a display unit 6, a first counter 7, a second comparison circuit 8, a control block 9, a generator 10 (clock) pulses, second counter 11, second memory block 12, subtraction unit 13, fourth counter 1, sample selection block 15, third counter 16, third register 17, first decoder 18, fifth counter 19, first switch 20, the fourth code comparison circuit 21, the second register 22, the second adder 23, he first adder 2, a third comparison circuit 25 ends the fourth adder 2b, the frequency divider 27, a third switch 28, a third adder 29, a second switch 30, down counter 31, a second decoder 32, 59,837 device operates as follows.  Before starting work using the control unit 9 (Fig.  1) the second 11 and fourth counters, as well as the reversible counter 31 and the fifth counter 19 are zeroed out. The input signal x (t) is amplified, converted into code in the analog-to-cis converter 2 with the maximum frequency fd supplied to the first circuit 3 comparison, where it is compared with the discrete value of signal x (t, coming from the first register i.  At the moment-fc-intersection of the level of quantizations studied by the signal (at the moment of changing the code at the output of the ADC 2 (Fig.  2a) the first 5 and second 12 memory blocks are switched to the recording mode and. the code is being written. signal x (t) to the first memory block 5 and to the first. register 4, and at the time of counting t.  - in the second memory block 12.  At the end of the recording of the values of the signal x and txt, the playback mode begins and lasts until the appearance after the second discrete value of the signal x ,, (t).  The time interval At C between the appearance of two co. The next values of the signal x, (t) and x (t) turn out to be less than the total time interval L tj of the 1c recording cycle and the playback cycle t.  Therefore, no recorded signal value has time to be displayed (reproduced) from blocks 5 and 12 of memory.  Thus, it receives, as it were, a continuous recording mode and at the time t2 of the intersection, the quantizations of the signal under study (at the time of code change at the output of the A / D converter 2) are examined (Fig.  2c) blocks 5 and 1.  the memory is transferred to the recording mode and the signal code x is recorded in the first memory block and in the first register i, and at the time of taking the reference t ,, in the second memory block 12.  At the end of the recording of the values of the biases, the playback mode starts and lasts until the next value of the signal x appears. , (ta).  The time interval At, 2 t "- t turns out to be less than the time interval Aty, therefore, no recorded signal value has time to be displayed (played back) from blocks 5 and 12 of memory.  Thus, a continuous recording mode of 26 s is obtained again, as it were, and at time t (yig.  2a) Blocks 5 and 12 of the memory are switched to the recording mode.  and t. d.  After recording the values of the signal x. , r is the playback mode.  time interval At t. - tn is greater than the time interval ut ,, therefore the recorded values of the signal in a certain sequence are output from blocks 5 and 12 of the memory.  Next, the polynomial restores the zero order and displays the shape of the registered part of the signal x (t).  In this case, the signal code stored in the first memory block 5, in a certain sequence, is output to the display unit 6, determining the position of the light point vertically.  At the same time, from the second memory unit 12, the corresponding code of the sampling moment is fed to the image recovery and shift unit, consisting of the first 7 and third 16 counters, subtraction unit 13 and the second comparison circuit 8, In teLi (where At is the interval sampling) playback cycles the signal code x is shifted along the horizontal axis by - discrete valuesAt. . .  SRI and on the display unit 6 highlight-- (points with equal amplitudeOt / 7 - t / l Then, during t playback of playback on block 6 of the display, the price will be highlighted with equal amplitude and x, j, then next- to ti blowing points amp Pitudoi At and so on d.  At the moment t, - the signal intersection of the signal vt) of the quantization level Xd, the blocks 5 and 12 of the memory are switched to the recording mode, and so on. P.  Thus, when registering a signal x (t), the time interval A t between the appearance of two-adjacent samples can be less than the sum of the recording cycle time, and the reproducing cycle, more than the sum of recording t of the recording cycle time t and the playback cycle tng.  In the first case, continuous recording is performed, in the second, after recording, the recorded values of the signal in a certain sequence are reproduced, and the registered part of the signal is restored and displayed.  At the instant tj of the memory overflow, the values of the signal x, t are eliminated, and the subsequent banners of the signal x are written in their place. , t. -.  (FIG. 2b) When the recording of the values of the cy | - X and IL blocks is completed, the blocks 5 and 12 of the memory are switched to the playback mode.  At the same time, in a certain sequence of blocks 5 and 12 of the memory, the recorded values of the signal are output and on display unit 6 highlights with the restored signal.  At the instant of the tyg intersection of the signal x (t) of the quantization level (at the moment of changing the code at the output of the ADC 2), the values of the signal x, t are eliminated, and the values of the signal x are recorded in their place. , t, o.  At the end of the recording of the values of b | - nala XQ, -t Q blocks 5 and 12 of the memory are transferred to the playback mode, and so on. e After recording the last signal value, a continuous process of reproducing, restoring and displaying the signal x (t) begins.  Consider how the record position number is selected. si and playback of the recorded part of the signal (all signal).  The device implements the selection of the position number O.  when recording according to an expression taken from the table (Fig.  3) P p h - 2 where p (1t2CH i 0,1,2 ,. . . , (1) 1 h o, n 1.  Since in the expression (1) there are two variables K and i, it is possible to use a number of options for the implementation of the selection of the position number O.  when recording.  In this case, the variant is realized, where n const, i var after i changes from O to its maximum value {- - O n increases by one. Zi After n reaches its maximum value (2-t2), an increase occurs. per unit K and all the processes are repeated until the signal x (t) under investigation ends.  Consider the reproduction of information when outputting from blocks 5 and 12 of memory.  9 28 When writing the first value of the code of the signal x, and the moment of counting is "I, the zero code from the fourth counter 1t is fed to the input of the first decoder 18, which in this case performs the operation of raising to the power of 2 in binary code.  The exception is minus the first degree (K 0, and the result of the erection is zero.  Through the third switch 28, a binary code occurs, corresponding to one unit (21, since K O, and fed to a third adder 29, where it is added to the zero code received from the output of the reversing counter 31.  The code from the third adder 29 passes through the second switch 30 and enters the fourth input of the reversing counter 31, but is not installed in it, since in the second MOM 2 -t term, the first value, therefore, the second Slag should be zero ( (1) - The output code of the reversible counter 31 is set in the third register 17 and G1 is fed to one of the inputs of the fourth adder 26, where it is added together with the first term of expression (1).  Let us now consider how the first term of expression (1) is obtained.  The zero code from the fifth counter 19 goes to one of the inputs of the second adder 23, the second input of which constantly receives the code of unit 1.  The unit code from the output of the second adder 23 is fed to one of the inputs of the first adder 2k, to the other input of which the zero code arrives (2} from the first instrument 18, since K P.  Further, the unit code from the first adder is supplied to the third comparison circuit 25, where it is compared with the unit code supplied from the first decoder (2) 18.  The third comparison circuit 25 in this case does not make any changes to the operation of the device, since it generates a pulse at the moment when the code from the output of the first adder 2 exceeds the code from the first decoder (l) 18.  The code from the first adder 2 also passes through the first switch 20 and enters the second input of the fourth adder 2b. From the output of the fourth adder 26, the code number of the memory position O into which new information is written, sets from to the second register 22, and also enters the blocks 5 and 12 memories.  When recording the values of the signal x.  the third commutator switch "1o" passes the binary code corresponding to one (Z), since it is KO and goes to the third adder 29, where it is added to the zero code received from the output of the reversible counter 31.  The code from the third adder 29 passes through the second switch 30 and is installed in the reversible counter 31 by a pulse from the divider 27. frequencies. Next, the unit code from the output of the reversible counter 31 is set to the third register 17 and is fed to the first input of the fourth adder 2b, the second code to the second input of the unit is also received, since the state of the fifth counter 19 has not changed.  The two code from the fourth adder 26 is set to the second register 22, and also goes to the blocks 5 and 12 of the memory. Next, the process of selecting the position number O in writing is similar.  When recording the 17th () value of the signal x and the time of reference, t. In the case of memory overflow (K 1), the fifth counter 19 counts the pulse from the frequency divider 27, which the counter 31 inverted. .  The code arriving at the input of the reversing counter 31 from the second switch 30 is not set, therefore a zero code arrives at the first input of the fourth adder 2b, and a two at the second input.  From the output of the fourth adder 26, the deuce code is set to the second register 22, and is also supplied to the blocks 5 and 12 of the memory.  Then, the position numbers Q are formed in a similar way in accordance with the expression (1).  When playing on the second input of the fourth adder 2b, the unit code 1 constantly passes through the first switch 20.  Thus, the implementation of the first term for the expressions from the table is obtained (FIG.  H).  The implementation of the second term for expressions from the table (FIG.  3) we obtain in the same way as the second term when writing in expression (1).  The difference is that after the first value the position number is greater than the position number 0 at which the signal registration process stopped, with the fourth comparison circuit.  codes 21, a control signal AND 1 is generated, which transitions from the implementation of the first expression of the table (FIG.  3) to the second expression.  Position number 0 (/) is stored in the second memory register 22.  The control signal AND 1 firstly sets in the third memory register 17 the counter counter code 31 necessary for the transition from the implementation of the second expression of the table (Fig 3) to the implementation of the third expression, secondly it controls the third switch 28 through which passes from the output of the first distributor 18 code 2, and not 2, as before.  Thus, we obtain the sum (.   +).  This is nothing more than the first value of the second term for the second table (FIG.  3), since K - 1 2 + 2 (2Y + 1).  The transition from the implementation of the second expression of the table (Fig.  3) the third is as follows.  After Qy Q second decryption. Rator 32 controls the third switch 2B, which in this case passes the code. At the same time, a 2 v code is set to the reversing counter 31 via the second switch 30 of the third G / memory register, which is then summed with code 2 on the third adder 29, and re-installed in the reversible counter 31, thereby obtaining the first value of the second term for the third 2 (SG + 1).  Thus, at one of the inputs of the fourth adder 26, we obtain the first term for the expressions of the table (FIG. 3), and at the other, the second term. Further, the code of the position number from which the information is to be output is sent to the first 5 and second 12 memory blocks.  After Qxj Qif, t. e.  the last value of the signal and time are output, the sequence of output of discrete values is repeated, t. e.  first, it corresponds to the first expression of the table (yig.  3, and then to the second, third, first, and second, and this is due to the fact that after Qv Qip the reversible counter is 31 inches (the fourth is the code comparison circuit 21, and this represents nothing more than the first value of the second term in the first expression of the table (FIG.  3} The elimination of misses is achieved by the fact that after each new recorded signal value and time, the playback mode begins.  When switching from the playback mode to the recording mode, you need to remember the position number at which the recording process stopped. Since the playback mode does not affect the first term of expression (1), it is enough to remember the second term 2 ii of this expression (1), which from reproduction and recording is set to the reversible counter 31 via the second switch 30 This third register registers the number of registered 1: -1X samples of the test / signal x (-t may exceed the number of samples sent to block 6 from Since the memory capacity exceeds the capacity of the matrix 5 memory block, Thus, on the display unit 6, the part f of the signal x (t) is highlighted. To view the waveform of the whole signal x (-t), the image is shifted by the unit 13 subtraction and third counter 16,.  So, the time taken to read (the time code determines the horizontal position of the light point; If you increase or decrease this code, then the corresponding light point will move to the right on the screen of the display unit b, then the left If you increase or decrease the code of the sampling moments of the entire signal x (-fc} by the same amount S, the entire image is shifted by the magnitude. Using control block 9, you increase or decrease the code of the third counter 1b, which goes to block 13 the second input from the second memory unit 12 receives the code of the sampling times. Thus, the image is shifted.  The recovery of the registered signal, a part of the signal, is carried out by a zero-order polynomial, which is implemented on the first counter 7 and the second code comparison circuit 8.  The first counter 7 receives the playback frequency pulses.  The code from the output of the first counter 7 is fed to the display unit 6, defining the light halving and 1 point of the point horizontally, as well as to one of the inputs of the second comparison circuit B, to the second of which is from block 13. Neither does the shifted code of the moment of counting.  The code of the first counter 7 is incremented by one with each playback pact, and the code X ;; (Fig.  ), defined kchi. The position of the light and (its points vertically, remains constant.  Therefore, on the display block b, it will successively highlight, - i -). points with equal amplitudes.  .  At the moment (Lig.  ) equality of codes, 1 is sent to the second code comparison circuit 8, the signal necessary for Lorming the next position number of the memory Q is received from the frequency divider 27.  This signal also enters the control unit 9, due to which the subsequent registered value of the signal x, y and time-t-j -t is output. Now on the display unit 6, the points with equal amplitudes X and 4 and so on are displayed. d.  The device eliminates errors when registering single signals and the spectrum of the signal under study.  The outcome of this is to expect a large economic effect, especially in the study of hardly repeatable ones.  and expensive 14 their experiments.  Claim 1.  A device for registering single signals, containing a signal quantization unit with a level, the output of which is connected to the input of an analog-digital converter, a control unit, the first and second outputs of which are connected to the first input of the first memory block and the input of the first counter, respectively, and the first input - with the output of the pulse generator, and the display unit, the inputs of which are connected to the outputs of the first memory block and the first counter, differing in that, in order to increase the accuracy of the device, it contains the first circuit Yeni.  the first input and output are connected to the output of the analog-digital converter and the second input of the control unit, respectively, the first register, the inputs of which are connected to the outputs of the analog-digital converter and the first comparison circuit, and the output. - with the second inputs of the first comparison circuit and the first memory block, respectively, the second counter, the inputs of which are connected to the output of the pulse generator and the third output of the control unit, the second memory block, the first and second inputs of which are connected to the first output of the control unit and the output of the second counter ,. the second comparison circuit, the first input and output of which are connected to the output of the first counter and the third input of the control unit, respectively; the subtraction unit, the first input and output of which are connected to the output of the second memory block and the second input of the second comparison circuit, respectively, the third counter, input and output which are connected to the fourth output of the control unit and the second input of the subtraction unit and the sample selection unit, the inputs and output of which are connected to the third output of the control unit, the outputs of the first and second comparison circuits and the third in odes first and second memory blocks, respectively.   2. The device according to claim 1, of tl and h. Is that the sampling unit contains a fourth counter, the first input of which is connected to the first inputs of the fifth counter, first switch, second register, frequency divider The second switch, the reversing counter is the first input of the unit, the second input is with the second input of the fifth counter and the output of the third comparison circuit, and you go with the second input of the divider and often the input of the first decoder whose outputs are connected to the first inputs of the first adder and the third circuit and the first y and the second inputs of the third switch, the third input of which is connected to the first input of the third register, the second input of the reversible counter and the output of the fourth comparison circuit, the fourth input of the switch is connected to the third input of the reversible counter and the output of the second decoder, and the output to the first input of the third adder the output of which is connected to the second input of the second switch, and the second input to the second input of the third register, the first input of the fourth adder and the output of the reversible counter, the fourth and fifth inputs to The second input of the second switch is connected to the third register output, the third and fourth inputs of the frequency divider are respectively the second and third inputs of the block, and the second output is connected to the third input of the fifth counter, the output which is connected to the input of the second adder, the output of which is connected to the second input of the first adder, the output of the first adder is connected to the second input of the third comparison circuit and the second input of the first output of which A mutator is connected to the second input of the fourth adder, the output of which is connected to the input of the second decoder, the first input of the fourth comparison circuit, the second input of the second register is the output of the block, and the output of the second register is connected to the second input of the fourth comparison circuit. Sources of inLormation taken into account during the examination 1. Hormone, Connelly. A simple system for the cyclical recording of pulsed data for studying the kinetics of chemical reactions. Instruments for scientific research, 1972, No. 8 .. .. USSR Author's Certificate No., cl. G, K K 15/20, 1975 (prototype). with.) jt- i, i ti f, t in t (tjist7tjt ,, f 5 t5 tg t,} i t ,, t, jf, 5e, 7 t, j Soenpou) 8edenue Record - --4jt tiit: i- rj L J Fig.Z